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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count

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This commit is contained in:
Blaise Tine
2020-11-02 01:50:12 -08:00
parent 3fe31fc337
commit 5be1d85648
39 changed files with 1145 additions and 1322 deletions
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4
hw/rtl/VX_core.v
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@@ -260,7 +260,7 @@ module VX_core #(
.core_dcache_req_if (arb_dcache_req_if),
.core_dcache_rsp_if (arb_dcache_rsp_if),
// Dram <-> Dcache
// DRAM <-> Dcache
.dcache_dram_req_if (dcache_dram_req_if),
.dcache_dram_rsp_if (dcache_dram_rsp_if),
.dcache_snp_req_if (dcache_snp_req_if),
@@ -270,7 +270,7 @@ module VX_core #(
.core_icache_req_if (core_icache_req_if),
.core_icache_rsp_if (core_icache_rsp_if),
// Dram <-> Icache
// DRAM <-> Icache
.icache_dram_req_if (icache_dram_req_if),
.icache_dram_rsp_if (icache_dram_rsp_if)
);