wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count

Browse Source
This commit is contained in:
Blaise Tine
2020-11-02 01:50:12 -08:00
parent 3fe31fc337
commit 5be1d85648
39 changed files with 1145 additions and 1322 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
hw/rtl/VX_csr_data.v
View File

@@ -17,7 +17,9 @@ module VX_csr_data #(
input wire write_enable,
input wire[`CSR_ADDR_BITS-1:0] write_addr,
input wire[`NW_BITS-1:0] write_wid,
input wire[`CSR_WIDTH-1:0] write_data
input wire[`CSR_WIDTH-1:0] write_data,
input wire busy
);
reg [`CSR_WIDTH-1:0] csr_satp;
reg [`CSR_WIDTH-1:0] csr_mstatus;
@@ -86,7 +88,9 @@ module VX_csr_data #(
csr_cycle <= 0;
csr_instret <= 0;
end else begin
csr_cycle <= csr_cycle + 1;
if (busy) begin
csr_cycle <= csr_cycle + 1;
end
if (cmt_to_csr_if.valid) begin
csr_instret <= csr_instret + 64'(cmt_to_csr_if.num_commits);
end