diff --git a/Dockerfile b/Dockerfile
new file mode 100644
index 00000000..ce1e707e
--- /dev/null
+++ b/Dockerfile
@@ -0,0 +1,79 @@
+# Dockerfile for setting up the development environment for vortex
+
+# Set base OS
+FROM ubuntu:18.04
+
+# Install dependencies
+RUN apt update && apt install -y \
+    # verilator dependencies
+    git perl python3 g++ libfl2 libfl-dev \
+    zlibc zlib1g zlib1g-dev \
+    ccache libgoogle-perftools-dev numactl perl-doc \
+    git autoconf flex bison \
+    # riscv-gnu-toolchain dependencies
+    autoconf automake autotools-dev curl python3 \
+    libmpc-dev libmpfr-dev libgmp-dev gawk build-essential \
+    bison flex texinfo gperf libtool patchutils bc zlib1g-dev \
+    libexpat-dev binutils build-essential libtool texinfo \
+    # riscv-isa-sim dependencies
+    device-tree-compiler 
+
+# set environment variables
+ENV RISCV32=/opt/riscv32
+ENV RISCV64=/opt/riscv64
+ENV VERILATOR_ROOT=/opt/verilator
+ENV POCL_CC_PATH=/opt/pocl/compiler
+ENV POCL_RT_PATH=/opt/pocl/runtime
+ENV VORTEX_HOME=/home/vortex
+ENV PATH=$PATH:${RISCV32}/bin:${RISCV64}/bin:${RISCV64}/riscv64-unknown-elf/bin:${VERILATOR_ROOT}/bin/verilator
+
+# Install riscv-gnu-toolchain
+RUN git clone https://github.com/riscv/riscv-gnu-toolchain /tmp/riscv-gnu-toolchain
+RUN cd /tmp/riscv-gnu-toolchain; \
+    ./configure --prefix=${RISCV64} --with-arch=rv64imfd --with-abi=lp64d; \
+    make -j `nproc`
+RUN cd /tmp/riscv-gnu-toolchain; \
+    make clean; \
+    ./configure --prefix=${RISCV32} --with-arch=rv32imf --with-abi=ilp32f; \
+    make -j `nproc`
+RUN rm -rf /tmp/riscv-gnu-toolchain
+
+# Install riscv-isa-sim 
+RUN git clone https://github.com/riscv-software-src/riscv-isa-sim.git /tmp/riscv-isa-sim
+RUN cd /tmp/riscv-isa-sim; \
+    mkdir build
+RUN cd /tmp/riscv-isa-sim/build; \
+    ../configure --prefix=${RISCV64}
+RUN cd /tmp/riscv-isa-sim/build; \
+    make -j `nproc`; \
+    make install
+RUN rm -rf /tmp/riscv-isa-sim
+
+# Install riscv-pk
+RUN git clone https://github.com/riscv-software-src/riscv-pk.git /tmp/riscv-pk
+RUN cd /tmp/riscv-pk; \
+    mkdir build 
+RUN cd /tmp/riscv-pk/build; \
+    ../configure --prefix=${RISCV64} --host=riscv64-unknown-elf
+RUN cd /tmp/riscv-pk/build; \
+    make -j `nproc`; \
+    make install
+RUN rm -rf /tmp/riscv-pk
+
+# Install verilator
+RUN git clone https://github.com/verilator/verilator /tmp/verilator
+RUN cd /tmp/verilator; \
+    git pull; \
+    git checkout v4.040
+RUN cd /tmp/verilator; \
+    autoconf; \
+    ./configure --prefix=/opt/verilator
+RUN cd/tmp/verilator; \
+    make -j `nproc`; \
+    make install
+RUN rm -rf /tmp/verilator
+
+# set working directory
+RUN mkdir -p /home/vortex
+WORKDIR /home/vortex
+
diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh
index e9e57b03..ef61f367 100644
--- a/hw/rtl/VX_config.vh
+++ b/hw/rtl/VX_config.vh
@@ -45,6 +45,7 @@
 `define L1_BLOCK_SIZE ((`L2_ENABLE || `L3_ENABLE) ? 16 : `MEM_BLOCK_SIZE)
 `endif
 
+// simx64
 `ifndef STARTUP_ADDR
 `define STARTUP_ADDR 32'h80000000
 `endif
diff --git a/runtime/Makefile b/runtime/Makefile
index d72eb665..824805a4 100644
--- a/runtime/Makefile
+++ b/runtime/Makefile
@@ -1,4 +1,7 @@
 RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
+# simx64
+RISCV64_TOOLCHAIN_PATH ?= /nethome/ssrivatsan8/riscv
+
 
 CC = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-gcc
 AR = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-gcc-ar
diff --git a/runtime/src/vx_start.S b/runtime/src/vx_start.S
index 16e91a15..9fa6dcec 100644
--- a/runtime/src/vx_start.S
+++ b/runtime/src/vx_start.S
@@ -23,13 +23,13 @@ _start:
   call    memset
 
   # Register global termination functions
-  la      a0, __libc_fini_array   
+  # la      a0, __libc_fini_array   
 
   # to be called upon exit
   call    atexit                  
 
   # Run global initialization functions
-  call    __libc_init_array       
+  # call    __libc_init_array       
 
   # call main program routine
   call    main
diff --git a/sim/common/rvfloats.cpp b/sim/common/rvfloats.cpp
index 17fab394..87ba5e80 100644
--- a/sim/common/rvfloats.cpp
+++ b/sim/common/rvfloats.cpp
@@ -8,11 +8,19 @@ extern "C" {
 }
 
 #define F32_SIGN 0x80000000
+// simx64
+#define F64_SIGN 0x8000000000000000
 
 inline float32_t to_float32_t(uint32_t x) { return float32_t{x}; }
 
+// simx64
+inline float64_t to_float64_t(uint64_t x) { return float64_t{x}; }
+
 inline uint32_t from_float32_t(float32_t x) { return uint32_t(x.v); }
 
+// simx64
+inline uint64_t from_float64_t(float64_t x) { return uint64_t(x.v); }
+
 inline uint32_t get_fflags() {
   uint32_t fflags = softfloat_exceptionFlags;
   if (fflags) {
@@ -25,35 +33,67 @@ inline uint32_t get_fflags() {
 extern "C" {
 #endif
 
-uint32_t rv_fadd(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) {
+uint64_t rv_fadd(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   auto r = f32_add(to_float32_t(a), to_float32_t(b));
   if (fflags) { *fflags = get_fflags(); }
   return from_float32_t(r);
 }
 
-uint32_t rv_fsub(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) {
+// simx64
+uint64_t rv_fadd_d(uint64_t a, uint64_t b, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f64_add(to_float64_t(a), to_float64_t(b));
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+uint64_t rv_fsub(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   auto r = f32_sub(to_float32_t(a), to_float32_t(b));
   if (fflags) { *fflags = get_fflags(); }
   return from_float32_t(r);
 }
 
-uint32_t rv_fmul(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) {
+// simx64
+uint64_t rv_fsub_d(uint64_t a, uint64_t b, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f64_sub(to_float64_t(a), to_float64_t(b));
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+uint64_t rv_fmul(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   auto r = f32_mul(to_float32_t(a), to_float32_t(b));
   if (fflags) { *fflags = get_fflags(); }
   return from_float32_t(r);
 }
 
-uint32_t rv_fmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) {
+// simx64
+uint64_t rv_fmul_d(uint64_t a, uint64_t b, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f64_mul(to_float64_t(a), to_float64_t(b));
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+uint64_t rv_fmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   auto r = f32_mulAdd(to_float32_t(a), to_float32_t(b), to_float32_t(c));
   if (fflags) { *fflags = get_fflags(); }
   return from_float32_t(r);
 }
 
-uint32_t rv_fmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) {
+// simx64
+uint64_t rv_fmadd_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f64_mulAdd(to_float64_t(a), to_float64_t(b), to_float64_t(c));
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+uint64_t rv_fmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   int c_neg = c ^ F32_SIGN;
   auto r = f32_mulAdd(to_float32_t(a), to_float32_t(b), to_float32_t(c_neg));
@@ -61,7 +101,16 @@ uint32_t rv_fmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* ff
   return from_float32_t(r);
 }
 
-uint32_t rv_fnmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) {
+// simx64
+uint64_t rv_fmsub_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  long c_neg = c ^ F64_SIGN;
+  auto r = f64_mulAdd(to_float64_t(a), to_float64_t(b), to_float64_t(c_neg));
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+uint64_t rv_fnmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   int a_neg = a ^ F32_SIGN;
   int c_neg = c ^ F32_SIGN;
@@ -70,7 +119,17 @@ uint32_t rv_fnmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* f
   return from_float32_t(r);
 }
 
-uint32_t rv_fnmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) {
+// simx64
+uint64_t rv_fnmadd_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  long a_neg = a ^ F64_SIGN;
+  long c_neg = c ^ F64_SIGN;
+  auto r = f64_mulAdd(to_float64_t(a_neg), to_float64_t(b), to_float64_t(c_neg));
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+uint64_t rv_fnmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   int a_neg = a ^ F32_SIGN;
   auto r = f32_mulAdd(to_float32_t(a_neg), to_float32_t(b), to_float32_t(c));
@@ -78,68 +137,211 @@ uint32_t rv_fnmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* f
   return from_float32_t(r);
 }
 
-uint32_t rv_fdiv(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) {
+// simx64
+uint64_t rv_fnmsub_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  long a_neg = a ^ F64_SIGN;
+  auto r = f64_mulAdd(to_float64_t(a_neg), to_float64_t(b), to_float64_t(c));
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+uint64_t rv_fdiv(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   auto r = f32_div(to_float32_t(a), to_float32_t(b));
   if (fflags) { *fflags = get_fflags(); }
   return from_float32_t(r);
 }
 
-uint32_t rv_fsqrt(uint32_t a, uint32_t frm, uint32_t* fflags) {
+// simx64
+uint64_t rv_fdiv_d(uint64_t a, uint64_t b, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f64_div(to_float64_t(a), to_float64_t(b));
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+uint64_t rv_fsqrt(uint32_t a, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   auto r = f32_sqrt(to_float32_t(a));
   if (fflags) { *fflags = get_fflags(); }
   return from_float32_t(r);
 }
 
-uint32_t rv_ftoi(uint32_t a, uint32_t frm, uint32_t* fflags) {
+// simx64x
+uint64_t rv_fsqrt_d(uint64_t a, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f64_sqrt(to_float64_t(a));
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+
+uint64_t rv_ftoi(uint32_t a, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   auto r = f32_to_i32(to_float32_t(a), frm, true);
   if (fflags) { *fflags = get_fflags(); }
   return r;
 }
 
-uint32_t rv_ftou(uint32_t a, uint32_t frm, uint32_t* fflags) {
+// simx64
+uint64_t rv_ftoi_d(uint64_t a, uint64_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f64_to_i32(to_float64_t(a), frm, true);
+  if (fflags) { *fflags = get_fflags(); }
+  return r;
+}
+
+uint64_t rv_ftou(uint32_t a, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   auto r = f32_to_ui32(to_float32_t(a), frm, true);
   if (fflags) { *fflags = get_fflags(); }
   return r;
 }
 
-uint32_t rv_itof(uint32_t a, uint32_t frm, uint32_t* fflags) {
+// simx64
+uint64_t rv_ftou_d(uint64_t a, uint64_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f64_to_ui32(to_float64_t(a), frm, true);
+  if (fflags) { *fflags = get_fflags(); }
+  return r;
+}
+
+// simx64
+uint64_t rv_ftol(uint32_t a, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f32_to_i64(to_float32_t(a), frm, true);
+  if (fflags) { *fflags = get_fflags(); }
+  return r;
+}
+
+// simx64
+uint64_t rv_ftol_d(uint64_t a, uint64_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f64_to_i64(to_float64_t(a), frm, true);
+  if (fflags) { *fflags = get_fflags(); }
+  return r;
+}
+
+// simx64
+uint64_t rv_ftolu(uint32_t a, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f32_to_ui64(to_float32_t(a), frm, true);
+  if (fflags) { *fflags = get_fflags(); }
+  return r;
+}
+
+// simx64
+uint64_t rv_ftolu_d(uint64_t a, uint64_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = f64_to_ui64(to_float64_t(a), frm, true);
+  if (fflags) { *fflags = get_fflags(); }
+  return r;
+}
+
+uint64_t rv_itof(uint32_t a, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   auto r = i32_to_f32(a);
   if (fflags) { *fflags = get_fflags(); }
   return from_float32_t(r);
 }
 
-uint32_t rv_utof(uint32_t a, uint32_t frm, uint32_t* fflags) {
+// simx64
+uint64_t rv_itof_d(uint32_t a, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = i32_to_f64(a);
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+uint64_t rv_utof(uint32_t a, uint32_t frm, uint32_t* fflags) {
   softfloat_roundingMode = frm;
   auto r = ui32_to_f32(a);
   if (fflags) { *fflags = get_fflags(); }
   return from_float32_t(r);
 }
 
-uint32_t rv_flt(uint32_t a, uint32_t b, uint32_t* fflags) {
+// simx64
+uint64_t rv_utof_d(uint32_t a, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = ui32_to_f64(a);
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+// simx64
+uint64_t rv_ltof(uint64_t a, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = i64_to_f32(a);
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float32_t(r);
+}
+
+// simx64
+uint64_t rv_ltof_d(uint64_t a, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = i64_to_f64(a);
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+// simx64
+uint64_t rv_lutof(uint64_t a, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = ui64_to_f32(a);
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float32_t(r);
+}
+
+// simx64
+uint64_t rv_lutof_d(uint64_t a, uint32_t frm, uint32_t* fflags) {
+  softfloat_roundingMode = frm;
+  auto r = ui64_to_f64(a);
+  if (fflags) { *fflags = get_fflags(); }
+  return from_float64_t(r);
+}
+
+uint64_t rv_flt(uint32_t a, uint32_t b, uint32_t* fflags) {
   auto r = f32_lt(to_float32_t(a), to_float32_t(b));
   if (fflags) { *fflags = get_fflags(); }
   return r;
 }
 
-uint32_t rv_fle(uint32_t a, uint32_t b, uint32_t* fflags) {
+// simx64
+uint64_t rv_flt_d(uint64_t a, uint64_t b, uint32_t* fflags) {
+  auto r = f64_lt(to_float64_t(a), to_float64_t(b));
+  if (fflags) { *fflags = get_fflags(); }
+  return r;
+}
+
+uint64_t rv_fle(uint32_t a, uint32_t b, uint32_t* fflags) {
   auto r = f32_le(to_float32_t(a), to_float32_t(b));
   if (fflags) { *fflags = get_fflags(); }
   return r;
 }
 
-uint32_t rv_feq(uint32_t a, uint32_t b, uint32_t* fflags) {
+// simx64
+uint64_t rv_fle_d(uint64_t a, uint64_t b, uint32_t* fflags) {
+  auto r = f64_le(to_float64_t(a), to_float64_t(b));
+  if (fflags) { *fflags = get_fflags(); }
+  return r;
+}
+
+uint64_t rv_feq(uint32_t a, uint32_t b, uint32_t* fflags) {
   auto r = f32_eq(to_float32_t(a), to_float32_t(b));
   if (fflags) { *fflags = get_fflags(); }  
   return r;
 }
 
-uint32_t rv_fmin(uint32_t a, uint32_t b, uint32_t* fflags) {  
-  int r;
+// simx64
+uint64_t rv_feq_d(uint64_t a, uint64_t b, uint32_t* fflags) {
+  auto r = f64_eq(to_float64_t(a), to_float64_t(b));
+  if (fflags) { *fflags = get_fflags(); }
+  return r;
+}
+
+uint64_t rv_fmin(uint32_t a, uint32_t b, uint32_t* fflags) {  
+  long r;
   if (isNaNF32UI(a) && isNaNF32UI(b)) {
     r = defaultNaNF32UI;   
   } else {
@@ -156,8 +358,27 @@ uint32_t rv_fmin(uint32_t a, uint32_t b, uint32_t* fflags) {
   return r;
 }
 
-uint32_t rv_fmax(uint32_t a, uint32_t b, uint32_t* fflags) {
-  int r;
+// simx64
+uint64_t rv_fmin_d(uint64_t a, uint64_t b, uint32_t* fflags) {  
+  long r;
+  if (isNaNF64UI(a) && isNaNF64UI(b)) {
+    r = defaultNaNF64UI;   
+  } else {
+    auto fa = to_float64_t(a);
+    auto fb = to_float64_t(b);
+    if ((f64_lt_quiet(fa, fb) || (f64_eq(fa, fb) && (a & F64_SIGN)))
+     || isNaNF64UI(b)) {
+      r = a;
+    } else {
+      r = b;
+    }
+  }
+  if (fflags) { *fflags = get_fflags(); }
+  return r;
+}
+
+uint64_t rv_fmax(uint32_t a, uint32_t b, uint32_t* fflags) {
+  long r;
   if (isNaNF32UI(a) && isNaNF32UI(b)) {
     r = defaultNaNF32UI;   
   } else {
@@ -174,7 +395,26 @@ uint32_t rv_fmax(uint32_t a, uint32_t b, uint32_t* fflags) {
   return r;
 }
 
-uint32_t rv_fclss(uint32_t a) {
+// simx64
+uint64_t rv_fmax_d(uint64_t a, uint64_t b, uint32_t* fflags) {
+  long r;
+  if (isNaNF64UI(a) && isNaNF64UI(b)) {
+    r = defaultNaNF64UI;   
+  } else {
+    auto fa = to_float64_t(a);
+    auto fb = to_float64_t(b);
+    if ((f64_lt_quiet(fb, fa) || (f64_eq(fb, fa) && (b & F64_SIGN)))
+     || isNaNF64UI(b)) {
+      r = a;
+    } else {
+      r = b;
+    }
+  }
+  if (fflags) { *fflags = get_fflags(); }
+  return r;
+}
+
+uint64_t rv_fclss(uint32_t a) {
   auto infOrNaN      = (0xff == expF32UI(a));
   auto subnormOrZero = (0 == expF32UI(a));
   bool sign          = signF32UI(a);
@@ -197,7 +437,31 @@ uint32_t rv_fclss(uint32_t a) {
   return r;
 }
 
-uint32_t rv_fsgnj(uint32_t a, uint32_t b) {
+// simx64
+uint64_t rv_fclss_d(uint64_t a) {
+  auto infOrNaN      = (0x7ff == expF64UI(a));
+  auto subnormOrZero = (0 == expF64UI(a));
+  bool sign          = signF64UI(a);
+  bool fracZero      = (0 == fracF64UI(a));
+  bool isNaN         = isNaNF64UI(a);
+  bool isSNaN        = softfloat_isSigNaNF64UI(a);
+
+  int r =
+      (  sign && infOrNaN && fracZero )        << 0 |
+      (  sign && !infOrNaN && !subnormOrZero ) << 1 |
+      (  sign && subnormOrZero && !fracZero )  << 2 |
+      (  sign && subnormOrZero && fracZero )   << 3 |
+      ( !sign && infOrNaN && fracZero )        << 7 |
+      ( !sign && !infOrNaN && !subnormOrZero ) << 6 |
+      ( !sign && subnormOrZero && !fracZero )  << 5 |
+      ( !sign && subnormOrZero && fracZero )   << 4 |
+      ( isNaN &&  isSNaN )                     << 8 |
+      ( isNaN && !isSNaN )                     << 9;  
+  
+  return r;
+}
+
+uint64_t rv_fsgnj(uint32_t a, uint32_t b) {
   
   int sign = b & F32_SIGN;
   int r = sign | (a & ~F32_SIGN);
@@ -205,7 +469,16 @@ uint32_t rv_fsgnj(uint32_t a, uint32_t b) {
   return r;
 }
 
-uint32_t rv_fsgnjn(uint32_t a, uint32_t b) {
+// simx64
+uint64_t rv_fsgnj_d(uint64_t a, uint64_t b) {
+  
+  long sign = b & F64_SIGN;
+  long r = sign | (a & ~F64_SIGN);
+
+  return r;
+}
+
+uint64_t rv_fsgnjn(uint32_t a, uint32_t b) {
   
   int sign = ~b & F32_SIGN;
   int r = sign | (a & ~F32_SIGN);
@@ -213,7 +486,16 @@ uint32_t rv_fsgnjn(uint32_t a, uint32_t b) {
   return r;
 }
 
-uint32_t rv_fsgnjx(uint32_t a, uint32_t b) {
+// simx64
+uint64_t rv_fsgnjn_d(uint64_t a, uint64_t b) {
+  
+  long sign = ~b & F64_SIGN;
+  long r = sign | (a & ~F64_SIGN);
+
+  return r;
+}
+
+uint64_t rv_fsgnjx(uint32_t a, uint32_t b) {
   
   int sign1 = a & F32_SIGN;
   int sign2 = b & F32_SIGN;
@@ -222,6 +504,30 @@ uint32_t rv_fsgnjx(uint32_t a, uint32_t b) {
   return r;
 }
 
+// simx64
+uint64_t rv_fsgnjx_d(uint64_t a, uint64_t b) {
+  
+  long sign1 = a & F64_SIGN;
+  long sign2 = b & F64_SIGN;
+  long r = (sign1 ^ sign2) | (a & ~F64_SIGN);
+
+  return r;
+}
+
+// simx64
+uint64_t rv_dtof(uint64_t a) {
+
+  auto r = f64_to_f32(to_float64_t(a));
+  return from_float32_t(r);
+}
+
+// simx64
+uint64_t rv_ftod(uint32_t a) {
+
+  auto r = f32_to_f64(to_float32_t(a));
+  return from_float64_t(r);
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/sim/common/rvfloats.h b/sim/common/rvfloats.h
index 392e5b63..2e36e16a 100644
--- a/sim/common/rvfloats.h
+++ b/sim/common/rvfloats.h
@@ -7,32 +7,76 @@
 extern "C" {
 #endif
 
-uint32_t rv_fadd(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags);
-uint32_t rv_fsub(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags);
-uint32_t rv_fmul(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags);
-uint32_t rv_fmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags);
-uint32_t rv_fmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags);
-uint32_t rv_fnmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags);
-uint32_t rv_fnmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fadd(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fsub(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fmul(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fnmadd(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fnmsub(uint32_t a, uint32_t b, uint32_t c, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fdiv(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fsqrt(uint32_t a, uint32_t frm, uint32_t* fflags);
 
-uint32_t rv_fdiv(uint32_t a, uint32_t b, uint32_t frm, uint32_t* fflags);
-uint32_t rv_fsqrt(uint32_t a, uint32_t frm, uint32_t* fflags);
+uint64_t rv_ftoi(uint32_t a, uint32_t frm, uint32_t* fflags);
+uint64_t rv_ftou(uint32_t a, uint32_t frm, uint32_t* fflags);
+// simx64
+uint64_t rv_ftol(uint32_t a, uint32_t frm, uint32_t* fflags);
+// simx64
+uint64_t rv_ftolu(uint32_t a, uint32_t frm, uint32_t* fflags);
+uint64_t rv_itof(uint32_t a, uint32_t frm, uint32_t* fflags);
+uint64_t rv_utof(uint32_t a, uint32_t frm, uint32_t* fflags);
+// simx64
+uint64_t rv_ltof(uint64_t a, uint32_t frm, uint32_t* fflags);
+// simx64
+uint64_t rv_lutof(uint64_t a, uint32_t frm, uint32_t* fflags);
 
-uint32_t rv_ftoi(uint32_t a, uint32_t frm, uint32_t* fflags);
-uint32_t rv_ftou(uint32_t a, uint32_t frm, uint32_t* fflags);
-uint32_t rv_itof(uint32_t a, uint32_t frm, uint32_t* fflags);
-uint32_t rv_utof(uint32_t a, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fclss(uint32_t a);
+uint64_t rv_fsgnj(uint32_t a, uint32_t b);
+uint64_t rv_fsgnjn(uint32_t a, uint32_t b);
+uint64_t rv_fsgnjx(uint32_t a, uint32_t b);
 
-uint32_t rv_fclss(uint32_t a);
-uint32_t rv_fsgnj(uint32_t a, uint32_t b);
-uint32_t rv_fsgnjn(uint32_t a, uint32_t b);
-uint32_t rv_fsgnjx(uint32_t a, uint32_t b);
+uint64_t rv_flt(uint32_t a, uint32_t b, uint32_t* fflags);
+uint64_t rv_fle(uint32_t a, uint32_t b, uint32_t* fflags);
+uint64_t rv_feq(uint32_t a, uint32_t b, uint32_t* fflags);
+uint64_t rv_fmin(uint32_t a, uint32_t b, uint32_t* fflags);
+uint64_t rv_fmax(uint32_t a, uint32_t b, uint32_t* fflags);
 
-uint32_t rv_flt(uint32_t a, uint32_t b, uint32_t* fflags);
-uint32_t rv_fle(uint32_t a, uint32_t b, uint32_t* fflags);
-uint32_t rv_feq(uint32_t a, uint32_t b, uint32_t* fflags);
-uint32_t rv_fmin(uint32_t a, uint32_t b, uint32_t* fflags);
-uint32_t rv_fmax(uint32_t a, uint32_t b, uint32_t* fflags);
+
+
+// simx64
+uint64_t rv_fadd_d(uint64_t a, uint64_t b, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fsub_d(uint64_t a, uint64_t b, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fmul_d(uint64_t a, uint64_t b, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fdiv_d(uint64_t a, uint64_t b, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fsqrt_d(uint64_t a, uint32_t frm, uint32_t* fflags);
+
+uint64_t rv_fmadd_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fmsub_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fnmadd_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t* fflags);
+uint64_t rv_fnmsub_d(uint64_t a, uint64_t b, uint64_t c, uint32_t frm, uint32_t* fflags);
+
+uint64_t rv_ftoi_d(uint64_t a, uint64_t frm, uint32_t* fflags);
+uint64_t rv_ftou_d(uint64_t a, uint64_t frm, uint32_t* fflags);
+uint64_t rv_ftol_d(uint64_t a, uint64_t frm, uint32_t* fflags);
+uint64_t rv_ftolu_d(uint64_t a, uint64_t frm, uint32_t* fflags);
+uint64_t rv_itof_d(uint32_t a, uint32_t frm, uint32_t* fflags);
+uint64_t rv_utof_d(uint32_t a, uint32_t frm, uint32_t* fflags);
+uint64_t rv_ltof_d(uint64_t a, uint32_t frm, uint32_t* fflags);
+uint64_t rv_lutof_d(uint64_t a, uint32_t frm, uint32_t* fflags);
+
+uint64_t rv_fclss_d(uint64_t a);
+uint64_t rv_fsgnj_d(uint64_t a, uint64_t b);
+uint64_t rv_fsgnjn_d(uint64_t a, uint64_t b);
+uint64_t rv_fsgnjx_d(uint64_t a, uint64_t b);
+
+uint64_t rv_flt_d(uint64_t a, uint64_t b, uint32_t* fflags);
+uint64_t rv_fle_d(uint64_t a, uint64_t b, uint32_t* fflags);
+uint64_t rv_feq_d(uint64_t a, uint64_t b, uint32_t* fflags);
+uint64_t rv_fmin_d(uint64_t a, uint64_t b, uint32_t* fflags);
+uint64_t rv_fmax_d(uint64_t a, uint64_t b, uint32_t* fflags);
+
+uint64_t rv_dtof(uint64_t a);
+uint64_t rv_ftod(uint32_t a);
 
 #ifdef __cplusplus
 }
diff --git a/sim/simX/Makefile b/sim/simX/Makefile
new file mode 100644
index 00000000..0feba083
--- /dev/null
+++ b/sim/simX/Makefile
@@ -0,0 +1,50 @@
+RTL_DIR = ../hw/rtl
+
+CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors -Werror -g
+CXXFLAGS += -fPIC -Wno-maybe-uninitialized
+CXXFLAGS += -I. -I../common -I../../hw
+CXXFLAGS += -I../common/softfloat/source/include
+CXXFLAGS += $(CONFIGS)
+
+LDFLAGS += ../common/softfloat/build/Linux-x86_64-GCC/softfloat.a
+
+TOP = vx_cache_sim
+
+SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp 
+SRCS += args.cpp pipeline.cpp warp.cpp core.cpp decode.cpp execute.cpp main.cpp
+
+OBJS := $(patsubst %.cpp, obj_dir/%.o, $(notdir $(SRCS)))
+VPATH := $(sort $(dir $(SRCS)))
+
+#$(info OBJS is $(OBJS))
+#$(info VPATH is $(VPATH))
+
+# Debugigng
+ifdef DEBUG
+	CXXFLAGS += -g -O0 -DDEBUG_LEVEL=$(DEBUG)
+else    
+	CXXFLAGS += -O2 -DNDEBUG
+endif
+
+PROJECT = simX
+
+all: $(PROJECT)
+
+$(PROJECT): $(SRCS)
+	$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@
+
+obj_dir/%.o: %.cpp
+	mkdir -p obj_dir
+	$(CXX) $(CXXFLAGS) -c $< -o $@
+
+static: $(OBJS)
+	$(AR) rcs lib$(PROJECT).a $(OBJS) ../common/softfloat/build/Linux-x86_64-GCC/*.o
+
+.depend: $(SRCS)
+	$(CXX) $(CXXFLAGS) -MM $^ > .depend;
+
+clean-static:
+	rm -rf lib$(PROJECT).a obj_dir .depend
+
+clean: clean-static
+	rm -rf $(PROJECT)
\ No newline at end of file
diff --git a/sim/simx/Makefile b/sim/simx/Makefile
index 1d081c9e..d83a17f4 100644
--- a/sim/simx/Makefile
+++ b/sim/simx/Makefile
@@ -45,4 +45,4 @@ $(DESTDIR)/lib$(PROJECT).so: $(SRCS)
 	$(CXX) $(CXXFLAGS) -MM $^ > .depend;
 
 clean:
-	rm -rf obj_dir $(DESTDIR)/$(PROJECT) $(DESTDIR)/lib$(PROJECT).so
\ No newline at end of file
+	rm -rf obj_dir $(DESTDIR)/$(PROJECT) $(DESTDIR)/lib$(PROJECT).so
diff --git a/sim/simx/archdef.h b/sim/simx/archdef.h
index c2a28f78..22cc1198 100644
--- a/sim/simx/archdef.h
+++ b/sim/simx/archdef.h
@@ -28,7 +28,7 @@ public:
     : num_cores_(num_cores)
     , num_warps_(num_warps)
     , num_threads_(num_threads)
-    , wsize_(4)
+    , wsize_(8)
     , vsize_(16)
     , num_regs_(32)
     , num_csrs_(4096)
@@ -66,6 +66,4 @@ public:
   uint16_t num_cores() const {
     return num_cores_;
   }
-};
-
 }
\ No newline at end of file
diff --git a/sim/simx/decode.cpp b/sim/simx/decode.cpp
index 86e30266..9ead3a7f 100644
--- a/sim/simx/decode.cpp
+++ b/sim/simx/decode.cpp
@@ -50,7 +50,7 @@ static const char* op_string(const Instr &instr) {
   Word func3  = instr.getFunc3();
   Word func7  = instr.getFunc7();
   Word rs2    = instr.getRSrc(1);
-  Word imm    = instr.getImm();
+  DoubleWord imm    = instr.getImm();
 
   switch (opcode) {
   case Opcode::NOP:        return "NOP";
@@ -109,8 +109,12 @@ static const char* op_string(const Instr &instr) {
     case 0: return "LBI";
     case 1: return "LHI";
     case 2: return "LW";
+    // simx64
+    case 3: return "LD";
     case 4: return "LBU";
     case 5: return "LHU";
+    // simx64
+    case 6: return "LWU";
     default:
       std::abort();
     }
@@ -119,9 +123,41 @@ static const char* op_string(const Instr &instr) {
     case 0: return "SB";
     case 1: return "SH";
     case 2: return "SW";
+    // simx64
+    case 3: return "SD";
     default:
       std::abort();
     }
+  // simx64
+  case Opcode::R_INST_64:
+    if (func7 & 0x1){
+      switch (func3) {
+      case 0: return func7 ? "SUBW" : "ADDW";
+      case 1: return "SLLW";
+      case 5: return func7 ? "SRAW" : "SRLW";  
+      default:
+        std::abort();
+      }
+    } else {
+      switch (func3) {
+        case 0: return "MULW";
+        case 4: return "DIVW";
+        case 5: return "DIVUW";
+        case 6: return "REMW";
+        case 7: return "REMUW";
+        default:
+          std::abort();
+      }
+    }
+  // simx64  
+  case Opcode::I_INST_64:
+    switch (func3) {
+      case 0: return "ADDIW";
+      case 1: return "SLLIW";
+      case 5: return func7 ? "SRAIW" : "SRLIW";
+      default:
+        std::abort();
+    }
   case Opcode::SYS_INST: 
     switch (func3) {
     case 0:
@@ -144,49 +180,131 @@ static const char* op_string(const Instr &instr) {
       std::abort();
     }
   case Opcode::FENCE: return "FENCE";
-  case Opcode::FL: return (func3 == 0x2) ? "FL" : "VL";
-  case Opcode::FS: return (func3 == 0x2) ? "FS" : "VS";
+  // simx64
+  case Opcode::FL: 
+    switch (func3) {
+      case 0x1: return "VL";
+      case 0x2: return "FLW";
+      case 0x3: return "FLD";
+      default: 
+        std::abort();
+    }
+  case Opcode::FS: 
+    switch (func3) {
+      case 0x1: return "VS";
+      case 0x2: return "FSW";
+      case 0x3: return "FSD";
+      default: 
+        std::abort();
+    }
   case Opcode::FCI: 
     switch (func7) {
-    case 0x00: return "FADD";
-    case 0x04: return "FSUB";
-    case 0x08: return "FMUL";
-    case 0x0c: return "FDIV";
-    case 0x2c: return "FSQRT";
+    case 0x00: return "FADD.S";
+    case 0x01: return "FADD.D";
+    case 0x04: return "FSUB.S";
+    case 0x05: return "FSUB.D";
+    case 0x08: return "FMUL.S";
+    case 0x09: return "FMUL.D";
+    case 0x0c: return "FDIV.S";
+    case 0x0d: return "FDIV.D";
+    case 0x2c: return "FSQRT.S";
+    case 0x2d: return "FSQRT.D";
     case 0x10:
       switch (func3) {            
-      case 0: return "FSGNJ";
-      case 1: return "FSGNJN";
-      case 2: return "FSGNJX";
+      case 0: return "FSGNJ.S";
+      case 1: return "FSGNJN.S";
+      case 2: return "FSGNJX.S";
+      default:
+        std::abort();
+      }
+    case 0x11:
+      switch (func3) {            
+      case 0: return "FSGNJ.D";
+      case 1: return "FSGNJN.D";
+      case 2: return "FSGNJX.D";
       default:
         std::abort();
       }
     case 0x14:
       switch (func3) {            
-      case 0: return "FMIM";
-      case 1: return "FMAX";
+      case 0: return "FMIN.S";
+      case 1: return "FMAX.S";
       default:
         std::abort();
       }
+    case 0x15:
+      switch (func3) {            
+      case 0: return "FMIN.D";
+      case 1: return "FMAX.D";
+      default:
+        std::abort();
+      }
+    case 0x20: return "FCVT.S.D";
+    case 0x21: return "FCVT.D.S";
     case 0x50: 
       switch (func3) {              
-      case 0: return "FLE"; 
-      case 1: return "FLT"; 
-      case 2: return "FEQ";
+      case 0: return "FLE.S"; 
+      case 1: return "FLT.S"; 
+      case 2: return "FEQ.S";
       default:
         std::abort();
       }
-    case 0x60: return rs2 ? "FCVT.WU.S" : "FCVT.W.S";
-    case 0x68: return rs2 ? "FCVT.S.WU" : "FCVT.S.W";
-    case 0x70: return func3 ? "FLASS" : "FMV.X.W";
+    case 0x51: 
+      switch (func3) {              
+      case 0: return "FLE.D"; 
+      case 1: return "FLT.D"; 
+      case 2: return "FEQ.D";
+      default:
+        std::abort();
+      }
+    // simx64
+    case 0x60: 
+      switch (rs2) {
+      case 0: return "FCVT.W.S";
+      case 1: return "FCVT.WU.S";
+      case 2: return "FCVT.L.S";
+      case 3: return "FCVT.LU.S";
+      default:
+        std::abort();
+      }
+    case 0x61:
+      switch (rs2) {
+      case 0: return "FCVT.W.D";
+      case 1: return "FCVT.WU.D";
+      case 2: return "FCVT.L.D";
+      case 3: return "FCVT.LU.D";
+      default:
+        std::abort();
+      }
+    case 0x68: 
+      switch (rs2) {
+      case 0: return "FCVT.S.W";
+      case 1: return "FCVT.S.WU";
+      case 2: return "FCVT.S.L";
+      case 3: return "FCVT.S.LU";
+      default:
+        std::abort();
+      }
+    case 0x69:
+      switch (rs2) {
+      case 0: return "FCVT.D.W";
+      case 1: return "FCVT.D.WU";
+      case 2: return "FCVT.D.L";
+      case 3: return "FCVT.D.LU";
+      default:
+        std::abort();
+      }
+    case 0x70: return func3 ? "FCLASS.S" : "FMV.X.W";
+    case 0x71: return func3 ? "FCLASS.D" : "FMV.X.D";
     case 0x78: return "FMV.W.X";
+    case 0x79: return "FMV.D.X";
     default:
       std::abort();
     }
-  case Opcode::FMADD:   return "FMADD";
-  case Opcode::FMSUB:   return "FMSUB";
-  case Opcode::FMNMADD: return "FMNMADD";
-  case Opcode::FMNMSUB: return "FMNMSUB";
+  case Opcode::FMADD:   return func2 ? "FMADD.D" : "FMADD.S";
+  case Opcode::FMSUB:   return func2 ? "FMSUB.D" : "FMSUB.S";
+  case Opcode::FMNMADD: return func2 ? "FNMADD.D" : "FNMADD.S";
+  case Opcode::FMNMSUB: return func2 ? "FNMSUB.D" : "FNMSUB.S";
   case Opcode::VSET:    return "VSET";
   case Opcode::GPGPU:
     switch (func3) {            
@@ -256,7 +374,8 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
 }
 
 Decoder::Decoder(const ArchDef &arch) {
-  inst_s_   = arch.wsize() * 8;
+  // simx64
+  inst_s_   = arch.wsize() * 4;
   opcode_s_ = 7;
   reg_s_    = 5;
   func2_s_  = 2;
@@ -314,7 +433,8 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
 
   auto iType = op_it->second.iType;
   if (op == Opcode::FL || op == Opcode::FS) { 
-    if (func3 != 0x2) {
+    // simx64
+    if (func3 != 0x2 && func3 != 0x3) {
       iType = InstType::V_TYPE;
     }
   }
@@ -326,8 +446,10 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
   case InstType::R_TYPE:
     if (op == Opcode::FCI) {      
       switch (func7) {
-      case 0x68: // FCVT.S.W, FCVT.S.WU
+      case 0x68: // FCVT.S.W, FCVT.S.WU, FCVT.S.L, FCVT.S.LU
+      case 0x69: // FCVT.D.W, FCVT.D.WU, FCVT.D.L, FCVT.D.LU
       case 0x78: // FMV.W.X
+      case 0x79: // FMV.D.X
         instr->setSrcReg(rs1);
         break;
       default:
@@ -335,9 +457,12 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
       }      
       instr->setSrcFReg(rs2);
       switch (func7) {
-      case 0x50: // FLE, FLT, FEQ
-      case 0x60: // FCVT.WU.S, FCVT.W.S
-      case 0x70: // FLASS, FMV.X.W
+      case 0x50: // FLE.S, FLT.S, FEQ.S
+      case 0x51: // FLE.D, FLT.D, FEQ.D
+      case 0x60: // FCVT.WU.S, FCVT.W.S, FCVT.L.S, FCVT.LU.S
+      case 0x61: // FCVT.W.D, FCVT.WU.D, FCVT.L.D, FCVT.LU.D
+      case 0x70: // FLASS.S, FMV.X.W
+      case 0x71: // FCLASS.D, FMV.X.D
         instr->setDestReg(rd);
         break;
       default:
@@ -369,8 +494,9 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
       break;
     case Opcode::I_INST:
       if (func3 == 0x1 || func3 == 0x5) {
-        // int5
-        instr->setImm(sext32(rs2, 5));
+        // simx64
+        // int6
+        instr->setImm(sext32(rs2, 6));
       } else {
         // int12
         instr->setImm(sext32(code >> shift_rs2_, 12));
@@ -390,7 +516,8 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
       instr->setSrcReg(rs2);
     }
     instr->setFunc3(func3);
-    Word imm = (func7 << reg_s_) | rd;
+    // simx64
+    DoubleWord imm = (func7 << reg_s_) | rd;
     instr->setImm(sext32(imm, 12));
   } break;
 
@@ -402,7 +529,8 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
     Word bits_4_1 = rd >> 1;
     Word bit_10_5 = func7 & 0x3f;
     Word bit_12   = func7 >> 6;
-    Word imm = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
+    // simx64
+    DoubleWord imm = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
     instr->setImm(sext32(imm, 13));
   } break;
 
@@ -418,7 +546,8 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
     Word bit_11 = (unordered >> 8) & 0x1;
     Word bits_10_1 = (unordered >> 9) & 0x3ff;
     Word bit_20 = (unordered >> 19) & 0x1;
-    Word imm = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
+    // simx64
+    DoubleWord imm = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
     if (bit_20) {
       imm |= ~j_imm_mask_;
     }
@@ -487,6 +616,8 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
     }
     instr->setFunc2(func2);
     instr->setFunc3(func3);
+    // simx64
+    instr->setFunc2(func2);
     break;
   default:
     std::abort();
diff --git a/sim/simx/execute.cpp b/sim/simx/execute.cpp
index 5df72c6f..8c8480d9 100644
--- a/sim/simx/execute.cpp
+++ b/sim/simx/execute.cpp
@@ -16,7 +16,7 @@
 using namespace vortex;
 
 static bool HasDivergentThreads(const ThreadMask &thread_mask,                                
-                                const std::vector<std::vector<Word>> &reg_file,
+                                const std::vector<std::vector<DoubleWord>> &reg_file,
                                 unsigned reg) {
   bool cond;
   size_t thread_idx = 0;
@@ -52,7 +52,7 @@ inline void update_fcrs(uint32_t fflags, Core* core, uint32_t tid, uint32_t wid)
 void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
   assert(tmask_.any());
 
-  Word nextPC = PC_ + core_->arch().wsize();
+  DoubleWord nextPC = PC_ + 4;
 
   Word func2  = instr.getFunc2();
   Word func3  = instr.getFunc3();
@@ -64,13 +64,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
   int rsrc0   = instr.getRSrc(0);
   int rsrc1   = instr.getRSrc(1);
   int rsrc2   = instr.getRSrc(2);
-  Word immsrc = instr.getImm();
+  DoubleWord immsrc = instr.getImm();
   Word vmask  = instr.getVmask();
 
   int num_threads = core_->arch().num_threads();
 
-  std::vector<Word[3]> rsdata(num_threads);
-  std::vector<Word> rddata(num_threads);
+  std::vector<DoubleWord[3]> rsdata(num_threads);
+  std::vector<DoubleWord> rddata(num_threads);
   
   int num_rsrcs = instr.getNRSrc();
   if (num_rsrcs) {              
@@ -123,7 +123,8 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
     for (int t = 0; t < num_threads; ++t) {
       if (!tmask_.test(t))
         continue;
-      rddata[t] = (immsrc << 12) & 0xfffff000;
+      // simx64
+      rddata[t] = (immsrc << 12) & 0xfffffffffffff000;
     }    
     rd_write = true;
     break;
@@ -133,7 +134,8 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
     for (int t = 0; t < num_threads; ++t) {
       if (!tmask_.test(t))
         continue;
-      rddata[t] = ((immsrc << 12) & 0xfffff000) + PC_;
+      // simx64
+      rddata[t] = ((immsrc << 12) & 0xfffffffffffff000) + PC_;
     }    
     rd_write = true;
     break;
@@ -148,48 +150,42 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
       if (func7 & 0x1) {
         switch (func3) {
         case 0:
-          // MUL
-          rddata[t] = ((WordI)rsdata[t][0]) * ((WordI)rsdata[t][1]);
+          // RV32M: MUL
+          rddata[t] = ((DoubleWordI)rsdata[t][0]) * ((DoubleWordI)rsdata[t][1]);
           trace->alu.type = AluType::IMUL;
           break;
         case 1: {
-          // MULH
-          int64_t first = (int64_t)rsdata[t][0];
-          if (rsdata[t][0] & 0x80000000) {
-            first = first | 0xFFFFFFFF00000000;
-          }
-          int64_t second = (int64_t)rsdata[t][1];
-          if (rsdata[t][1] & 0x80000000) {
-            second = second | 0xFFFFFFFF00000000;
-          }
-          uint64_t result = first * second;
-          rddata[t] = (result >> 32) & 0xFFFFFFFF;
+          // RV32M: MULH
+          // simx64
+          __int128_t first = sext128((__int128_t)rsdata[t][0], 64);
+          __int128_t second = sext128((__int128_t)rsdata[t][1], 64);
+          rddata[t] = ((first * second) >> 64) & 0xFFFFFFFFFFFFFFFF;
           trace->alu.type = AluType::IMUL;
         } break;
         case 2: {
-          // MULHSU          
-          int64_t first = (int64_t)rsdata[t][0];
-          if (rsdata[t][0] & 0x80000000) {
-            first = first | 0xFFFFFFFF00000000;
-          }
-          int64_t second = (int64_t)rsdata[t][1];
-          rddata[t] = ((first * second) >> 32) & 0xFFFFFFFF;
+          // RV32M: MULHSU   
+          // simx64       
+          __int128_t first = sext128((__int128_t)rsdata[t][0], 64);
+          __int128_t second = (__int128_t)rsdata[t][1];
+          rddata[t] = ((first * second) >> 64) & 0xFFFFFFFFFFFFFFFF;
           trace->alu.type = AluType::IMUL;
         } break;
         case 3: {
-          // MULHU
-          uint64_t first = (uint64_t)rsdata[t][0];
-          uint64_t second = (uint64_t)rsdata[t][1];
-          rddata[t] = ((first * second) >> 32) & 0xFFFFFFFF;
+          // RV32M: MULHU
+          // simx64
+          __uint128_t first = (__int128_t)rsdata[t][0];
+          __uint128_t second = (__int128_t)rsdata[t][1];
+          rddata[t] = ((first * second) >> 64) & 0xFFFFFFFFFFFFFFFF;
           trace->alu.type = AluType::IMUL;
         } break;
         case 4: {
-          // DIV
-          WordI dividen = rsdata[t][0];
-          WordI divisor = rsdata[t][1];
+          // RV32M: DIV
+          // simx64
+          DoubleWordI dividen = rsdata[t][0];
+          DoubleWordI divisor = rsdata[t][1];
           if (divisor == 0) {
             rddata[t] = -1;
-          } else if (dividen == WordI(0x80000000) && divisor == WordI(0xffffffff)) {
+          } else if (dividen == DoubleWordI(0x8000000000000000) && divisor == DoubleWordI(0xffffffffffffffff)) {
             rddata[t] = dividen;
           } else {
             rddata[t] = dividen / divisor;
@@ -197,9 +193,10 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           trace->alu.type = AluType::IDIV;
         } break;
         case 5: {
-          // DIVU
-          Word dividen = rsdata[t][0];
-          Word divisor = rsdata[t][1];
+          // RV32M: DIVU
+          // simx64
+          DoubleWord dividen = rsdata[t][0];
+          DoubleWord divisor = rsdata[t][1];
           if (divisor == 0) {
             rddata[t] = -1;
           } else {
@@ -208,12 +205,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           trace->alu.type = AluType::IDIV;
         } break;
         case 6: {
-          // REM
-          WordI dividen = rsdata[t][0];
-          WordI divisor = rsdata[t][1];
+          // RV32M: REM
+          // simx64
+          DoubleWordI dividen = rsdata[t][0];
+          DoubleWordI divisor = rsdata[t][1];
           if (rsdata[t][1] == 0) {
             rddata[t] = dividen;
-          } else if (dividen == WordI(0x80000000) && divisor == WordI(0xffffffff)) {
+          } else if (dividen == DoubleWordI(0x8000000000000000) && divisor == DoubleWordI(0xffffffffffffffff)) {
             rddata[t] = 0;
           } else {
             rddata[t] = dividen % divisor;
@@ -221,9 +219,9 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           trace->alu.type = AluType::IDIV;
         } break;
         case 7: {
-          // REMU
-          Word dividen = rsdata[t][0];
-          Word divisor = rsdata[t][1];
+          // RV32M: REMU
+          DoubleWord dividen = rsdata[t][0];
+          DoubleWord divisor = rsdata[t][1];
           if (rsdata[t][1] == 0) {
             rddata[t] = dividen;
           } else {
@@ -238,44 +236,44 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         switch (func3) {
         case 0:
           if (func7) {
-            // SUB
+            // RV32I: SUB
             rddata[t] = rsdata[t][0] - rsdata[t][1];
           } else {
-            // ADD
+            // RV32I: ADD
             rddata[t] = rsdata[t][0] + rsdata[t][1];
           }
           break;
         case 1:
-          // SHL
+          // RV32I: SHL
           rddata[t] = rsdata[t][0] << rsdata[t][1];
           break;
         case 2:
-          // LT
-          rddata[t] = (WordI(rsdata[t][0]) < WordI(rsdata[t][1]));
+          // RV32I: LT
+          rddata[t] = (DoubleWordI(rsdata[t][0]) < DoubleWordI(rsdata[t][1]));
           break;
         case 3:
-          // LTU
-          rddata[t] = (Word(rsdata[t][0]) < Word(rsdata[t][1]));
+          // RV32I: LTU
+          rddata[t] = (DoubleWord(rsdata[t][0]) < DoubleWord(rsdata[t][1]));
           break;
         case 4:
-          // XOR
+          // RV32I: XOR
           rddata[t] = rsdata[t][0] ^ rsdata[t][1];
           break;
         case 5:
           if (func7) {
-            // SRA
-            rddata[t] = WordI(rsdata[t][0]) >> WordI(rsdata[t][1]);
+            // RV32I: SRA
+            rddata[t] = DoubleWordI(rsdata[t][0]) >> DoubleWordI(rsdata[t][1]);
           } else {
-            // SHR
-            rddata[t] = Word(rsdata[t][0]) >> Word(rsdata[t][1]);
+            // RV32I: SHR
+            rddata[t] = DoubleWord(rsdata[t][0]) >> DoubleWord(rsdata[t][1]);
           }
           break;
         case 6:
-          // OR
+          // RV32I: OR
           rddata[t] = rsdata[t][0] | rsdata[t][1];
           break;
         case 7:
-          // AND
+          // RV32I: AND
           rddata[t] = rsdata[t][0] & rsdata[t][1];
           break;
         default:
@@ -294,42 +292,42 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         continue;
       switch (func3) {
       case 0:
-        // ADDI
+        // RV32I: ADDI
         rddata[t] = rsdata[t][0] + immsrc;
         break;
       case 1:
-        // SLLI
+        // RV32I: SLLI
         rddata[t] = rsdata[t][0] << immsrc;
         break;
       case 2:
-        // SLTI
-        rddata[t] = (WordI(rsdata[t][0]) < WordI(immsrc));
+        // RV32I: SLTI
+        rddata[t] = (DoubleWordI(rsdata[t][0]) < DoubleWordI(immsrc));
         break;
       case 3: {
-        // SLTIU
-        rddata[t] = (Word(rsdata[t][0]) < Word(immsrc));
+        // RV32I: SLTIU
+        rddata[t] = (DoubleWord(rsdata[t][0]) < DoubleWord(immsrc));
       } break;
       case 4:
-        // XORI
+        // RV32I: XORI
         rddata[t] = rsdata[t][0] ^ immsrc;
         break;
       case 5:
         if (func7) {
-          // SRAI
-          Word result = WordI(rsdata[t][0]) >> immsrc;
+          // RV32I: SRAI
+          DoubleWord result = WordI(rsdata[t][0]) >> immsrc;
           rddata[t] = result;
         } else {
-          // SRLI
-          Word result = Word(rsdata[t][0]) >> immsrc;
+          // RV32I: SRLI
+          DoubleWord result = Word(rsdata[t][0]) >> immsrc;
           rddata[t] = result;
         }
         break;
       case 6:
-        // ORI
+        // RV32I: ORI
         rddata[t] = rsdata[t][0] | immsrc;
         break;
       case 7:
-        // ANDI
+        // RV32I: ANDI
         rddata[t] = rsdata[t][0] & immsrc;
         break;
       }
@@ -346,38 +344,38 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         continue;
       switch (func3) {
       case 0:
-        // BEQ
+        // RV32I: BEQ
         if (rsdata[t][0] == rsdata[t][1]) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 1:
-        // BNE
+        // RV32I: BNE
         if (rsdata[t][0] != rsdata[t][1]) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 4:
-        // BLT
-        if (WordI(rsdata[t][0]) < WordI(rsdata[t][1])) {
+        // RV32I: BLT
+        if (DoubleWordI(rsdata[t][0]) < DoubleWordI(rsdata[t][1])) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 5:
-        // BGE
-        if (WordI(rsdata[t][0]) >= WordI(rsdata[t][1])) {
+        // RV32I: BGE
+        if (DoubleWordI(rsdata[t][0]) >= DoubleWordI(rsdata[t][1])) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 6:
-        // BLTU
-        if (Word(rsdata[t][0]) < Word(rsdata[t][1])) {
+        // RV32I: BLTU
+        if (DoubleWord(rsdata[t][0]) < DoubleWord(rsdata[t][1])) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 7:
-        // BGEU
-        if (Word(rsdata[t][0]) >= Word(rsdata[t][1])) {
+        // RV32I: BGEU
+        if (DoubleWord(rsdata[t][0]) >= DoubleWord(rsdata[t][1])) {
           nextPC = PC_ + immsrc;
         }
         break;
@@ -425,32 +423,39 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
       for (int t = 0; t < num_threads; ++t) {
         if (!tmask_.test(t))
           continue;
-        Word mem_addr  = ((rsdata[t][0] + immsrc) & 0xFFFFFFFC); // word aligned
-        Word shift_by  = ((rsdata[t][0] + immsrc) & 0x00000003) * 8;
-        Word data_read = core_->dcache_read(mem_addr, 4);
+        DoubleWord mem_addr  = ((rsdata[t][0] + immsrc) & 0xFFFFFFFFFFFFFFF8); // word aligned
+        Word shift_by  = ((rsdata[t][0] + immsrc) & 0x00000007) * 8;
+        // simx64
+        DoubleWord data_read = core_->dcache_read(mem_addr, 8);
         trace->mem_addrs.at(t).push_back({mem_addr, 4});
         DP(4, "LOAD MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << data_read);
         switch (func3) {
         case 0:
-          // LBI
+          // RV32I: LBI
           rddata[t] = sext32((data_read >> shift_by) & 0xFF, 8);
           break;
         case 1:
-          // LHI
+          // RV32I: LHI
           rddata[t] = sext32((data_read >> shift_by) & 0xFFFF, 16);
           break;
         case 2:
-          // LW
-          rddata[t] = data_read;
+          // RV32I: LW
+          rddata[t] = sext32((data_read >> shift_by) & 0xFFFFFFFF, 32);
           break;
+        case 3:
+          // RV64I: LD
+          rddata[t] = data_read;
         case 4:
-          // LBU
-          rddata[t] = Word((data_read >> shift_by) & 0xFF);
+          // RV32I: LBU
+          rddata[t] = DoubleWord((data_read >> shift_by) & 0xFF);
           break;
         case 5:
-          // LHU
-          rddata[t] = Word((data_read >> shift_by) & 0xFFFF);
+          // RV32I: LHU
+          rddata[t] = DoubleWord((data_read >> shift_by) & 0xFFFF);
           break; 
+        case 6:
+          // RV64I: LWU
+          rddata[t] = DoubleWord((data_read >> shift_by) & 0xFFFFFFFF);
         default:
           std::abort();      
         }
@@ -490,22 +495,25 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
       for (int t = 0; t < num_threads; ++t) {
         if (!tmask_.test(t))
           continue;
-        Word mem_addr = rsdata[t][0] + immsrc;
+        DoubleWord mem_addr = rsdata[t][0] + immsrc;
         trace->mem_addrs.at(t).push_back({mem_addr, (1u << func3)});
         DP(4, "STORE MEM: ADDRESS=0x" << std::hex << mem_addr);
         switch (func3) {
         case 0:
-          // SB
+          // RV32I: SB
           core_->dcache_write(mem_addr, rsdata[t][1] & 0x000000FF, 1);
           break;
         case 1:
-          // SH
-          core_->dcache_write(mem_addr, rsdata[t][1], 2);
+          // RV32I: SH
+          core_->dcache_write(mem_addr, rsdata[t][1] & 0x0000FFFF, 2);
           break;
         case 2:
-          // SW
-          core_->dcache_write(mem_addr, rsdata[t][1], 4);
+          // RV32I: SW
+          core_->dcache_write(mem_addr, rsdata[t][1] & 0xFFFFFFFF, 4);
           break;
+        case 3:
+          // RV64I: SD
+          core_->dcache_write(mem_addr, rsdata[t][1], 8);
         default:
           std::abort();
         }
@@ -527,6 +535,120 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
       }
     }
     break;
+  // simx64
+  case R_INST_64: {
+    if (func7 & 0x1){
+      switch (func3) {
+        case 0: 
+          // RV64M: MULW
+          rddata[t] = sext64((WordI)rsdata[t][0] * (WordI)rsdata[t][1], 32);
+          break;
+        case 4: {
+          // RV64M: DIVW
+          int32_t dividen = (WordI) rsdata[t][0];
+          int32_t divisor = (WordI) rsdata[t][1];
+          if (divisor == 0){
+            rddata[t] = -1;
+          } else if (dividen == WordI(0x80000000) && divisor == WordI(0xFFFFFFFF)) {
+            rddata[t] = sext64(dividen, 32);
+          } else {
+            rddata[t] = sext64(dividen / divisor, 32);
+          }
+        } break;     
+        case 5: {
+          // RV64M: DIVUW
+          uint32_t dividen = (Word) rsdata[0];
+          uint32_t divisor = (Word) rsdata[1];
+          if (divisor == 0){
+            rddata[t] = -1;
+          } else {
+            rddata[t] = sext64(dividen / divisor, 32);
+          }
+        } break;
+        case 6: {
+          // RV64M: REMW
+          int32_t dividen = (WordI) rsdata[0];
+          int32_t divisor = (WordI) rsdata[1];
+          if (divisor == 0){
+            rddata[t] = sext64(dividen, 32);
+          } else if (dividen == WordI(0x80000000) && divisor == WordI(0xFFFFFFFF)) {
+            rddata[t] = 0;
+          } else {
+            rddata[t] = sext64(dividen % divisor, 32);
+          }
+        } break; 
+        case 7: {
+          // RV64M: REMUW
+          uint32_t dividen = (Word) rsdata[0];
+          uint32_t divisor = (Word) rsdata[1];
+          if (divisor == 0){
+            rddata[t] = sext64(dividen, 32);
+          } else {
+            rddata[t] = sext64(dividen % divisor, 32);
+          }
+        } break; 
+        default:
+          std::abort();
+      }
+    } else {
+      switch (func3) {
+      case 0: 
+        if (func7){
+          // RV64I: SUBW
+          rddata[t] = sext64((Word)rsdata[0] - (Word)rsdata[1], 32);
+        }
+        else{
+          // RV64I: ADDW
+          rddata[t] = sext64((Word)rsdata[0] + (Word)rsdata[1], 32);
+        }    
+        break;
+      case 1: 
+        // RV64I: SLLW
+        rddata[t] = sext64((Word)rsdata[0] << (Word)rsdata[1], 32);
+        break;
+      case 5:
+        if (func7) {
+          // RV64I: SRAW
+          rddata[t] = sext64((WordI)rsdata[0] >> (WordI)rsdata[1], 32);
+        } else {
+          // RV64I: SRLW
+          rddata[t] = sext64((Word)rsdata[0] >> (Word)rsdata[1], 32);
+        }
+        break;
+      default:
+        std::abort();
+      }
+    }
+    rd_write = true;
+  } break;
+    
+  // simx64
+  case I_INST_64: {
+    switch (func3) {
+      case 0:
+        // RV64I: ADDIW
+        rddata[t] = sext64((Word)rsdata[0] + (Word)immsrc, 32);
+        break;
+      case 1: 
+        // RV64I: SLLIW
+        rddata[t] = sext64((Word)rsdata[0] << (Word)immsrc, 32);
+        break;
+      case 5:
+        if (func7) {
+          // RV64I: SRAIW
+          DoubleWord result = sext64((WordI)rsdata[0] >> (WordI)immsrc, 32);
+          rddata[t] = result;
+        } else {
+          // RV64I: SRLIW
+          DoubleWord result = sext64((Word)rsdata[0] >> (Word)immsrc, 32);
+          rddata[t] = result;
+        }
+        break;
+      default:
+        std::abort();
+    }
+    rd_write = true;
+  } break;
   case SYS_INST:
     for (int t = 0; t < num_threads; ++t) {
       if (!tmask_.test(t))
@@ -538,10 +660,10 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         trace->alu.type = AluType::SYSCALL;
         trace->fetch_stall = true;
         switch (csr_addr) {
-        case 0: // ECALL
+        case 0: // RV32I: ECALL
           core_->trigger_ecall();
           break;
-        case 1: // EBREAK
+        case 1: // RV32I: EBREAK
           core_->trigger_ebreak();
           break;
         case 0x002: // URET
@@ -556,40 +678,40 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         csr_value = core_->get_csr(csr_addr, t, id_);
         switch (func3) {
         case 1:
-          // CSRRW
+          // RV32I: CSRRW
           rddata[t] = csr_value;
           core_->set_csr(csr_addr, rsdata[t][0], t, id_);      
           trace->used_iregs.set(rsrc0);
           rd_write = true;
           break;
         case 2:
-          // CSRRS
+          // RV32I: CSRRS
           rddata[t] = csr_value;
           core_->set_csr(csr_addr, csr_value | rsdata[t][0], t, id_);
           trace->used_iregs.set(rsrc0);
           rd_write = true;
           break;
         case 3:
-          // CSRRC
+          // RV32I: CSRRC
           rddata[t] = csr_value;
           core_->set_csr(csr_addr, csr_value & ~rsdata[t][0], t, id_);
           trace->used_iregs.set(rsrc0);
           rd_write = true;
           break;
         case 5:
-          // CSRRWI
+          // RV32I: CSRRWI
           rddata[t] = csr_value;
           core_->set_csr(csr_addr, rsrc0, t, id_);      
           rd_write = true;
           break;
         case 6:
-          // CSRRSI;
+          // RV32I: CSRRSI;
           rddata[t] = csr_value;
           core_->set_csr(csr_addr, csr_value | rsrc0, t, id_);
           rd_write = true;
           break;
         case 7:
-          // CSRRCI
+          // RV32I: CSRRCI
           rddata[t] = csr_value;
           core_->set_csr(csr_addr, csr_value & ~rsrc0, t, id_);
           rd_write = true;
@@ -612,80 +734,177 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
       uint32_t frm = get_fpu_rm(func3, core_, t, id_);
       uint32_t fflags = 0;
       switch (func7) {
-      case 0x00: //FADD
+      case 0x00: // RV32F: FADD.S
         rddata[t] = rv_fadd(rsdata[t][0], rsdata[t][1], frm, &fflags);
         trace->fpu.type = FpuType::FMA;
         trace->used_fregs.set(rsrc0);
         trace->used_fregs.set(rsrc1);
         break;
-      case 0x04: //FSUB
+      case 0x01: // RV32D: FADD.D
+        rddata[t] = rv_fadd_d(rsdata[t][0], rsdata[t][1], frm, &fflags);
+        trace->fpu.type = FpuType::FMA;
+        trace->used_fregs.set(rsrc0);
+        trace->used_fregs.set(rsrc1);
+        break;
+      case 0x04: // RV32F: FSUB.S
         rddata[t] = rv_fsub(rsdata[t][0], rsdata[t][1], frm, &fflags);
         trace->fpu.type = FpuType::FMA;
         trace->used_fregs.set(rsrc0);
         trace->used_fregs.set(rsrc1);
         break;
-      case 0x08: //FMUL
+      case 0x05: // RV32D: FSUB.D
+        rddata[t] = rv_fsub_d(rsdata[t][0], rsdata[t][1], frm, &fflags);
+        trace->fpu.type = FpuType::FMA;
+        trace->used_fregs.set(rsrc0);
+        trace->used_fregs.set(rsrc1);
+        break;
+      case 0x08: // RV32F: FMUL.S
         rddata[t] = rv_fmul(rsdata[t][0], rsdata[t][1], frm, &fflags);
         trace->fpu.type = FpuType::FMA;
         trace->used_fregs.set(rsrc0);
         trace->used_fregs.set(rsrc1);
         break;
-      case 0x0c: //FDIV
+      case 0x09: // RV32F: FMUL.D
+        rddata[t] = rv_fmul_d(rsdata[t][0], rsdata[t][1], frm, &fflags);
+        trace->fpu.type = FpuType::FMA;
+        trace->used_fregs.set(rsrc0);
+        trace->used_fregs.set(rsrc1);
+        break;
+      case 0x0c: // RV32F: FDIV.S
         rddata[t] = rv_fdiv(rsdata[t][0], rsdata[t][1], frm, &fflags);
         trace->fpu.type = FpuType::FDIV;
         trace->used_fregs.set(rsrc0);
         trace->used_fregs.set(rsrc1);
         break;
-      case 0x2c: //FSQRT
+      case 0x0c: // RV32F: FDIV.D
+        rddata[t] = rv_fdiv_d(rsdata[t][0], rsdata[t][1], frm, &fflags);
+        trace->fpu.type = FpuType::FDIV;
+        trace->used_fregs.set(rsrc0);
+        trace->used_fregs.set(rsrc1);
+        break;
+      case 0x2c: // RV32F: FSQRT.S
         rddata[t] = rv_fsqrt(rsdata[t][0], frm, &fflags);
         trace->fpu.type = FpuType::FSQRT;
         trace->used_fregs.set(rsrc0);
-        break;        
+        break;
+      case 0x2d: // RV32D: FSQRT.D
+        rddata[t] = rv_fsqrt_d(rsdata[t][0], frm, &fflags);
+        trace->fpu.type = FpuType::FSQRT;
+        trace->used_fregs.set(rsrc0);
+        break;         
       case 0x10:
         switch (func3) {            
-        case 0: // FSGNJ.S
+        case 0: // RV32F: FSGNJ.S
           rddata[t] = rv_fsgnj(rsdata[t][0], rsdata[t][1]);
           break;          
-        case 1: // FSGNJN.S
+        case 1: // RV32F: FSGNJN.S
           rddata[t] = rv_fsgnjn(rsdata[t][0], rsdata[t][1]);
           break;          
-        case 2: // FSGNJX.S
+        case 2: // RV32F: FSGNJX.S
           rddata[t] = rv_fsgnjx(rsdata[t][0], rsdata[t][1]);
           break;
         }
+      case 0x11:
+        switch (func3) {            
+        case 0: // RV32F: FSGNJ.D
+          rddata[t] = rv_fsgnj_d(rsdata[t][0], rsdata[t][1]);
+          break;          
+        case 1: // RV32F: FSGNJN.D
+          rddata[t] = rv_fsgnjn_d(rsdata[t][0], rsdata[t][1]);
+          break;          
+        case 2: // RV32F: FSGNJX.D
+          rddata[t] = rv_fsgnjx_d(rsdata[t][0], rsdata[t][1]);
+          break;
+        }
         trace->fpu.type = FpuType::FNCP;
         trace->used_fregs.set(rsrc0);
         trace->used_fregs.set(rsrc1);
         break;
       case 0x14:              
         if (func3) {
-          // FMAX.S
+          // RV32F: FMAX.S
           rddata[t] = rv_fmax(rsdata[t][0], rsdata[t][1], &fflags);
         } else {
-          // FMIN.S
+          // RV32F: FMIN.S
           rddata[t] = rv_fmin(rsdata[t][0], rsdata[t][1], &fflags);
         }
         trace->fpu.type = FpuType::FNCP;
         trace->used_fregs.set(rsrc0);
         trace->used_fregs.set(rsrc1);        
         break;
-      case 0x60:
-        if (rsrc1 == 0) { 
-          // FCVT.W.S
-          rddata[t] = rv_ftoi(rsdata[t][0], frm, &fflags);
+      case 0x15:              
+        if (func3) {
+          // RV32D: FMAX.D
+          rddata[t] = rv_fmax_d(rsdata[t][0], rsdata[t][1], &fflags);
         } else {
-          // FCVT.WU.S
-          rddata[t] = rv_ftou(rsdata[t][0], frm, &fflags);
+          // RV32D: FMIN.D
+          rddata[t] = rv_fmin_d(rsdata[t][0], rsdata[t][1], &fflags);
+        }
+        trace->fpu.type = FpuType::FNCP;
+        trace->used_fregs.set(rsrc0);
+        trace->used_fregs.set(rsrc1);        
+        break;
+      case 0x60:
+        switch(rsrc1) {
+          case 0: 
+            // RV32F: FCVT.W.S
+            rddata[t] = sext64(rv_ftoi(rsdata[0], frm, &fflags), 32);
+            break;
+          case 1:
+            // RV32F: FCVT.WU.S
+            rddata[t] = sext64(rv_ftou(rsdata[0], frm, &fflags), 32);
+            break;
+          case 2:
+            // RV64F: FCVT.L.S
+            rddata[t] = rv_ftol(rsdata[0], frm, &fflags);
+            break;
+          case 3:
+            // RV64F: FCVT.LU.S
+            rddata[t] = rv_ftolu(rsdata[0], frm, &fflags);
+            break;
+        }
+        trace->fpu.type = FpuType::FCVT;
+        trace->used_fregs.set(rsrc0);
+        break;
+      case 0x61:
+        switch(rsrc1) {
+          case 0: 
+            // RV32F: FCVT.W.D
+            rddata[t] = sext64(rv_ftoi_d(rsdata[0], frm, &fflags), 32);
+            break;
+          case 1:
+            // RV32F: FCVT.WU.D
+            rddata[t] = sext64(rv_ftou_d(rsdata[0], frm, &fflags), 32);
+            break;
+          case 2:
+            // RV64F: FCVT.L.D
+            rddata[t] = rv_ftol_d(rsdata[0], frm, &fflags);
+            break;
+          case 3:
+            // RV64F: FCVT.LU.D
+            rddata[t] = rv_ftolu_d(rsdata[0], frm, &fflags);
+            break;
         }
         trace->fpu.type = FpuType::FCVT;
         trace->used_fregs.set(rsrc0);
         break;
       case 0x70:      
         if (func3) {
-          // FCLASS.S
+          // RV32F: FCLASS.S
           rddata[t] = rv_fclss(rsdata[t][0]);
         } else {          
-          // FMV.X.W
+          // RV32F: FMV.X.W
+          rddata[t] = rsdata[t][0];
+        }        
+        trace->fpu.type = FpuType::FNCP;
+        trace->used_fregs.set(rsrc0);
+        break;
+      case 0x71:      
+        if (func3) {
+          // RV32D: FCLASS.S
+          rddata[t] = rv_fclss_d(rsdata[t][0]);
+        } else {          
+          // RV64D: FMV.X.D
           rddata[t] = rsdata[t][0];
         }        
         trace->fpu.type = FpuType::FNCP;
@@ -694,35 +913,87 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
       case 0x50:             
         switch(func3) {              
         case 0:
-          // FLE.S
+          // RV32F: FLE.S
           rddata[t] = rv_fle(rsdata[t][0], rsdata[t][1], &fflags);    
           break;              
         case 1:
-          // FLT.S
+          // RV32F: FLT.S
           rddata[t] = rv_flt(rsdata[t][0], rsdata[t][1], &fflags);
           break;              
         case 2:
-          // FEQ.S
+          // RV32F: FEQ.S
           rddata[t] = rv_feq(rsdata[t][0], rsdata[t][1], &fflags);
           break;
         } 
         trace->fpu.type = FpuType::FNCP;
         trace->used_fregs.set(rsrc0);
         trace->used_fregs.set(rsrc1);
+        break;  
+      case 0x51:             
+        switch(func3) {              
+        case 0:
+          // RV32D: FLE.D
+          rddata[t] = rv_fle_d(rsdata[t][0], rsdata[t][1], &fflags);    
+          break;              
+        case 1:
+          // RV32D: FLT.D
+          rddata[t] = rv_flt_d(rsdata[t][0], rsdata[t][1], &fflags);
+          break;              
+        case 2:
+          // RV32D: FEQ.D
+          rddata[t] = rv_feq_d(rsdata[t][0], rsdata[t][1], &fflags);
+          break;
+        } 
+        trace->fpu.type = FpuType::FNCP;
+        trace->used_fregs.set(rsrc0);
+        trace->used_fregs.set(rsrc1);
         break;        
       case 0x68:
-        if (rsrc1) {
-          // FCVT.S.WU:
-          rddata[t] = rv_utof(rsdata[t][0], frm, &fflags);
-        } else {
-          // FCVT.S.W:
-          rddata[t] = rv_itof(rsdata[t][0], frm, &fflags);
+        switch(rsrc1) {
+          case 0: 
+            // RV32F: FCVT.S.W
+            rddata[t] = rv_itof(rsdata[t][0], frm, &fflags);
+            break;
+          case 1:
+            // RV32F: FCVT.S.WU
+            rddata[t] = rv_utof(rsdata[t][0], frm, &fflags);
+            break;
+          case 2:
+            // RV64F: FCVT.S.L
+            rddata[t] = rv_ltof(rsdata[t][0], frm, &fflags);
+            break;
+          case 3:
+            // RV64F: FCVT.S.LU
+            rddata[t] = rv_lutof(rsdata[t][0], frm, &fflags);
+            break;
         }
         trace->fpu.type = FpuType::FCVT;
         trace->used_iregs.set(rsrc0);
         break;
-      case 0x78:
-        // FMV.W.X
+      case 0x69:
+        switch(rsrc1) {
+          case 0: 
+            // RV32D: FCVT.D.W
+            rddata[t] = rv_itof_d(rsdata[t][0], frm, &fflags);
+            break;
+          case 1:
+            // RV32F: FCVT.D.WU
+            rddata[t] = rv_utof_d(rsdata[t][0], frm, &fflags);
+            break;
+          case 2:
+            // RV64D: FCVT.D.L
+            rddata[t] = rv_ltof_d(rsdata[t][0], frm, &fflags);
+            break;
+          case 3:
+            // RV64D: FCVT.D.LU
+            rddata[t] = rv_lutof_d(rsdata[t][0], frm, &fflags);
+            break;
+        }
+        trace->fpu.type = FpuType::FCVT;
+        trace->used_iregs.set(rsrc0);
+        break;
+      case 0x78:  // FMV.W.X
+      case 0x79:  // FMV.D.X
         rddata[t] = rsdata[t][0];
         trace->fpu.type = FpuType::FNCP;
         trace->used_iregs.set(rsrc0);
@@ -747,16 +1018,36 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
       Word fflags = 0;
       switch (opcode) {
       case FMADD:
-        rddata[t] = rv_fmadd(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
+        if (func2)
+          // RV32D: FMADD.D
+          rddata[t] = rv_fmadd_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
+        else
+          // RV32F: FMADD.S
+          rddata[t] = rv_fmadd(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
         break;
       case FMSUB:
-        rddata[t] = rv_fmsub(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
+        if (func2)
+          // RV32D: FMSUB.D
+          rddata[t] = rv_fmsub_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
+        else 
+          // RV32F: FMSUB.S
+          rddata[t] = rv_fmsub(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
         break;
       case FMNMADD:
-        rddata[t] = rv_fnmadd(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
-        break;  
+        if (func2)
+          // RV32D: FNMADD.D
+          rddata[t] = rv_fnmadd_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
+        else
+          // RV32F: FNMADD.S
+          rddata[t] = rv_fnmadd(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
+        break; 
       case FMNMSUB:
-        rddata[t] = rv_fnmsub(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
+        if (func2)
+          // RV32D: FNMSUB.D
+          rddata[t] = rv_fnmsub_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
+        else
+          // RV32F: FNMSUB.S
+          rddata[t] = rv_fnmsub(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
         break;
       default:
         break;
@@ -1832,7 +2123,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
     }
   }
 
-  PC_ += core_->arch().wsize();
+  PC_ += 4;
   if (PC_ != nextPC) {
     DP(3, "*** Next PC: " << std::hex << nextPC << std::dec);
     PC_ = nextPC;
diff --git a/sim/simx/instr.h b/sim/simx/instr.h
index 334b8565..1d4c7699 100644
--- a/sim/simx/instr.h
+++ b/sim/simx/instr.h
@@ -32,6 +32,9 @@ enum Opcode {
   // GPGPU Extension
   GPGPU     = 0x6b,
   GPU       = 0x5b,
+  // RV64 Standard Extensions
+  R_INST_64 = 0x3b,
+  I_INST_64 = 0x1b,
 };
 
 enum InstType { 
@@ -72,7 +75,7 @@ public:
   void setFunc2(Word func2) { func2_ = func2; }
   void setFunc3(Word func3) { func3_ = func3; }
   void setFunc7(Word func7) { func7_ = func7; }
-  void setImm(Word imm) { has_imm_ = true; imm_ = imm; }
+  void setImm(DoubleWord imm) { has_imm_ = true; imm_ = imm; }
   void setVlsWidth(Word width) { vlsWidth_ = width; }
   void setVmop(Word mop) { vMop_ = mop; }
   void setVnf(Word nf) { vNf_ = nf; }
@@ -95,7 +98,7 @@ public:
   int getRDest() const { return rdest_; }  
   RegType getRDType() const { return rdest_type_; }  
   bool hasImm() const { return has_imm_; }
-  Word getImm() const { return imm_; }
+  DoubleWord getImm() const { return imm_; }
   Word getVlsWidth() const { return vlsWidth_; }
   Word getVmop() const { return vMop_; }
   Word getvNf() const { return vNf_; }
@@ -115,7 +118,7 @@ private:
   int num_rsrcs_;
   bool has_imm_;
   RegType rdest_type_;
-  Word imm_;
+  DoubleWord imm_;
   RegType rsrc_type_[MAX_REG_SOURCES];
   int rsrc_[MAX_REG_SOURCES];  
   int rdest_;
diff --git a/sim/simx/pipeline.cpp b/sim/simx/pipeline.cpp
new file mode 100644
index 00000000..c54977a0
--- /dev/null
+++ b/sim/simx/pipeline.cpp
@@ -0,0 +1,63 @@
+#include <iostream>
+#include "pipeline.h"
+
+using namespace vortex;
+
+namespace vortex {
+std::ostream &operator<<(std::ostream &os, const Pipeline& pipeline) {
+  os << pipeline.name_ << ": valid=" << pipeline.valid << std::endl;
+  os << pipeline.name_ << ": stalled=" << pipeline.stalled << std::endl;
+  os << pipeline.name_ << ": stall_warp=" << pipeline.stall_warp << std::endl;      
+  os << pipeline.name_ << ": wid=" << pipeline.wid << std::endl;
+  os << pipeline.name_ << ": PC=" << std::hex << pipeline.PC << std::endl;
+  os << pipeline.name_ << ": used_iregs=" << pipeline.used_iregs << std::endl;
+  os << pipeline.name_ << ": used_fregs=" << pipeline.used_fregs << std::endl;
+  os << pipeline.name_ << ": used_vregs=" << pipeline.used_vregs << std::endl;
+  return os;
+}
+}
+
+Pipeline::Pipeline(const char* name) 
+: name_(name) {
+  this->clear();
+}
+
+void Pipeline::clear() {
+  valid = false;
+  stalled = false;
+  stall_warp = false;
+  wid = 0;
+  PC = 0;
+  used_iregs.reset();
+  used_fregs.reset();
+  used_vregs.reset();
+}
+
+bool Pipeline::enter(Pipeline *drain) {
+  if (drain) {
+    if (drain->stalled) {
+      this->stalled = true;
+      return false;
+    }
+    drain->valid = false;
+  }
+  this->stalled = false;
+  if (!this->valid)
+    return false;
+  return true;
+}
+
+void Pipeline::next(Pipeline *drain) {
+  if (drain) {
+    drain->valid = this->valid;
+    drain->stalled = this->stalled;
+    drain->stall_warp = this->stall_warp;
+    drain->wid = this->wid;
+    drain->PC = this->PC;
+    drain->rdest = this->rdest;
+    drain->rdest_type = this->rdest_type;
+    drain->used_iregs = this->used_iregs;
+    drain->used_fregs = this->used_fregs;
+    drain->used_vregs = this->used_vregs;
+  }
+}
\ No newline at end of file
diff --git a/sim/simx/pipeline.h b/sim/simx/pipeline.h
index 18d54e21..dbd1c972 100644
--- a/sim/simx/pipeline.h
+++ b/sim/simx/pipeline.h
@@ -18,7 +18,7 @@ struct pipeline_trace_t {
   int         cid;
   int         wid;  
   ThreadMask  tmask;
-  Word        PC;
+  DoubleWord        PC;
 
   //--
   bool        fetch_stall;
diff --git a/sim/simx/types.h b/sim/simx/types.h
index 9177dba4..a97b5041 100644
--- a/sim/simx/types.h
+++ b/sim/simx/types.h
@@ -13,8 +13,11 @@ namespace vortex {
 typedef uint8_t  Byte;
 typedef uint32_t Word;
 typedef int32_t  WordI;
+// simx64
+typedef uint64_t DoubleWord;
+typedef int64_t DoubleWordI;
 
-typedef uint32_t Addr;
+typedef uint64_t Addr;
 typedef uint32_t Size;
 
 typedef std::bitset<32> RegMask;
diff --git a/sim/simx/warp.cpp b/sim/simx/warp.cpp
index b05b1246..9fca6595 100644
--- a/sim/simx/warp.cpp
+++ b/sim/simx/warp.cpp
@@ -13,8 +13,8 @@ using namespace vortex;
 Warp::Warp(Core *core, Word id)
     : id_(id)
     , core_(core)
-    , ireg_file_(core->arch().num_threads(), std::vector<Word>(core->arch().num_regs()))
-    , freg_file_(core->arch().num_threads(), std::vector<Word>(core->arch().num_regs()))
+    , ireg_file_(core->arch().num_threads(), std::vector<DoubleWord>(core->arch().num_regs()))
+    , freg_file_(core->arch().num_threads(), std::vector<DoubleWord>(core->arch().num_regs()))
     , vreg_file_(core->arch().num_threads(), std::vector<Byte>(core->arch().vsize()))
 {
   this->clear();
@@ -71,7 +71,7 @@ void Warp::eval(pipeline_trace_t *trace) {
   for (int i = 0; i < core_->arch().num_regs(); ++i) {
     DPN(4, "  %r" << std::setfill('0') << std::setw(2) << std::dec << i << ':');
     for (int j = 0; j < core_->arch().num_threads(); ++j) {
-      DPN(4, ' ' << std::setfill('0') << std::setw(8) << std::hex << ireg_file_.at(j).at(i) << std::setfill(' ') << ' ');
+      DPN(4, ' ' << std::setfill('0') << std::setw(16) << std::hex << ireg_file_.at(j).at(i) << std::setfill(' ') << ' ');
     }
     DPN(4, std::endl);
   }  
diff --git a/sim/simx/warp.h b/sim/simx/warp.h
index 9e9970f3..cfed0933 100644
--- a/sim/simx/warp.h
+++ b/sim/simx/warp.h
@@ -11,7 +11,7 @@ class Core;
 class Instr;
 class pipeline_trace_t;
 struct DomStackEntry {
-  DomStackEntry(const ThreadMask &tmask, Word PC) 
+  DomStackEntry(const ThreadMask &tmask, DoubleWord PC) 
     : tmask(tmask)
     , PC(PC)
     , fallThrough(false)
@@ -26,7 +26,7 @@ struct DomStackEntry {
   {}
 
   ThreadMask tmask;
-  Word PC;
+  DoubleWord PC;
   bool fallThrough;
   bool unanimous;
 };
@@ -66,11 +66,11 @@ public:
     return id_;
   }
 
-  Word getPC() const {
+  DoubleWord getPC() const {
     return PC_;
   }
 
-  void setPC(Word PC) {
+  void setPC(DoubleWord PC) {
     PC_ = PC;
   }
 
@@ -99,11 +99,11 @@ private:
   Core *core_;
   bool active_;
   
-  Word PC_;
+  DoubleWord PC_;
   ThreadMask tmask_;  
   
-  std::vector<std::vector<Word>> ireg_file_;
-  std::vector<std::vector<Word>> freg_file_;
+  std::vector<std::vector<DoubleWord>> ireg_file_;
+  std::vector<std::vector<DoubleWord>> freg_file_;
   std::vector<std::vector<Byte>> vreg_file_;
   std::stack<DomStackEntry> dom_stack_;
 
diff --git a/tests/regression/basic64/Makefile b/tests/regression/basic64/Makefile
new file mode 100644
index 00000000..6d9c842d
--- /dev/null
+++ b/tests/regression/basic64/Makefile
@@ -0,0 +1,74 @@
+RISCV64_TOOLCHAIN_PATH ?= /nethome/ssrivatsan8/riscv
+RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
+VORTEX_DRV_PATH ?= $(realpath ../../../driver)
+VORTEX_RT_PATH ?= $(realpath ../../../runtime)
+
+OPTS ?= -n256
+
+VX_CC  = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc
+VX_CXX = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-g++
+VX_DP  = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objdump
+VX_CP  = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objcopy
+
+# https://www.sifive.com/blog/all-aboard-part-1-compiler-args
+# find march and mabi combinations by navigating to the riscv64-unknown-elf-toolchain directory
+# and running ./riscv64-unknown-elf-gcc --print-multi-lib
+VX_CFLAGS += -march=rv64i -mabi=lp64 -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections
+VX_CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw
+
+VX_LDFLAGS += -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link64.ld -Wl,--noinhibit-exec,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a
+
+VX_SRCS = kernel.c
+
+#CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -pedantic -Wfatal-errors
+CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors
+
+CXXFLAGS += -I$(VORTEX_DRV_PATH)/include
+
+LDFLAGS += -L$(VORTEX_DRV_PATH)/stub -lvortex
+
+PROJECT = basic64
+
+SRCS = main.cpp
+
+all: $(PROJECT) kernel.bin kernel.dump
+
+kernel.dump:  kernel.elf
+	$(VX_DP) -D  kernel.elf > kernel.dump
+
+kernel.bin:  kernel.elf
+	$(VX_CP) -O binary kernel.elf kernel.bin
+
+kernel.elf: $(VX_SRCS)
+	$(VX_CC) $(VX_CFLAGS) $(VX_SRCS) $(VX_LDFLAGS) -o kernel.elf
+
+$(PROJECT): $(SRCS)
+	$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@
+
+run-simx: $(PROJECT) kernel.bin   
+	LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)
+	
+run-fpga: $(PROJECT) kernel.bin   
+	LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)
+
+run-asesim: $(PROJECT) kernel.bin   
+	LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)
+	
+run-vlsim: $(PROJECT) kernel.bin   
+	LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)
+
+run-rtlsim: $(PROJECT) kernel.bin   
+	LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)
+
+.depend: $(SRCS)
+	$(CXX) $(CXXFLAGS) -MM $^ > .depend;
+
+clean:
+	rm -rf $(PROJECT) *.o .depend
+
+clean-all: clean
+	rm -rf *.elf *.bin *.dump
+
+ifneq ($(MAKECMDGOALS),clean)
+    -include .depend
+endif
\ No newline at end of file
diff --git a/tests/regression/basic64/common.h b/tests/regression/basic64/common.h
new file mode 100644
index 00000000..e496cf34
--- /dev/null
+++ b/tests/regression/basic64/common.h
@@ -0,0 +1,12 @@
+#ifndef _COMMON_H_
+#define _COMMON_H_
+
+#define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000
+
+typedef struct {
+  uint32_t count;
+  uint32_t src_ptr;
+  uint32_t dst_ptr;  
+} kernel_arg_t;
+
+#endif
\ No newline at end of file
diff --git a/tests/regression/basic64/kernel.c b/tests/regression/basic64/kernel.c
new file mode 100644
index 00000000..bc5ec076
--- /dev/null
+++ b/tests/regression/basic64/kernel.c
@@ -0,0 +1,16 @@
+#include <stdint.h>
+#include <vx_intrinsics.h>
+#include "common.h"
+
+void main() {
+	kernel_arg_t* arg = (kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR;
+	uint32_t count   = arg->count;
+	int32_t* src_ptr = (int32_t*)arg->src_ptr;
+	int32_t* dst_ptr = (int32_t*)arg->dst_ptr;
+	
+	uint32_t offset  = vx_core_id() * count;
+	
+	for (uint32_t i = 0; i < count; ++i) {
+		dst_ptr[offset + i] = src_ptr[offset + i];
+	}
+}
\ No newline at end of file
diff --git a/tests/regression/basic64/kernel_scheduler.h b/tests/regression/basic64/kernel_scheduler.h
new file mode 100644
index 00000000..8fd7dc28
--- /dev/null
+++ b/tests/regression/basic64/kernel_scheduler.h
@@ -0,0 +1,153 @@
+#include <iostream>
+#include <assert.h>
+
+#define NUM_CORES_MAX 32
+
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+
+struct context_t {
+  uint32_t num_groups[3];
+  uint32_t global_offset[3];
+  uint32_t local_size[3];
+  char * printf_buffer;
+  uint32_t *printf_buffer_position;
+  uint32_t printf_buffer_capacity;
+  uint32_t work_dim;
+};
+
+typedef void (*vx_pocl_workgroup_func) (
+  const void * /* args */,
+	const struct context_t * /* context */,
+	uint32_t /* group_x */,
+	uint32_t /* group_y */,
+	uint32_t /* group_z */
+);
+
+typedef struct {
+  struct context_t * ctx;
+  vx_pocl_workgroup_func pfn;
+  const void * args;
+  int offset; 
+  int N;
+  int R;
+} wspawn_args_t;
+
+void kernel_spawn_callback(int core_id, int NW, int NT, int nW, wspawn_args_t* p_wspawn_args) {
+  assert(nW <= NW);
+  for (int wid = 0; wid < nW; ++wid) {
+    for (int tid = 0; tid < NT; ++tid) {
+      int wK = (p_wspawn_args->N * wid) + MIN(p_wspawn_args->R, wid);
+      int tK = p_wspawn_args->N + (wid < p_wspawn_args->R);
+      int offset = p_wspawn_args->offset + (wK * NT) + (tid * tK);
+
+      int X = p_wspawn_args->ctx->num_groups[0];
+      int Y = p_wspawn_args->ctx->num_groups[1];
+      int XY = X * Y;
+
+      for (int wg_id = offset, N = wg_id + tK; wg_id < N; ++wg_id) {    
+        int k = wg_id / XY;
+        int wg_2d = wg_id - k * XY;
+        int j = wg_2d / X;
+        int i = wg_2d - j * X;
+
+        int gid0 = p_wspawn_args->ctx->global_offset[0] + i;
+        int gid1 = p_wspawn_args->ctx->global_offset[1] + j;
+        int gid2 = p_wspawn_args->ctx->global_offset[2] + k;
+
+        printf("c%d w%d t%d: g={%d, %d, %d}\n", core_id, wid, tid, gid0, gid1, gid2);
+      }
+    }
+  }
+}
+
+void kernel_spawn_remaining_callback(int core_id, int NW, int NT, int wid, int nT, wspawn_args_t* p_wspawn_args) {    
+  assert(wid < NW);
+  assert(nT <= NT);
+  for (int t = 0; t < nT; ++t) {
+    int tid = core_id * NW * NT + wid * NT + t;
+
+    int wg_id = p_wspawn_args->offset + tid;
+
+    int X = p_wspawn_args->ctx->num_groups[0];
+    int Y = p_wspawn_args->ctx->num_groups[1];
+    int XY = X * Y;
+    
+    int k = wg_id / XY;
+    int wg_2d = wg_id - k * XY;
+    int j = wg_2d / X;
+    int i = wg_2d - j * X;
+
+    int gid0 = p_wspawn_args->ctx->global_offset[0] + i;
+    int gid1 = p_wspawn_args->ctx->global_offset[1] + j;
+    int gid2 = p_wspawn_args->ctx->global_offset[2] + k;
+
+    printf("c%d w%d t%d: g={%d, %d, %d}\n", core_id, wid, tid, gid0, gid1, gid2);
+  }
+}
+
+void kernel_run_once(context_t* ctx, int NC, int NW, int NT, int core_id) {
+    // total number of WGs
+    int X = ctx->num_groups[0];
+    int Y = ctx->num_groups[1];
+    int Z = ctx->num_groups[2];
+    int Q = X * Y * Z;
+
+    // current core id
+    if (core_id >= NUM_CORES_MAX)
+      return;
+
+    // calculate necessary active cores
+    int WT = NW * NT;
+    int nC = (Q > WT) ? (Q / WT) : 1;
+    int nc = MIN(nC, NC);
+    if (core_id >= nc)
+      return; // terminate extra cores
+
+    // number of workgroups per core
+    int wgs_per_core = Q / nc;
+    int wgs_per_core0 = wgs_per_core;  
+    if (core_id == (NC-1)) {    
+      int QC_r = Q - (nc * wgs_per_core0); 
+      wgs_per_core0 += QC_r; // last core executes remaining WGs
+    }
+
+    // number of workgroups per warp
+    int nW = wgs_per_core0 / NT;              // total warps per core
+    int rT = wgs_per_core0 - (nW * NT);       // remaining threads
+    int fW = (nW >= NW) ? (nW / NW) : 0;      // full warps iterations
+    int rW = (fW != 0) ? (nW - fW * NW) : 0;  // reamining full warps
+    if (0 == fW)
+      fW = 1;
+
+    //--
+    wspawn_args_t wspawn_args = { ctx, NULL, NULL, core_id * wgs_per_core, fW, rW };
+
+    //--
+    if (nW >= 1)	{ 
+      int nw = MIN(nW, NW);
+      kernel_spawn_callback(core_id, NW, NT, nw, &wspawn_args);
+    }  
+
+    //--    
+    if (rT != 0) {
+      wspawn_args.offset = wgs_per_core0 - rT;
+      kernel_spawn_remaining_callback(core_id, NW, NT, 0, rT, &wspawn_args);
+    }
+  }
+
+  void kernel_run(int X, int Y, int Z, int NC, int NW, int NT) {
+    context_t ctx;
+
+    ctx.num_groups[0] = X;
+    ctx.num_groups[1] = Y;
+    ctx.num_groups[2] = Z;
+    ctx.global_offset[0] = 0;
+    ctx.global_offset[1] = 0;
+    ctx.global_offset[2] = 0;
+
+    for (int cid = 0; cid < NC; ++cid) {
+      kernel_run_once(&ctx, NC, NW, NT, cid);
+    }
+
+    exit (0);
+  }
\ No newline at end of file
diff --git a/tests/regression/basic64/main.cpp b/tests/regression/basic64/main.cpp
new file mode 100755
index 00000000..c92bae8d
--- /dev/null
+++ b/tests/regression/basic64/main.cpp
@@ -0,0 +1,286 @@
+#include <iostream>
+#include <unistd.h>
+#include <string.h>
+#include <vortex.h>
+#include <chrono>
+#include "common.h"
+#include "kernel_scheduler.h"
+
+#define RT_CHECK(_expr)                                         \
+   do {                                                         \
+     int _ret = _expr;                                          \
+     if (0 == _ret)                                             \
+       break;                                                   \
+     printf("Error: '%s' returned %d!\n", #_expr, (int)_ret);   \
+	 cleanup();			                                              \
+     exit(-1);                                                  \
+   } while (false)
+
+///////////////////////////////////////////////////////////////////////////////
+
+const char* kernel_file = "kernel.bin";
+int test = -1;
+uint32_t count = 0;
+
+vx_device_h device = nullptr;
+vx_buffer_h staging_buf = nullptr;
+
+static void show_usage() {
+   std::cout << "Vortex Test." << std::endl;
+   std::cout << "Usage: [-t testno][-k: kernel][-n words][-h: help]" << std::endl;
+}
+
+static void parse_args(int argc, char **argv) {
+  int c;
+  while ((c = getopt(argc, argv, "n:t:k:h?")) != -1) {
+    switch (c) {
+    case 'n':
+      count = atoi(optarg);
+      break;
+    case 't':
+      test = atoi(optarg);
+      break;
+    case 'k':
+      kernel_file = optarg;
+      break;
+    case 'h': 
+    case '?': {
+      show_usage();
+      exit(0);
+    } break;
+    default:
+      show_usage();
+      exit(-1);
+    }
+  }
+}
+
+void cleanup() {
+  if (staging_buf) {
+    vx_buf_release(staging_buf);
+  }
+  if (device) {
+    vx_dev_close(device);
+  }
+}
+
+uint64_t shuffle(int i, uint64_t value) {
+  return (value << i) | (value & ((1 << i)-1));;
+}
+
+int run_memcopy_test(uint32_t dev_addr, uint64_t value, int num_blocks) {
+  int errors = 0;
+  
+  auto time_start = std::chrono::high_resolution_clock::now();
+
+  int num_blocks_8 = (64 * num_blocks) / 8;
+
+  // update source buffer
+  for (int i = 0; i < num_blocks_8; ++i) {
+    ((uint64_t*)vx_host_ptr(staging_buf))[i] = shuffle(i, value);
+  }
+
+  /*for (int i = 0; i < num_blocks; ++i) {
+    std::cout << "data[" << i << "]=0x";
+    for (int j = 7; j >= 0; --j) {
+      std::cout << std::hex << ((uint64_t*)vx_host_ptr(staging_buf))[i * 8 +j];
+    }
+    std::cout << std::endl;
+  }*/
+  
+  // write source buffer to local memory
+  std::cout << "write source buffer to local memory" << std::endl;
+  auto t0 = std::chrono::high_resolution_clock::now();
+  RT_CHECK(vx_copy_to_dev(staging_buf, dev_addr, 64 * num_blocks, 0));
+  auto t1 = std::chrono::high_resolution_clock::now();
+
+  // clear destination buffer
+  for (int i = 0; i < num_blocks_8; ++i) {
+    ((uint64_t*)vx_host_ptr(staging_buf))[i] = 0;
+  }
+
+  // read destination buffer from local memory
+  std::cout << "read destination buffer from local memory" << std::endl;
+  auto t2 = std::chrono::high_resolution_clock::now();
+  RT_CHECK(vx_copy_from_dev(staging_buf, dev_addr, 64 * num_blocks, 0));
+  auto t3 = std::chrono::high_resolution_clock::now();
+
+  // verify result
+  std::cout << "verify result" << std::endl;
+  for (int i = 0; i < num_blocks_8; ++i) {
+    auto curr = ((uint64_t*)vx_host_ptr(staging_buf))[i];
+    auto ref = shuffle(i, value);
+    if (curr != ref) {
+      std::cout << "error at 0x" << std::hex << (dev_addr + 8 * i)
+                << ": actual 0x" << curr << ", expected 0x" << ref << std::endl;
+      ++errors;
+    }
+  } 
+  
+  if (errors != 0) {
+    std::cout << "Found " << std::dec << errors << " errors!" << std::endl;
+    std::cout << "FAILED!" << std::endl;
+    return 1;
+  }
+
+  auto time_end = std::chrono::high_resolution_clock::now();
+
+  double elapsed;
+  elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(t1 - t0).count();  
+  printf("upload time: %lg ms\n", elapsed);
+  elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(t3 - t2).count();  
+  printf("download time: %lg ms\n", elapsed);
+  elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(time_end - time_start).count();  
+  printf("Total elapsed time: %lg ms\n", elapsed);
+
+  return 0;
+}
+
+int run_kernel_test(const kernel_arg_t& kernel_arg, 
+                    uint32_t buf_size, 
+                    uint32_t num_points) {
+  int errors = 0; 
+
+  auto time_start = std::chrono::high_resolution_clock::now();
+  
+  // update source buffer
+  {
+    auto buf_ptr = (int32_t*)vx_host_ptr(staging_buf);
+    for (uint32_t i = 0; i < num_points; ++i) {
+      buf_ptr[i] = i;
+    }
+  }
+  std::cout << "upload source buffer" << std::endl;
+  auto t0 = std::chrono::high_resolution_clock::now();
+  RT_CHECK(vx_copy_to_dev(staging_buf, kernel_arg.src_ptr, buf_size, 0));
+  auto t1 = std::chrono::high_resolution_clock::now();
+
+  // clear destination buffer
+  {
+    auto buf_ptr = (int32_t*)vx_host_ptr(staging_buf);
+    for (uint32_t i = 0; i < num_points; ++i) {
+      buf_ptr[i] = 0xdeadbeef;
+    }
+  }  
+  std::cout << "clear destination buffer" << std::endl;
+  RT_CHECK(vx_copy_to_dev(staging_buf, kernel_arg.dst_ptr, buf_size, 0));
+
+  // start device
+  std::cout << "start execution" << std::endl;
+  auto t2 = std::chrono::high_resolution_clock::now();
+  RT_CHECK(vx_start(device));
+  RT_CHECK(vx_ready_wait(device, -1));
+  auto t3 = std::chrono::high_resolution_clock::now();
+
+  // read destination buffer from local memory
+  std::cout << "read destination buffer from local memory" << std::endl;
+  auto t4 = std::chrono::high_resolution_clock::now();
+  RT_CHECK(vx_copy_from_dev(staging_buf, kernel_arg.dst_ptr, buf_size, 0));
+  auto t5 = std::chrono::high_resolution_clock::now();
+
+  
+  // verify result
+  std::cout << "verify result" << std::endl;
+  for (uint32_t i = 0; i < num_points; ++i) {
+    int32_t curr = ((int32_t*)vx_host_ptr(staging_buf))[i];
+    int32_t ref = i;
+    if (curr != ref) {
+      std::cout << "error at result #" << std::dec << i
+                << std::hex << ": actual 0x" << curr << ", expected 0x" << ref << std::endl;
+      ++errors;
+    }
+  } 
+  
+  if (errors != 0) {
+    std::cout << "Found " << std::dec << errors << " errors!" << std::endl;
+    std::cout << "FAILED!" << std::endl;
+    return 1;
+  }
+
+  auto time_end = std::chrono::high_resolution_clock::now();
+
+  double elapsed;
+  elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(t1 - t0).count();  
+  printf("upload time: %lg ms\n", elapsed);
+  elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(t3 - t2).count();  
+  printf("execute time: %lg ms\n", elapsed);
+  elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(t5 - t4).count();  
+  printf("download time: %lg ms\n", elapsed);
+  elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(time_end - time_start).count();  
+  printf("Total elapsed time: %lg ms\n", elapsed);
+
+  return 0;
+}
+
+int main(int argc, char *argv[]) {
+
+  size_t value; 
+  kernel_arg_t kernel_arg;
+
+  // parse command arguments
+  parse_args(argc, argv);
+
+  if (count == 0) {
+    count = 1;
+  }
+
+  // open device connection
+  std::cout << "open device connection" << std::endl;
+  RT_CHECK(vx_dev_open(&device));
+  
+  unsigned max_cores;
+  RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_CORES, &max_cores));
+  uint32_t num_points = count;
+  uint32_t num_blocks = (num_points * sizeof(int32_t) + 63) / 64;
+  uint32_t buf_size   = num_blocks * 64;
+
+  std::cout << "number of points: " << num_points << std::endl;
+  std::cout << "buffer size: " << buf_size << " bytes" << std::endl;
+
+  // allocate device memory
+  RT_CHECK(vx_alloc_dev_mem(device, buf_size, &value));
+  kernel_arg.src_ptr = value;
+  RT_CHECK(vx_alloc_dev_mem(device, buf_size, &value));
+  kernel_arg.dst_ptr = value;
+
+  kernel_arg.count = num_points;
+
+  std::cout << "dev_src=" << std::hex << kernel_arg.src_ptr << std::endl;
+  std::cout << "dev_dst=" << std::hex << kernel_arg.dst_ptr << std::endl;
+
+  // allocate shared memory  
+  std::cout << "allocate shared memory" << std::endl;
+  uint32_t alloc_size = std::max<uint32_t>(buf_size, sizeof(kernel_arg_t));
+  RT_CHECK(vx_alloc_shared_mem(device, alloc_size, &staging_buf));
+
+  // run tests  
+  if (0 == test || -1 == test) {
+    std::cout << "run memcopy test" << std::endl;
+    RT_CHECK(run_memcopy_test(kernel_arg.src_ptr, 0x0badf00d40ff40ff, num_blocks));
+  }
+
+  if (1 == test || -1 == test) {
+    // upload program
+    std::cout << "upload program" << std::endl;  
+    RT_CHECK(vx_upload_kernel_file(device, kernel_file));
+
+    // upload kernel argument
+    std::cout << "upload kernel argument" << std::endl;
+    {
+      auto buf_ptr = (void*)vx_host_ptr(staging_buf);
+      memcpy(buf_ptr, &kernel_arg, sizeof(kernel_arg_t));
+      RT_CHECK(vx_copy_to_dev(staging_buf, KERNEL_ARG_DEV_MEM_ADDR, sizeof(kernel_arg_t), 0));
+    }
+
+    std::cout << "run kernel test" << std::endl;
+    RT_CHECK(run_kernel_test(kernel_arg, buf_size, num_points));
+  }
+
+  // cleanup
+  std::cout << "cleanup" << std::endl;  
+  cleanup();
+
+  std::cout << "Test PASSED" << std::endl;  
+  
+  return 0;
+}
\ No newline at end of file
diff --git a/tests/riscv/isa64/Makefile b/tests/riscv/isa64/Makefile
new file mode 100644
index 00000000..136ea5e2
--- /dev/null
+++ b/tests/riscv/isa64/Makefile
@@ -0,0 +1,43 @@
+# ALL_TESTS := $(wildcard *.hex)
+
+# D_TESTS := $(wildcard *ud-p-*.hex)
+# V_TESTS := $(wildcard *-v-*.hex)
+# M_TESTS := $(wildcard *um-*.hex)
+# A_TESTS := $(wildcard *ua-*.hex)
+
+# EXCLUDED_TESTS := $(V_TESTS) $(D_TESTS) $(M_TESTS) $(A_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex
+
+# TESTS := $(filter-out $(EXCLUDED_TESTS), $(ALL_TESTS))
+
+ALL_TESTS := $(wildcard *.hex)
+
+EXCLUDED_TESTS := rv64ud-p-move.hex
+
+I_TESTS := $(wildcard *ui-p-*.hex)
+M_TESTS := $(wildcard *um-p-*.hex)
+F_TESTS := $(wildcard *uf-p-*.hex)
+D_TESTS := $(filter-out $(EXCLUDED_TESTS), $(wildcard *ud-p-*.hex))
+
+TESTS := $(I_TESTS) $(M_TESTS) $(F_TESTS) $(D_TESTS)
+
+all:
+
+run-simx-i:	
+	$(foreach test, $(I_TESTS), ../../../sim/simX/simX -r -a rv64i -c 1 -i $(test) || exit;)
+
+run-simx-m:	
+	$(foreach test, $(M_TESTS), ../../../sim/simX/simX -r -a rv64im -c 1 -i $(test) || exit;)
+
+run-simx-f:	
+	$(foreach test, $(F_TESTS), ../../../sim/simX/simX -r -a rv64imf -c 1 -i $(test) || exit;)
+
+run-simx-d:	
+	$(foreach test, $(D_TESTS), ../../../sim/simX/simX -r -a rv64imfd -c 1 -i $(test) || exit;)
+
+run-simx:	
+	$(foreach test, $(TESTS), ../../../sim/simX/simX -r -a rv64i -c 1 -i $(test) || exit;)
+
+run-rtlsim:
+	$(foreach test, $(TESTS), ../../../sim/rtlsim/rtlsim -r $(test) || exit;)
+
+clean:
\ No newline at end of file
diff --git a/tests/riscv/isa64/rv64ud-p-fadd.hex b/tests/riscv/isa64/rv64ud-p-fadd.hex
new file mode 100644
index 00000000..2adb634b
--- /dev/null
+++ b/tests/riscv/isa64/rv64ud-p-fadd.hex
@@ -0,0 +1,92 @@
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diff --git a/tests/riscv/isa64/rv64ud-p-fclass.hex b/tests/riscv/isa64/rv64ud-p-fclass.hex
new file mode 100644
index 00000000..f795d599
--- /dev/null
+++ b/tests/riscv/isa64/rv64ud-p-fclass.hex
@@ -0,0 +1,56 @@
+:0200000480007A
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diff --git a/tests/riscv/isa64/rv64ud-p-fcmp.hex b/tests/riscv/isa64/rv64ud-p-fcmp.hex
new file mode 100644
index 00000000..58a009a7
--- /dev/null
+++ b/tests/riscv/isa64/rv64ud-p-fcmp.hex
@@ -0,0 +1,114 @@
+:0200000480007A
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new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ud-p-ldst.hex b/tests/riscv/isa64/rv64ud-p-ldst.hex
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new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ud-p-structural.hex b/tests/riscv/isa64/rv64ud-p-structural.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64uf-p-fadd.hex b/tests/riscv/isa64/rv64uf-p-fadd.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64uf-p-recoding.hex b/tests/riscv/isa64/rv64uf-p-recoding.hex
new file mode 100644
index 00000000..a2c4034a
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diff --git a/tests/riscv/isa64/rv64ui-p-add.hex b/tests/riscv/isa64/rv64ui-p-add.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-addi.hex b/tests/riscv/isa64/rv64ui-p-addi.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-addiw.hex b/tests/riscv/isa64/rv64ui-p-addiw.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-addw.hex b/tests/riscv/isa64/rv64ui-p-addw.hex
new file mode 100644
index 00000000..5be931d8
--- /dev/null
+++ b/tests/riscv/isa64/rv64ui-p-addw.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-and.hex b/tests/riscv/isa64/rv64ui-p-and.hex
new file mode 100644
index 00000000..958131df
--- /dev/null
+++ b/tests/riscv/isa64/rv64ui-p-and.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-andi.hex b/tests/riscv/isa64/rv64ui-p-andi.hex
new file mode 100644
index 00000000..0cfdbf04
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+++ b/tests/riscv/isa64/rv64ui-p-andi.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-auipc.hex b/tests/riscv/isa64/rv64ui-p-auipc.hex
new file mode 100644
index 00000000..f1b272f5
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diff --git a/tests/riscv/isa64/rv64ui-p-beq.hex b/tests/riscv/isa64/rv64ui-p-beq.hex
new file mode 100644
index 00000000..63a7763e
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diff --git a/tests/riscv/isa64/rv64ui-p-bgeu.hex b/tests/riscv/isa64/rv64ui-p-bgeu.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-blt.hex b/tests/riscv/isa64/rv64ui-p-blt.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-bltu.hex b/tests/riscv/isa64/rv64ui-p-bltu.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-bne.hex b/tests/riscv/isa64/rv64ui-p-bne.hex
new file mode 100644
index 00000000..bee17982
--- /dev/null
+++ b/tests/riscv/isa64/rv64ui-p-bne.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-fence_i.hex b/tests/riscv/isa64/rv64ui-p-fence_i.hex
new file mode 100644
index 00000000..b24865a1
--- /dev/null
+++ b/tests/riscv/isa64/rv64ui-p-fence_i.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-jal.hex b/tests/riscv/isa64/rv64ui-p-jal.hex
new file mode 100644
index 00000000..f18e9b36
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diff --git a/tests/riscv/isa64/rv64ui-p-jalr.hex b/tests/riscv/isa64/rv64ui-p-jalr.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-lb.hex b/tests/riscv/isa64/rv64ui-p-lb.hex
new file mode 100644
index 00000000..c8624213
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diff --git a/tests/riscv/isa64/rv64ui-p-lbu.hex b/tests/riscv/isa64/rv64ui-p-lbu.hex
new file mode 100644
index 00000000..48c545bc
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diff --git a/tests/riscv/isa64/rv64ui-p-ld.hex b/tests/riscv/isa64/rv64ui-p-ld.hex
new file mode 100644
index 00000000..d0b0253d
--- /dev/null
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diff --git a/tests/riscv/isa64/rv64ui-p-lh.hex b/tests/riscv/isa64/rv64ui-p-lh.hex
new file mode 100644
index 00000000..2a79b236
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diff --git a/tests/riscv/isa64/rv64ui-p-lhu.hex b/tests/riscv/isa64/rv64ui-p-lhu.hex
new file mode 100644
index 00000000..f9caef43
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diff --git a/tests/riscv/isa64/rv64ui-p-lui.hex b/tests/riscv/isa64/rv64ui-p-lui.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-lw.hex b/tests/riscv/isa64/rv64ui-p-lw.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-lwu.hex b/tests/riscv/isa64/rv64ui-p-lwu.hex
new file mode 100644
index 00000000..11dedbf4
--- /dev/null
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diff --git a/tests/riscv/isa64/rv64ui-p-or.hex b/tests/riscv/isa64/rv64ui-p-or.hex
new file mode 100644
index 00000000..2a7b679c
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diff --git a/tests/riscv/isa64/rv64ui-p-ori.hex b/tests/riscv/isa64/rv64ui-p-ori.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-sb.hex b/tests/riscv/isa64/rv64ui-p-sb.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-sd.hex b/tests/riscv/isa64/rv64ui-p-sd.hex
new file mode 100644
index 00000000..35487362
--- /dev/null
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diff --git a/tests/riscv/isa64/rv64ui-p-sh.hex b/tests/riscv/isa64/rv64ui-p-sh.hex
new file mode 100644
index 00000000..cc46d23f
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diff --git a/tests/riscv/isa64/rv64ui-p-simple.hex b/tests/riscv/isa64/rv64ui-p-simple.hex
new file mode 100644
index 00000000..0839fdba
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+++ b/tests/riscv/isa64/rv64ui-p-simple.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-sll.hex b/tests/riscv/isa64/rv64ui-p-sll.hex
new file mode 100644
index 00000000..ff5c32af
--- /dev/null
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diff --git a/tests/riscv/isa64/rv64ui-p-slli.hex b/tests/riscv/isa64/rv64ui-p-slli.hex
new file mode 100644
index 00000000..64e2772d
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diff --git a/tests/riscv/isa64/rv64ui-p-slliw.hex b/tests/riscv/isa64/rv64ui-p-slliw.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-sllw.hex b/tests/riscv/isa64/rv64ui-p-sllw.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-slt.hex b/tests/riscv/isa64/rv64ui-p-slt.hex
new file mode 100644
index 00000000..da77f17c
--- /dev/null
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diff --git a/tests/riscv/isa64/rv64ui-p-slti.hex b/tests/riscv/isa64/rv64ui-p-slti.hex
new file mode 100644
index 00000000..877b6b11
--- /dev/null
+++ b/tests/riscv/isa64/rv64ui-p-slti.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-sltiu.hex b/tests/riscv/isa64/rv64ui-p-sltiu.hex
new file mode 100644
index 00000000..3c2ed7f0
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diff --git a/tests/riscv/isa64/rv64ui-p-sltu.hex b/tests/riscv/isa64/rv64ui-p-sltu.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-sra.hex b/tests/riscv/isa64/rv64ui-p-sra.hex
new file mode 100644
index 00000000..093878c0
--- /dev/null
+++ b/tests/riscv/isa64/rv64ui-p-sra.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-srai.hex b/tests/riscv/isa64/rv64ui-p-srai.hex
new file mode 100644
index 00000000..428ef673
--- /dev/null
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diff --git a/tests/riscv/isa64/rv64ui-p-sraiw.hex b/tests/riscv/isa64/rv64ui-p-sraiw.hex
new file mode 100644
index 00000000..257d8a16
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diff --git a/tests/riscv/isa64/rv64ui-p-sraw.hex b/tests/riscv/isa64/rv64ui-p-sraw.hex
new file mode 100644
index 00000000..234bc98f
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diff --git a/tests/riscv/isa64/rv64ui-p-srl.hex b/tests/riscv/isa64/rv64ui-p-srl.hex
new file mode 100644
index 00000000..3d73c116
--- /dev/null
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diff --git a/tests/riscv/isa64/rv64ui-p-srli.hex b/tests/riscv/isa64/rv64ui-p-srli.hex
new file mode 100644
index 00000000..29911e99
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diff --git a/tests/riscv/isa64/rv64ui-p-srliw.hex b/tests/riscv/isa64/rv64ui-p-srliw.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-srlw.hex b/tests/riscv/isa64/rv64ui-p-srlw.hex
new file mode 100644
index 00000000..4008588f
--- /dev/null
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diff --git a/tests/riscv/isa64/rv64ui-p-sub.hex b/tests/riscv/isa64/rv64ui-p-sub.hex
new file mode 100644
index 00000000..89ba9bc9
--- /dev/null
+++ b/tests/riscv/isa64/rv64ui-p-sub.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-subw.hex b/tests/riscv/isa64/rv64ui-p-subw.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64ui-p-sw.hex b/tests/riscv/isa64/rv64ui-p-sw.hex
new file mode 100644
index 00000000..405f6f9b
--- /dev/null
+++ b/tests/riscv/isa64/rv64ui-p-sw.hex
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diff --git a/tests/riscv/isa64/rv64ui-p-xor.hex b/tests/riscv/isa64/rv64ui-p-xor.hex
new file mode 100644
index 00000000..090f1253
--- /dev/null
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diff --git a/tests/riscv/isa64/rv64ui-p-xori.hex b/tests/riscv/isa64/rv64ui-p-xori.hex
new file mode 100644
index 00000000..3b2340da
--- /dev/null
+++ b/tests/riscv/isa64/rv64ui-p-xori.hex
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diff --git a/tests/riscv/isa64/rv64um-p-div.hex b/tests/riscv/isa64/rv64um-p-div.hex
new file mode 100644
index 00000000..dcb0cdc8
--- /dev/null
+++ b/tests/riscv/isa64/rv64um-p-div.hex
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diff --git a/tests/riscv/isa64/rv64um-p-divu.hex b/tests/riscv/isa64/rv64um-p-divu.hex
new file mode 100644
index 00000000..48617602
--- /dev/null
+++ b/tests/riscv/isa64/rv64um-p-divu.hex
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diff --git a/tests/riscv/isa64/rv64um-p-divuw.hex b/tests/riscv/isa64/rv64um-p-divuw.hex
new file mode 100644
index 00000000..75338393
--- /dev/null
+++ b/tests/riscv/isa64/rv64um-p-divuw.hex
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diff --git a/tests/riscv/isa64/rv64um-p-divw.hex b/tests/riscv/isa64/rv64um-p-divw.hex
new file mode 100644
index 00000000..b379b8a1
--- /dev/null
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diff --git a/tests/riscv/isa64/rv64um-p-mul.hex b/tests/riscv/isa64/rv64um-p-mul.hex
new file mode 100644
index 00000000..b6536ff1
--- /dev/null
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diff --git a/tests/riscv/isa64/rv64um-p-mulh.hex b/tests/riscv/isa64/rv64um-p-mulh.hex
new file mode 100644
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diff --git a/tests/riscv/isa64/rv64um-p-mulhsu.hex b/tests/riscv/isa64/rv64um-p-mulhsu.hex
new file mode 100644
index 00000000..1f5f9260
--- /dev/null
+++ b/tests/riscv/isa64/rv64um-p-mulhsu.hex
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diff --git a/tests/riscv/isa64/rv64um-p-mulhu.hex b/tests/riscv/isa64/rv64um-p-mulhu.hex
new file mode 100644
index 00000000..828ccc38
--- /dev/null
+++ b/tests/riscv/isa64/rv64um-p-mulhu.hex
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diff --git a/tests/riscv/isa64/rv64um-p-mulw.hex b/tests/riscv/isa64/rv64um-p-mulw.hex
new file mode 100644
index 00000000..6de52e5e
--- /dev/null
+++ b/tests/riscv/isa64/rv64um-p-mulw.hex
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diff --git a/tests/riscv/isa64/rv64um-p-rem.hex b/tests/riscv/isa64/rv64um-p-rem.hex
new file mode 100644
index 00000000..6c5728b4
--- /dev/null
+++ b/tests/riscv/isa64/rv64um-p-rem.hex
@@ -0,0 +1,52 @@
+:0200000480007A
+:100000006F008004732F2034930F80006308FF0378
+:10001000930F90006304FF03930FB0006300FF038E
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diff --git a/tests/riscv/isa64/rv64um-p-remu.hex b/tests/riscv/isa64/rv64um-p-remu.hex
new file mode 100644
index 00000000..ba81a927
--- /dev/null
+++ b/tests/riscv/isa64/rv64um-p-remu.hex
@@ -0,0 +1,52 @@
+:0200000480007A
+:100000006F008004732F2034930F80006308FF0378
+:10001000930F90006304FF03930FB0006300FF038E
+:10002000130F000063040F0067000F00732F2034CC
+:1000300063540F006F00400093E19153171F0000BD
+:1000400023223FFC6FF09FFF93000000130100008C
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+:100060009303000013040000930400001305000034
+:10007000930500001306000093060000130700001C
+:100080009307000013080000930800001309000004
+:1000900093090000130A0000930A0000130B0000EC
+:1000A000930B0000130C0000930C0000130D0000D4
+:1000B000930D0000130E0000930E0000130F0000BC
+:1000C000930F0000732540F16310050097020000B4
+:1000D000938202017390523073500018970200000F
+:1000E00093824202739052309B021000939252030B
+:1000F0009382F2FF7390023B9302F0017390023AF5
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+:100240009303100093019000631077029300000065
+:100250001301000033F72002930300009301A00074
+:1002600063147700631030020F00F00F6380010009
+:100270009391110093E111009308D00513850100BB
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+:0C02B00000000000000000000000000042
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+:1010300000000000000000000000000000000000B0
+:081040000000000000000000A8
+:040000058000000077
+:00000001FF
diff --git a/tests/riscv/isa64/rv64um-p-remuw.hex b/tests/riscv/isa64/rv64um-p-remuw.hex
new file mode 100644
index 00000000..39493b38
--- /dev/null
+++ b/tests/riscv/isa64/rv64um-p-remuw.hex
@@ -0,0 +1,52 @@
+:0200000480007A
+:100000006F008004732F2034930F80006308FF0378
+:10001000930F90006304FF03930FB0006300FF038E
+:10002000130F000063040F0067000F00732F2034CC
+:1000300063540F006F00400093E19153171F0000BD
+:1000400023223FFC6FF09FFF93000000130100008C
+:10005000930100001302000093020000130300004C
+:100060009303000013040000930400001305000034
+:10007000930500001306000093060000130700001C
+:100080009307000013080000930800001309000004
+:1000900093090000130A0000930A0000130B0000EC
+:1000A000930B0000130C0000930C0000130D0000D4
+:1000B000930D0000130E0000930E0000130F0000BC
+:1000C000930F0000732540F16310050097020000B4
+:1000D000938202017390523073500018970200000F
+:1000E00093824202739052309B021000939252030B
+:1000F0009382F2FF7390023B9302F0017390023AF5
+:100100007350403097020000938242017390523046
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diff --git a/tests/riscv/isa64/rv64um-p-remw.hex b/tests/riscv/isa64/rv64um-p-remw.hex
new file mode 100644
index 00000000..4c849829
--- /dev/null
+++ b/tests/riscv/isa64/rv64um-p-remw.hex
@@ -0,0 +1,52 @@
+:0200000480007A
+:100000006F008004732F2034930F80006308FF0378
+:10001000930F90006304FF03930FB0006300FF038E
+:10002000130F000063040F0067000F00732F2034CC
+:1000300063540F006F00400093E19153171F0000BD
+:1000400023223FFC6FF09FFF93000000130100008C
+:10005000930100001302000093020000130300004C
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+:10007000930500001306000093060000130700001C
+:100080009307000013080000930800001309000004
+:1000900093090000130A0000930A0000130B0000EC
+:1000A000930B0000130C0000930C0000130D0000D4
+:1000B000930D0000130E0000930E0000130F0000BC
+:1000C000930F0000732540F16310050097020000B4
+:1000D000938202017390523073500018970200000F
+:1000E00093824202739052309B021000939252030B
+:1000F0009382F2FF7390023B9302F0017390023AF5
+:100100007350403097020000938242017390523046
+:10011000735020307350303093010000970200007C
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diff --git a/tests/runtime/Makefile b/tests/runtime/Makefile
index f420f31c..a6869135 100644
--- a/tests/runtime/Makefile
+++ b/tests/runtime/Makefile
@@ -11,10 +11,10 @@ run-simx:
 run-rtlsim:
 	$(MAKE) -C hello run-rtlsim
 	$(MAKE) -C fibonacci run-rtlsim
-	$(MAKE) -C simple run-rtlsim
+	$(MAKE) -C simple run-rtlsim	
 
 clean:
 	$(MAKE) -C hello clean
 	$(MAKE) -C fibonacci clean
-	$(MAKE) -C simple clean
+	$(MAKE) -C simple clean	
 
diff --git a/tests/runtime/hello64/Makefile b/tests/runtime/hello64/Makefile
new file mode 100644
index 00000000..dbf04c83
--- /dev/null
+++ b/tests/runtime/hello64/Makefile
@@ -0,0 +1,42 @@
+RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
+RISCV64_TOOLCHAIN_PATH ?= /nethome/ssrivatsan8/riscv
+VORTEX_RT_PATH ?= $(realpath ../../../runtime)
+
+CC = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc
+AR = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc-ar
+DP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objdump
+CP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objcopy
+
+CFLAGS += -march=rv64imfd -mabi=lp64d -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections
+CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw
+
+LDFLAGS += -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link64.ld -Wl,--gc-sections 
+
+# $(VORTEX_RT_PATH)/libvortexrt.a
+
+PROJECT = hello64
+
+SRCS = main.cpp $(VORTEX_RT_PATH)/src/vx_start.S $(VORTEX_RT_PATH)/src/vx_syscalls.c
+
+all: $(PROJECT).elf $(PROJECT).bin $(PROJECT).dump
+
+$(PROJECT).dump: $(PROJECT).elf
+	$(DP) -D $(PROJECT).elf > $(PROJECT).dump
+
+$(PROJECT).bin: $(PROJECT).elf
+	$(CP) -O binary $(PROJECT).elf $(PROJECT).bin
+
+$(PROJECT).elf: $(SRCS)
+	$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
+
+run-rtlsim: $(PROJECT).bin
+	../../../sim/rtlsim/rtlsim $(PROJECT).bin
+
+run-simx: $(PROJECT).bin
+	../../../sim/simX/simX -a rv64i -c 1 -i $(PROJECT).bin
+
+.depend: $(SRCS)
+	$(CC) $(CFLAGS) -MM $^ > .depend;
+
+clean:
+	rm -rf *.elf *.bin *.dump .depend 
diff --git a/tests/runtime/hello64/main.cpp b/tests/runtime/hello64/main.cpp
new file mode 100644
index 00000000..d9ad0537
--- /dev/null
+++ b/tests/runtime/hello64/main.cpp
@@ -0,0 +1,6 @@
+#include <stdio.h>
+
+int main()
+{
+	return 0;
+}
\ No newline at end of file
diff --git a/tests/runtime/simple64/Makefile b/tests/runtime/simple64/Makefile
new file mode 100644
index 00000000..1ccf20cf
--- /dev/null
+++ b/tests/runtime/simple64/Makefile
@@ -0,0 +1,40 @@
+RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
+RISCV64_TOOLCHAIN_PATH ?= /nethome/ssrivatsan8/riscv
+VORTEX_RT_PATH ?= $(realpath ../../../runtime)
+
+CC = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc
+AR = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc-ar
+DP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objdump
+CP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objcopy
+
+CFLAGS += -march=rv64imfd -mabi=lp64d -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections
+CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw
+
+LDFLAGS += -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link64.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a
+
+PROJECT = simple64
+
+SRCS = main.cpp
+
+all: $(PROJECT).elf $(PROJECT).bin $(PROJECT).dump
+
+$(PROJECT).dump: $(PROJECT).elf
+	$(DP) -D $(PROJECT).elf > $(PROJECT).dump
+
+$(PROJECT).bin: $(PROJECT).elf
+	$(CP) -O binary $(PROJECT).elf $(PROJECT).bin
+
+$(PROJECT).elf: $(SRCS)
+	$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
+
+run-rtlsim: $(PROJECT).bin
+	../../../sim/rtlsim/rtlsim $(PROJECT).bin
+
+run-simx: $(PROJECT).bin
+	../../../sim/simX/simX -a rv64i -c 1 -i $(PROJECT).bin
+
+.depend: $(SRCS)
+	$(CC) $(CFLAGS) -MM $^ > .depend;
+
+clean:
+	rm -rf *.elf *.bin *.dump .depend 
diff --git a/tests/runtime/simple64/main.cpp b/tests/runtime/simple64/main.cpp
new file mode 100644
index 00000000..68e00b3a
--- /dev/null
+++ b/tests/runtime/simple64/main.cpp
@@ -0,0 +1,5 @@
+int main()
+{
+	int num=1+2;
+	return 0;
+}
\ No newline at end of file