From 614797e52f9e3d0da523efed67a45fb7ff147138 Mon Sep 17 00:00:00 2001
From: felsabbagh3 <felsabbagh3@gatech.edu>
Date: Fri, 27 Mar 2020 13:15:23 -0700
Subject: [PATCH] Migrating fpga_synthesis_temp to main

---
 rtl/VX_cache/VX_tag_data_access.v     |  2 +-
 rtl/VX_cache/VX_tag_data_structure.v  |  3 ++-
 rtl/VX_define.v                       |  2 +-
 rtl/VX_lsu.v                          | 12 +++++++++++-
 runtime/mains/simple/vx_simple_main.c | 19 ++++++++++---------
 5 files changed, 25 insertions(+), 13 deletions(-)

diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v
index b69d6a89..2c8417b8 100644
--- a/rtl/VX_cache/VX_tag_data_access.v
+++ b/rtl/VX_cache/VX_tag_data_access.v
@@ -262,7 +262,7 @@ module VX_tag_data_access
 		end
 	endgenerate
 
-	assign use_write_enable = we;
+	assign use_write_enable = (writefill_st1e && !real_writefill) ? 0 : we;
 	assign use_write_data   = data_write;
 
 ///////////////////////
diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v
index 55b9cc9e..71c7a82d 100644
--- a/rtl/VX_cache/VX_tag_data_structure.v
+++ b/rtl/VX_cache/VX_tag_data_structure.v
@@ -71,7 +71,8 @@ module VX_tag_data_structure
     reg                                    dirty[`BANK_LINE_COUNT-1:0];
 
 
-    wire[`TAG_SELECT_SIZE_RNG] kkkkkk = write_addr[`TAG_SELECT_ADDR_RNG];
+    wire[`TAG_SELECT_ADDR_RNG]  curr_tag = write_addr[`TAG_SELECT_ADDR_RNG];
+    wire[`LINE_SELECT_ADDR_RNG] curr_inx = write_addr[`LINE_SELECT_ADDR_RNG];
 
     assign read_valid = valid[read_addr[`LINE_SELECT_ADDR_RNG]];
     assign read_dirty = dirty[read_addr[`LINE_SELECT_ADDR_RNG]];
diff --git a/rtl/VX_define.v b/rtl/VX_define.v
index 7c0840fd..97749c83 100644
--- a/rtl/VX_define.v
+++ b/rtl/VX_define.v
@@ -12,7 +12,7 @@
 `endif
 
 `ifndef NUMBER_CORES_PER_CLUSTER
-`define NUMBER_CORES_PER_CLUSTER 2
+`define NUMBER_CORES_PER_CLUSTER 1
 `endif
 
 `ifndef NUMBER_CLUSTERS
diff --git a/rtl/VX_lsu.v b/rtl/VX_lsu.v
index b962b738..a0abf1ff 100644
--- a/rtl/VX_lsu.v
+++ b/rtl/VX_lsu.v
@@ -69,7 +69,16 @@ module VX_lsu (
 	assign VX_mem_wb.wb_valid    = VX_dcache_rsp.core_wb_valid;
 	assign VX_mem_wb.wb_warp_num = VX_dcache_rsp.core_wb_warp_num;
 	assign VX_mem_wb.loaded_data = VX_dcache_rsp.core_wb_readdata;
-	assign VX_mem_wb.mem_wb_pc   = VX_dcache_rsp.core_wb_pc[0];
+	
+	wire[(`CLOG2(`NT))-1:0] use_pc_index;
+	wire found;
+	VX_generic_priority_encoder #(.N(`NT)) pick_first_pc(
+		.valids(VX_dcache_rsp.core_wb_valid),
+		.index (use_pc_index),
+		.found (found)
+		);
+
+	assign VX_mem_wb.mem_wb_pc   = VX_dcache_rsp.core_wb_pc[use_pc_index];
 
 
 
@@ -78,3 +87,4 @@ module VX_lsu (
 endmodule // Memory
 
 
+
diff --git a/runtime/mains/simple/vx_simple_main.c b/runtime/mains/simple/vx_simple_main.c
index 1d53458d..6cb5d966 100644
--- a/runtime/mains/simple/vx_simple_main.c
+++ b/runtime/mains/simple/vx_simple_main.c
@@ -39,12 +39,13 @@ void mat_add_kernel(void * void_arguments)
 
 	bool valid = (wid < arguments->numRows) && (tid < arguments->numColums);
 
-	__if (valid)
-	{
+	// __if (valid)
+	// {
 		unsigned index = (wid * arguments->numColums) + tid;
-		arguments->z[index] = arguments->x[index] + arguments->y[index];
-	}
-	__endif
+		unsigned val = arguments->x[index] + arguments->y[index];
+		arguments->z[index] = val;
+	// }
+	// __endif
 }
 
 int main()
@@ -79,8 +80,8 @@ int main()
 
 
 	// Test wspawn
-	vx_print_str("test_wspawn\n");
-	test_wsapwn();
+	// vx_print_str("test_wspawn\n");
+	// test_wsapwn();
 
 	vx_print_str("Shared Memory test\n");
 	unsigned * ptr = (unsigned *) 0xFFFF0000;
@@ -113,9 +114,9 @@ int main()
 
 	// vx_spawnWarps(numWarps, numThreads, mat_add_kernel, &arguments);
 
-	// for (int i = 0; i < arguments.numRows; i++)
+	// for (int i = 0; i < numWarps; i++)
 	// {
-	// 	for (int j = 0; j < arguments.numColums; j++)
+	// 	for (int j = 0; j < numThreads; j++)
 	// 	{
 	// 		unsigned index = (i * arguments.numColums) + j;
 	// 		vx_print_hex(z[index]);