wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

driver basic test and demo test refactoring

Browse Source
This commit is contained in:
Blaise Tine
2020-06-19 09:12:07 -07:00
parent e2e1b63e14
commit 68d9fc9a75
55 changed files with 1006 additions and 1205 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
hw/rtl/VX_pipeline.v
View File

@@ -3,9 +3,9 @@
module VX_pipeline #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_CORE_IO
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_PIPELINE_IO
`SCOPE_SIGNALS_BE_IO
// Clock
@@ -100,7 +100,7 @@ module VX_pipeline #(
VX_front_end #(
.CORE_ID(CORE_ID)
) front_end (
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_ISTAGE_BIND
.clk (clk),
.reset (reset),
@@ -129,8 +129,8 @@ module VX_pipeline #(
VX_back_end #(
.CORE_ID(CORE_ID)
) back_end (
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_BE_BIND
.clk (clk),
.reset (reset),
@@ -181,7 +181,7 @@ module VX_pipeline #(
`SCOPE_ASSIGN(scope_gpr_stage_delay, gpr_stage_delay);
`ifdef DBG_PRINT_WB
always_ff @(posedge clk) begin
always @(posedge clk) begin
if ((| writeback_if.valid) && (writeback_if.wb != 0)) begin
$display("%t: Writeback: wid=%0d, rd=%0d, data=%0h", $time, writeback_if.warp_num, writeback_if.rd, writeback_if.data);
end