driver basic test and demo test refactoring
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@@ -11,11 +11,12 @@ double sc_time_stamp() {
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Simulator::Simulator() {
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// force random values for unitialized signals
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Verilated::randReset(1);
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Verilated::randReset(2);
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ram_ = nullptr;
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vortex_ = new VVortex_Socket();
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dram_rsp_active_ = false;
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snp_req_active_ = false;
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#ifdef VCD_OUTPUT
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@@ -76,7 +77,7 @@ void Simulator::eval_dram_bus() {
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return;
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}
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// handle DRAM response cycle
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// schedule DRAM responses
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int dequeue_index = -1;
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for (int i = 0; i < dram_rsp_vec_.size(); i++) {
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if (dram_rsp_vec_[i].cycles_left > 0) {
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@@ -88,16 +89,23 @@ void Simulator::eval_dram_bus() {
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}
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}
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// handle DRAM response message
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if ((dequeue_index != -1)
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// send DRAM response
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if (dram_rsp_active_
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&& vortex_->dram_rsp_valid
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&& vortex_->dram_rsp_ready) {
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vortex_->dram_rsp_valid = 1;
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memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE);
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vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;
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free(dram_rsp_vec_[dequeue_index].data);
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dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index);
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} else {
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vortex_->dram_rsp_valid = 0;
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dram_rsp_active_ = false;
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}
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if (!dram_rsp_active_) {
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if (dequeue_index != -1) {
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vortex_->dram_rsp_valid = 1;
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memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE);
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vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;
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free(dram_rsp_vec_[dequeue_index].data);
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dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index);
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dram_rsp_active_ = true;
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} else {
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vortex_->dram_rsp_valid = 0;
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}
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}
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// handle DRAM stalls
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@@ -111,7 +119,7 @@ void Simulator::eval_dram_bus() {
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}
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#endif
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// handle DRAM requests
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// process DRAM requests
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if (!dram_stalled) {
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if (vortex_->dram_req_valid) {
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if (vortex_->dram_req_rw) {
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