diff --git a/rtl/VX_d_e_reg.v b/rtl/VX_d_e_reg.v index d8d168b3..ed342586 100644 --- a/rtl/VX_d_e_reg.v +++ b/rtl/VX_d_e_reg.v @@ -26,7 +26,7 @@ module VX_d_e_reg ( input wire in_jal, input wire[31:0] in_jal_offset, input wire in_freeze, - input wire[`NT_M1:0] in_valid, + input wire in_valid[`NT_M1:0], output wire[11:0] out_csr_address, // done output wire out_is_csr, // done @@ -47,7 +47,7 @@ module VX_d_e_reg ( output wire out_jal, output wire[31:0] out_jal_offset, output wire[31:0] out_PC_next, - output wire[`NT_M1:0] out_valid + output wire out_valid[`NT_M1:0] ); @@ -70,10 +70,10 @@ module VX_d_e_reg ( reg[31:0] curr_PC; reg jal; reg[31:0] jal_offset; - reg[`NT_M1:0] valid; + reg valid[`NT_M1:0]; reg[31:0] reg_data_z[`NT_T2_M1:0]; - reg[`NT_M1:0] valid_z; + reg valid_z[`NT_M1:0]; integer ini_reg; initial begin diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v index 3d2123cc..289b05e1 100644 --- a/rtl/VX_decode.v +++ b/rtl/VX_decode.v @@ -6,12 +6,12 @@ module VX_decode( input wire clk, input wire[31:0] in_instruction, input wire[31:0] in_curr_PC, - input wire[`NT_M1:0] in_valid, + input wire in_valid[`NT_M1:0], // WriteBack inputs input wire[31:0] in_write_data[`NT_M1:0], input wire[4:0] in_rd, input wire[1:0] in_wb, - input wire[`NT_M1:0] in_wb_valid, + input wire in_wb_valid[`NT_M1:0], // FORWARDING INPUTS input wire in_src1_fwd, @@ -40,7 +40,7 @@ module VX_decode( output reg[31:0] out_jal_offset, output reg[19:0] out_upper_immed, output wire[31:0] out_PC_next, - output wire[`NT_M1:0] out_valid + output wire out_valid[`NT_M1:0] ); wire[6:0] curr_opcode; diff --git a/rtl/VX_e_m_reg.v b/rtl/VX_e_m_reg.v index 696224f2..7523239c 100644 --- a/rtl/VX_e_m_reg.v +++ b/rtl/VX_e_m_reg.v @@ -23,7 +23,7 @@ module VX_e_m_reg ( input wire in_jal, input wire[31:0] in_jal_dest, input wire in_freeze, - input wire[`NT_M1:0] in_valid, + input wire in_valid[`NT_M1:0], output wire[11:0] out_csr_address, output wire out_is_csr, @@ -42,7 +42,7 @@ module VX_e_m_reg ( output wire out_jal, output wire[31:0] out_jal_dest, output wire[31:0] out_PC_next, - output wire[`NT_M1:0] out_valid + output wire out_valid[`NT_M1:0] ); @@ -63,7 +63,7 @@ module VX_e_m_reg ( reg[2:0] branch_type; reg jal; reg[31:0] jal_dest; - reg[`NT_M1:0] valid; + reg valid[`NT_M1:0]; // reg[31:0] reg_data_z[`NT_T2_M1:0]; // reg[`NT_M1:0] valid_z; diff --git a/rtl/VX_execute.v b/rtl/VX_execute.v index 7e8dc4e3..45d824a3 100644 --- a/rtl/VX_execute.v +++ b/rtl/VX_execute.v @@ -22,7 +22,7 @@ module VX_execute ( input wire in_jal, input wire[31:0] in_jal_offset, input wire[31:0] in_curr_PC, - input wire[`NT_M1:0] in_valid, + input wire in_valid[`NT_M1:0], output wire[11:0] out_csr_address, output wire out_is_csr, @@ -40,7 +40,7 @@ module VX_execute ( output wire[31:0] out_branch_offset, output wire out_branch_stall, output wire[31:0] out_PC_next, - output wire[`NT_M1:0] out_valid + output wire out_valid[`NT_M1:0] ); diff --git a/rtl/VX_f_d_reg.v b/rtl/VX_f_d_reg.v index 38705aa0..d5887c15 100644 --- a/rtl/VX_f_d_reg.v +++ b/rtl/VX_f_d_reg.v @@ -5,13 +5,14 @@ module VX_f_d_reg ( input wire clk, input wire reset, input wire[31:0] in_instruction, - input wire[`NT_M1:0] in_valid, + input wire in_valid[`NT_M1:0], input wire[31:0] in_curr_PC, input wire in_fwd_stall, input wire in_freeze, + output wire[31:0] out_instruction, output wire[31:0] out_curr_PC, - output wire[`NT_M1:0] out_valid + output wire out_valid[`NT_M1:0] ); // always @(posedge clk) begin @@ -20,7 +21,7 @@ module VX_f_d_reg ( reg[31:0] instruction; reg[31:0] curr_PC; - reg[`NT_M1:0] valid; + reg valid[`NT_M1:0]; integer reset_cur_thread = 0; diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index 44151fee..43a80b44 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -19,7 +19,7 @@ module VX_fetch ( output wire[31:0] out_instruction, output wire out_delay, output wire[31:0] out_curr_PC, - output wire[`NT_M1:0] out_valid + output wire out_valid[`NT_M1:0] ); diff --git a/rtl/VX_m_w_reg.v b/rtl/VX_m_w_reg.v index beca932b..772d4d85 100644 --- a/rtl/VX_m_w_reg.v +++ b/rtl/VX_m_w_reg.v @@ -12,7 +12,7 @@ module VX_m_w_reg ( input wire[4:0] in_rs2, input wire[31:0] in_PC_next, input wire in_freeze, - input wire[`NT_M1:0] in_valid, + input wire in_valid[`NT_M1:0], output wire[31:0] out_alu_result[`NT_M1:0], output wire[31:0] out_mem_result[`NT_M1:0], // NEW @@ -21,7 +21,7 @@ module VX_m_w_reg ( output wire[4:0] out_rs1, output wire[4:0] out_rs2, output wire[31:0] out_PC_next, - output wire[`NT_M1:0] out_valid + output wire out_valid[`NT_M1:0] ); @@ -33,7 +33,7 @@ module VX_m_w_reg ( reg[4:0] rs2; reg[1:0] wb; reg[31:0] PC_next; - reg[`NT_M1:0] valid; + reg valid[`NT_M1:0]; initial begin diff --git a/rtl/VX_memory.v b/rtl/VX_memory.v index 06b07a22..08e55443 100644 --- a/rtl/VX_memory.v +++ b/rtl/VX_memory.v @@ -15,7 +15,7 @@ module VX_memory ( input wire[31:0] in_curr_PC, input wire[31:0] in_branch_offset, input wire[2:0] in_branch_type, - input wire[`NT_M1:0] in_valid, + input wire in_valid[`NT_M1:0], input wire[31:0] in_cache_driver_out_data[`NT_M1:0], output wire[31:0] out_alu_result[`NT_M1:0], @@ -28,11 +28,11 @@ module VX_memory ( output wire[31:0] out_branch_dest, output wire out_delay, output wire[31:0] out_PC_next, - output wire[`NT_M1:0] out_valid, + output wire out_valid[`NT_M1:0], output wire[31:0] out_cache_driver_in_address[`NT_M1:0], output wire[2:0] out_cache_driver_in_mem_read, output wire[2:0] out_cache_driver_in_mem_write, - output wire[`NT_M1:0] out_cache_driver_in_valid, + output wire out_cache_driver_in_valid[`NT_M1:0], output wire[31:0] out_cache_driver_in_data[`NT_M1:0] ); diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 58fd66bb..ccf83282 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -10,7 +10,7 @@ module Vortex( output wire[31:0] out_cache_driver_in_address[`NT_M1:0], output wire[2:0] out_cache_driver_in_mem_read, output wire[2:0] out_cache_driver_in_mem_write, - output wire[`NT_M1:0] out_cache_driver_in_valid, + output wire out_cache_driver_in_valid[`NT_M1:0], output wire[31:0] out_cache_driver_in_data[`NT_M1:0] ); @@ -21,12 +21,12 @@ assign curr_PC = fetch_curr_PC; wire[31:0] fetch_instruction; wire fetch_delay; wire[31:0] fetch_curr_PC; -wire[`NT_M1:0] fetch_valid; +wire fetch_valid[`NT_M1:0]; // From f_d_register wire[31:0] f_d_instruction; wire[31:0] f_d_curr_PC; -wire[`NT_M1:0] f_d_valid; +wire f_d_valid[`NT_M1:0]; // From decode wire decode_branch_stall; @@ -48,7 +48,7 @@ reg decode_jal; reg[31:0] decode_jal_offset; reg[19:0] decode_upper_immed; wire[31:0] decode_PC_next; -wire[`NT_M1:0] decode_valid; +wire decode_valid[`NT_M1:0]; // From d_e_register wire[11:0] d_e_csr_address; @@ -70,7 +70,7 @@ wire[31:0] d_e_curr_PC; wire d_e_jal; wire[31:0] d_e_jal_offset; wire[31:0] d_e_PC_next; -wire[`NT_M1:0] d_e_valid; +wire d_e_valid[`NT_M1:0]; // From execute @@ -90,7 +90,7 @@ wire execute_jal; wire[31:0] execute_jal_dest; wire[31:0] execute_branch_offset; wire[31:0] execute_PC_next; -wire[`NT_M1:0] execute_valid; +wire execute_valid[`NT_M1:0]; // From e_m_register @@ -113,7 +113,7 @@ wire[31:0] e_m_curr_PC; wire[31:0] e_m_branch_offset; wire[2:0] e_m_branch_type; wire[31:0] e_m_PC_next; -wire[`NT_M1:0] e_m_valid; +wire e_m_valid[`NT_M1:0]; // From memory @@ -127,7 +127,7 @@ wire[1:0] memory_wb; wire[4:0] memory_rs1; wire[4:0] memory_rs2; wire[31:0] memory_PC_next; -wire[`NT_M1:0] memory_valid; +wire memory_valid[`NT_M1:0]; // From m_w_register wire[31:0] m_w_alu_result[`NT_M1:0]; @@ -139,7 +139,7 @@ wire[4:0] m_w_rs1; wire[4:0] m_w_rs2; /* verilator lint_on UNUSED */ wire[31:0] m_w_PC_next; -wire[`NT_M1:0] m_w_valid; +wire m_w_valid[`NT_M1:0]; // From writeback wire[31:0] writeback_write_data[`NT_M1:0]; diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex index c756b229..29d20758 100755 Binary files a/rtl/obj_dir/VVortex and b/rtl/obj_dir/VVortex differ diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp index aa0c793d..5d2717a9 100644 --- a/rtl/obj_dir/VVortex.cpp +++ b/rtl/obj_dir/VVortex.cpp @@ -94,15 +94,20 @@ void VVortex::_eval_initial_loop(VVortex__Syms* __restrict vlSymsp) { VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__1\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + // Begin mtask footprint all: + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3,0,0); // Body + __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 0U; // ALWAYS at VX_fetch.v:144 vlTOPp->Vortex__DOT__vx_fetch__DOT__old = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC); // ALWAYS at VX_fetch.v:144 - vlTOPp->Vortex__DOT__vx_fetch__DOT__stall_reg = - ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)); - // ALWAYS at VX_fetch.v:144 vlTOPp->Vortex__DOT__vx_fetch__DOT__BR_reg = ((IData)(vlTOPp->reset) ? 0U : @@ -117,6 +122,23 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp) ((IData)(4U) + vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use)); // ALWAYS at VX_fetch.v:144 + vlTOPp->Vortex__DOT__vx_fetch__DOT__stall_reg = + ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)); + // ALWAYS at VX_f_d_reg.v:29 + if (vlTOPp->reset) { + __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 1U; + } else { + if ((1U & (~ (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)))) { + __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 + = vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid + [1U]; + __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 1U; + __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3 + = vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid + [0U]; + } + } + // ALWAYS at VX_fetch.v:144 vlTOPp->Vortex__DOT__vx_fetch__DOT__state = ((IData)(vlTOPp->reset) ? 0U : @@ -135,6 +157,23 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp) : ((IData)(4U) + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest)); + // ALWAYSPOST at VX_f_d_reg.v:34 + if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] = 0U; + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] = 0U; + } + if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2; + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] + = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3; + } + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [0U]; // ALWAYS at VX_fetch.v:144 vlTOPp->Vortex__DOT__vx_fetch__DOT__prev_debug = 0U; // ALWAYS at VX_fetch.v:82 @@ -158,6 +197,24 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__state)) ? vlTOPp->Vortex__DOT__vx_fetch__DOT__JAL_reg : vlTOPp->Vortex__DOT__vx_fetch__DOT__real_PC))))))); + vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] + = vlTOPp->Vortex__DOT__f_d_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] + = vlTOPp->Vortex__DOT__f_d_valid[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]; + vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [1U]; + vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [0U]; } VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) { @@ -169,6 +226,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0,0,0); VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0,4,0); VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1,0,0); VL_SIG8(__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0,0,0); VL_SIG16(__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0); VL_SIG16(__Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0); @@ -192,6 +255,20 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 = 0U; __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 = 0U; __Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = 0U; + // ALWAYS at VX_m_w_reg.v:60 + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid + [1U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid + [0U]; + // ALWAYS at VX_e_m_reg.v:123 + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid + [1U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid + [0U]; // ALWAYS at VX_e_m_reg.v:123 __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0 = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data @@ -238,6 +315,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) // ALWAYS at VX_csr_handler.v:34 vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle); + // ALWAYS at VX_csr_handler.v:34 + if (vlTOPp->Vortex__DOT__m_w_valid[0U]) { + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret + = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret); + } // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src = (1U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) @@ -254,6 +336,17 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) // ALWAYS at VX_e_m_reg.v:123 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type; + // ALWAYS at VX_d_e_reg.v:133 + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid + [1U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid + [0U]); // ALWAYS at VX_e_m_reg.v:123 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read; @@ -273,16 +366,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest = (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data [0U] + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset); - // ALWAYS at VX_csr_handler.v:34 - if ((1U & (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid))) { - vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret - = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret); - } // ALWAYS at VX_register_file.v:36 if ((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) - & ((IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid) - >> 1U))) { + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U])) { __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data [1U]; @@ -293,7 +381,8 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) // ALWAYS at VX_register_file.v:36 if ((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) - & (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid))) { + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U])) { __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data [0U]; @@ -330,6 +419,16 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data [0U]); + // ALWAYSPOST at VX_m_w_reg.v:69 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[0U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1; + // ALWAYSPOST at VX_e_m_reg.v:142 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1; // ALWAYSPOST at VX_e_m_reg.v:133 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[3U] = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0; @@ -354,6 +453,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1; + // ALWAYSPOST at VX_d_e_reg.v:154 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1; // ALWAYSPOST at VX_register_file.v:39 if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0) { vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0] @@ -378,6 +482,18 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v2; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[0U] = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v3; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[3U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data [3U]; @@ -412,6 +528,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (IData)(vlTOPp->Vortex__DOT__decode_branch_type)); + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [0U]; vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read; // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read @@ -507,8 +629,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd; // ALWAYS at VX_m_w_reg.v:60 vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; // ALWAYS at VX_e_m_reg.v:123 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address; @@ -537,6 +657,14 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data [0U]; + vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [0U]; + vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [0U]; vlTOPp->Vortex__DOT__e_m_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data [3U]; vlTOPp->Vortex__DOT__e_m_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data @@ -557,6 +685,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) [1U]; vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result [0U]; + vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [0U]; vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle) @@ -587,6 +719,14 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) [1U]; vlTOPp->Vortex__DOT__d_e_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] + = vlTOPp->Vortex__DOT__m_w_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] + = vlTOPp->Vortex__DOT__m_w_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] + = vlTOPp->Vortex__DOT__e_m_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] + = vlTOPp->Vortex__DOT__e_m_valid[0U]; vlTOPp->Vortex__DOT__use_rd2[0U] = vlTOPp->Vortex__DOT__e_m_reg_data [1U]; vlTOPp->Vortex__DOT__use_rd2[1U] = vlTOPp->Vortex__DOT__e_m_reg_data @@ -611,6 +751,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = vlTOPp->Vortex__DOT__e_m_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] = vlTOPp->Vortex__DOT__e_m_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[1U] + = vlTOPp->Vortex__DOT__d_e_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] + = vlTOPp->Vortex__DOT__d_e_valid[0U]; vlTOPp->Vortex__DOT__execute_branch_stall = ((0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal)); @@ -626,8 +770,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd; // ALWAYS at VX_e_m_reg.v:123 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb; - // ALWAYS at VX_e_m_reg.v:123 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid; // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) @@ -661,6 +803,18 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = vlTOPp->Vortex__DOT__d_e_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[0U] = vlTOPp->Vortex__DOT__d_e_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] = vlTOPp->Vortex__DOT__use_rd2[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] @@ -737,6 +891,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data [3U]; @@ -761,6 +921,14 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data [2U]; + vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [1U]; + vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [0U]; + vlTOPp->Vortex__DOT__memory_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [1U]; + vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 [1U]; @@ -781,6 +949,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) [1U]; vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result [0U]; + vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [1U]; + vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] @@ -837,11 +1009,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr)) ? 1U : 0U)))); - vlTOPp->out_cache_driver_in_valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; - // ALWAYS at VX_d_e_reg.v:133 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) - ? (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z) - : (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid)); vlTOPp->Vortex__DOT__execute_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data [3U]; vlTOPp->Vortex__DOT__execute_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data @@ -860,6 +1027,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data [1U]); + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__memory_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__memory_valid[0U]; vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data [1U]; vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data @@ -878,6 +1049,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = vlTOPp->Vortex__DOT__memory_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__execute_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__execute_valid[0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[3U] = vlTOPp->Vortex__DOT__execute_reg_data[3U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2U] @@ -1204,6 +1379,12 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->in_cache_driver_out_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] = vlTOPp->in_cache_driver_out_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [0U]; vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data; vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[1U] @@ -1212,6 +1393,12 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data; vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data; + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result [1U]; @@ -1305,6 +1492,14 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data [0U]; + vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [0U]; + vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [0U]; vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result [1U]; vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result @@ -1533,6 +1728,14 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { [1U]; vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] + = vlTOPp->Vortex__DOT__m_w_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] + = vlTOPp->Vortex__DOT__m_w_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] + = vlTOPp->Vortex__DOT__f_d_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] + = vlTOPp->Vortex__DOT__f_d_valid[0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] @@ -1557,6 +1760,20 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->Vortex__DOT__memory_mem_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] = vlTOPp->Vortex__DOT__memory_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]; + vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [1U]; + vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__decode_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__decode_valid[0U]; } VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) { @@ -1633,27 +1850,21 @@ void VVortex::_initial__TOP__6(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[0U] = 0U; - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid = (2U - & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid)); + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[1U] = 0U; - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid = (1U - & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid)); + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] = 0U; // INITIAL at VX_d_e_reg.v:79 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[0U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[0U] = 0U; - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = (2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid)); - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z = - (2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z)); + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[0U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[1U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[1U] = 0U; - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = (1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid)); - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z = - (1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z)); + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[1U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = 0U; @@ -1675,7 +1886,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__7\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // ALWAYS at VX_f_d_reg.v:28 + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__decode_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__decode_valid[0U]; + // ALWAYS at VX_f_d_reg.v:29 if (vlTOPp->reset) { vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC = 0U; } else { @@ -1684,19 +1899,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) = vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC; } } - // ALWAYS at VX_f_d_reg.v:28 - if (vlTOPp->reset) { - vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid - = (2U & (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid)); - vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid - = (1U & (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid)); - } else { - if ((1U & (~ (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)))) { - vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid - = vlTOPp->Vortex__DOT__fetch_valid; - } - } - // ALWAYS at VX_f_d_reg.v:28 + // ALWAYS at VX_f_d_reg.v:29 if (vlTOPp->reset) { vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction = 0U; } else { @@ -2079,13 +2282,21 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)); - vlTOPp->Vortex__DOT__fetch_valid = ((2U & (IData)(vlTOPp->Vortex__DOT__fetch_valid)) - | (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) - & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)))); - vlTOPp->Vortex__DOT__fetch_valid = ((1U & (IData)(vlTOPp->Vortex__DOT__fetch_valid)) - | (2U & (((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) - << 1U) - & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)))); + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] + = (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid))); + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[1U] + = (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) + & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) + >> 1U))); + vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [1U]; + vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__fetch_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__fetch_valid[0U]; } void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { @@ -2148,6 +2359,12 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset << 1U)); + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[3U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data [3U]; @@ -2170,24 +2387,19 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result [0U]; - vlTOPp->out_cache_driver_in_valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; vlTOPp->Vortex__DOT__execute_branch_stall = ((0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal)); + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; - vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd - = ((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) - & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0x14U)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); - vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd - = ((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) - & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[3U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data [3U]; @@ -2200,6 +2412,16 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data [0U]; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd + = ((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd + = ((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data @@ -2214,6 +2436,10 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result [0U])); + vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [0U]; vlTOPp->Vortex__DOT__e_m_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data [3U]; vlTOPp->Vortex__DOT__e_m_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data @@ -2226,6 +2452,18 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { [1U]; vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result [0U]; + vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [0U]; + vlTOPp->Vortex__DOT__d_e_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + [3U]; + vlTOPp->Vortex__DOT__d_e_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + [2U]; + vlTOPp->Vortex__DOT__d_e_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + [1U]; + vlTOPp->Vortex__DOT__d_e_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + [0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) @@ -2239,20 +2477,16 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))); - vlTOPp->Vortex__DOT__d_e_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data - [3U]; - vlTOPp->Vortex__DOT__d_e_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data - [2U]; - vlTOPp->Vortex__DOT__d_e_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data - [1U]; - vlTOPp->Vortex__DOT__d_e_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data - [0U]; vlTOPp->Vortex__DOT__writeback_write_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data [1U]; vlTOPp->Vortex__DOT__writeback_write_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] + = vlTOPp->Vortex__DOT__e_m_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] + = vlTOPp->Vortex__DOT__e_m_valid[0U]; vlTOPp->Vortex__DOT__use_rd2[0U] = vlTOPp->Vortex__DOT__e_m_reg_data [1U]; vlTOPp->Vortex__DOT__use_rd2[1U] = vlTOPp->Vortex__DOT__e_m_reg_data @@ -2261,6 +2495,18 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->Vortex__DOT__e_m_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] = vlTOPp->Vortex__DOT__e_m_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[1U] + = vlTOPp->Vortex__DOT__d_e_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] + = vlTOPp->Vortex__DOT__d_e_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[3U] + = vlTOPp->Vortex__DOT__d_e_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2U] + = vlTOPp->Vortex__DOT__d_e_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[0U] + = vlTOPp->Vortex__DOT__d_e_reg_data[0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) @@ -2285,20 +2531,24 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd))); - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[3U] - = vlTOPp->Vortex__DOT__d_e_reg_data[3U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2U] - = vlTOPp->Vortex__DOT__d_e_reg_data[2U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[1U] - = vlTOPp->Vortex__DOT__d_e_reg_data[1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[0U] - = vlTOPp->Vortex__DOT__d_e_reg_data[0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] = vlTOPp->Vortex__DOT__writeback_write_data [1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] = vlTOPp->Vortex__DOT__writeback_write_data [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] = vlTOPp->Vortex__DOT__use_rd2[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] @@ -2361,30 +2611,12 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result [0U]; - vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)); - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling - = ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) - | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); - vlTOPp->Vortex__DOT__vx_fetch__DOT__stall = ((( - (0x63U - == - (0x7fU - & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) - | ((0x6fU - == - (0x7fU - & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) - | (0x67U - == - (0x7fU - & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))) - | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) - | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); - vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)); + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data [3U]; @@ -2409,6 +2641,38 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data [2U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)); + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling + = ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) + | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); + vlTOPp->Vortex__DOT__vx_fetch__DOT__stall = ((( + (0x63U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + | ((0x6fU + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + | (0x67U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))) + | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) + | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); + vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)); + vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [1U]; + vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [0U]; + vlTOPp->Vortex__DOT__memory_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [1U]; + vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 [1U]; @@ -2433,13 +2697,10 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { [1U]; vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result [0U]; - vlTOPp->Vortex__DOT__fetch_valid = ((2U & (IData)(vlTOPp->Vortex__DOT__fetch_valid)) - | (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) - & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)))); - vlTOPp->Vortex__DOT__fetch_valid = ((1U & (IData)(vlTOPp->Vortex__DOT__fetch_valid)) - | (2U & (((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) - << 1U) - & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)))); + vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [1U]; + vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [0U]; vlTOPp->Vortex__DOT__execute_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data [3U]; vlTOPp->Vortex__DOT__execute_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data @@ -2458,6 +2719,17 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data [1U]); + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] + = (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid))); + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[1U] + = (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) + & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) + >> 1U))); + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__memory_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__memory_valid[0U]; vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data [1U]; vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data @@ -2471,6 +2743,10 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->Vortex__DOT__memory_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__execute_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__execute_valid[0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[3U] = vlTOPp->Vortex__DOT__execute_reg_data[3U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2U] @@ -2489,6 +2765,10 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data [0U]), VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [1U]; + vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [0U]; // ALWAYS at VX_alu.v:47 vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) @@ -2743,6 +3023,10 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data [0U] + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))))); + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__fetch_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__fetch_valid[0U]; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] @@ -3203,20 +3487,33 @@ void VVortex::_ctor_var_reset() { }} out_cache_driver_in_mem_read = VL_RAND_RESET_I(3); out_cache_driver_in_mem_write = VL_RAND_RESET_I(3); - out_cache_driver_in_valid = VL_RAND_RESET_I(2); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32); }} - Vortex__DOT__fetch_valid = VL_RAND_RESET_I(2); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__fetch_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__f_d_valid[__Vi0] = VL_RAND_RESET_I(1); + }} Vortex__DOT__decode_csr_address = VL_RAND_RESET_I(12); { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__decode_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__decode_itype_immed = VL_RAND_RESET_I(32); Vortex__DOT__decode_branch_type = VL_RAND_RESET_I(3); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__decode_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__d_e_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__d_e_valid[__Vi0] = VL_RAND_RESET_I(1); + }} Vortex__DOT__execute_branch_stall = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__execute_alu_result[__Vi0] = VL_RAND_RESET_I(32); @@ -3224,12 +3521,18 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__execute_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__execute_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__e_m_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__e_m_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__e_m_valid[__Vi0] = VL_RAND_RESET_I(1); + }} Vortex__DOT__memory_branch_dir = VL_RAND_RESET_I(1); Vortex__DOT__memory_branch_dest = VL_RAND_RESET_I(32); { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { @@ -3238,12 +3541,18 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__memory_mem_result[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__memory_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__m_w_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__m_w_mem_result[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__m_w_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__writeback_write_data[__Vi0] = VL_RAND_RESET_I(32); }} @@ -3257,6 +3566,18 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__forwarding_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_fetch__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_decode__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellout__vx_decode__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} @@ -3266,30 +3587,54 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_decode__in_write_data[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_decode__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_execute__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellout__vx_execute__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_execute__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_execute__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellinp__vx_execute__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} @@ -3299,12 +3644,18 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__use_rd2[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_memory__out_mem_result[__Vi0] = VL_RAND_RESET_I(32); }} @@ -3314,18 +3665,27 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_memory__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_memory__in_rd2[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_memory__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[__Vi0] = VL_RAND_RESET_I(32); }} @@ -3376,7 +3736,9 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_fetch__DOT__valid = VL_RAND_RESET_I(2); Vortex__DOT__vx_f_d_reg__DOT__instruction = VL_RAND_RESET_I(32); Vortex__DOT__vx_f_d_reg__DOT__curr_PC = VL_RAND_RESET_I(32); - Vortex__DOT__vx_f_d_reg__DOT__valid = VL_RAND_RESET_I(2); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_f_d_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_decode__DOT__rd1_register[__Vi0] = VL_RAND_RESET_I(32); }} @@ -3417,11 +3779,15 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_d_e_reg__DOT__curr_PC = VL_RAND_RESET_I(32); Vortex__DOT__vx_d_e_reg__DOT__jal = VL_RAND_RESET_I(1); Vortex__DOT__vx_d_e_reg__DOT__jal_offset = VL_RAND_RESET_I(32); - Vortex__DOT__vx_d_e_reg__DOT__valid = VL_RAND_RESET_I(2); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_d_e_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[__Vi0] = VL_RAND_RESET_I(32); }} - Vortex__DOT__vx_d_e_reg__DOT__valid_z = VL_RAND_RESET_I(2); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_d_e_reg__DOT__valid_z[__Vi0] = VL_RAND_RESET_I(1); + }} Vortex__DOT__vx_d_e_reg__DOT__stalling = VL_RAND_RESET_I(1); Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32); { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { @@ -3454,7 +3820,9 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_e_m_reg__DOT__branch_type = VL_RAND_RESET_I(3); Vortex__DOT__vx_e_m_reg__DOT__jal = VL_RAND_RESET_I(1); Vortex__DOT__vx_e_m_reg__DOT__jal_dest = VL_RAND_RESET_I(32); - Vortex__DOT__vx_e_m_reg__DOT__valid = VL_RAND_RESET_I(2); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_e_m_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_m_w_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32); }} @@ -3464,7 +3832,9 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_m_w_reg__DOT__rd = VL_RAND_RESET_I(5); Vortex__DOT__vx_m_w_reg__DOT__wb = VL_RAND_RESET_I(2); Vortex__DOT__vx_m_w_reg__DOT__PC_next = VL_RAND_RESET_I(32); - Vortex__DOT__vx_m_w_reg__DOT__valid = VL_RAND_RESET_I(2); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_m_w_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_writeback__DOT__out_pc_data[__Vi0] = VL_RAND_RESET_I(32); }} diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h index fe11b41f..007ba2a8 100644 --- a/rtl/obj_dir/VVortex.h +++ b/rtl/obj_dir/VVortex.h @@ -25,11 +25,11 @@ VL_MODULE(VVortex) { VL_IN8(reset,0,0); VL_OUT8(out_cache_driver_in_mem_read,2,0); VL_OUT8(out_cache_driver_in_mem_write,2,0); - VL_OUT8(out_cache_driver_in_valid,1,0); VL_IN(fe_instruction,31,0); VL_OUT(curr_PC,31,0); VL_IN(in_cache_driver_out_data[2],31,0); VL_OUT(out_cache_driver_in_address[2],31,0); + VL_OUT8(out_cache_driver_in_valid[2],0,0); VL_OUT(out_cache_driver_in_data[2],31,0); // LOCAL SIGNALS @@ -37,7 +37,6 @@ VL_MODULE(VVortex) { // Anonymous structures to workaround compiler member-count bugs struct { // Begin mtask footprint all: - VL_SIG8(Vortex__DOT__fetch_valid,1,0); VL_SIG8(Vortex__DOT__decode_branch_type,2,0); VL_SIG8(Vortex__DOT__execute_branch_stall,0,0); VL_SIG8(Vortex__DOT__memory_branch_dir,0,0); @@ -50,7 +49,6 @@ VL_MODULE(VVortex) { VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,1,0); - VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid,1,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0); @@ -64,8 +62,6 @@ VL_MODULE(VVortex) { VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__branch_type,2,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__is_csr,0,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__jal,0,0); - VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid,1,0); - VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z,1,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__stalling,0,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__rd,4,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__wb,1,0); @@ -74,10 +70,8 @@ VL_MODULE(VVortex) { VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__is_csr,0,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__branch_type,2,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__jal,0,0); - VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid,1,0); VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__rd,4,0); VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__wb,1,0); - VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid,1,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0); @@ -101,14 +95,14 @@ VL_MODULE(VVortex) { VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0); VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0); - }; - struct { VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0); VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0); + }; + struct { VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0); @@ -120,30 +114,43 @@ VL_MODULE(VVortex) { VL_SIG64(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0); + VL_SIG8(Vortex__DOT__fetch_valid[2],0,0); + VL_SIG8(Vortex__DOT__f_d_valid[2],0,0); VL_SIG(Vortex__DOT__decode_reg_data[4],31,0); + VL_SIG8(Vortex__DOT__decode_valid[2],0,0); VL_SIG(Vortex__DOT__d_e_reg_data[4],31,0); + VL_SIG8(Vortex__DOT__d_e_valid[2],0,0); VL_SIG(Vortex__DOT__execute_alu_result[2],31,0); VL_SIG(Vortex__DOT__execute_reg_data[4],31,0); + VL_SIG8(Vortex__DOT__execute_valid[2],0,0); VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0); VL_SIG(Vortex__DOT__e_m_reg_data[4],31,0); + VL_SIG8(Vortex__DOT__e_m_valid[2],0,0); VL_SIG(Vortex__DOT__memory_alu_result[2],31,0); VL_SIG(Vortex__DOT__memory_mem_result[2],31,0); + VL_SIG8(Vortex__DOT__memory_valid[2],0,0); VL_SIG(Vortex__DOT__m_w_alu_result[2],31,0); VL_SIG(Vortex__DOT__m_w_mem_result[2],31,0); + VL_SIG8(Vortex__DOT__m_w_valid[2],0,0); VL_SIG(Vortex__DOT__writeback_write_data[2],31,0); VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0); VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0); VL_SIG(Vortex__DOT__use_rd2[2],31,0); + VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0); VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[2],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[2],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[32],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[32],31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[2],0,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[2],0,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0); + VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[2],0,0); VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0); VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0); VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0); @@ -163,28 +170,45 @@ VL_MODULE(VVortex) { VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data,31,0); VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0); VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[4],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[4],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[4],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[4],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[4],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[4],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[4],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0); VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0); diff --git a/rtl/obj_dir/VVortex__ALL.a b/rtl/obj_dir/VVortex__ALL.a index e0884b0c..06200527 100644 Binary files a/rtl/obj_dir/VVortex__ALL.a and b/rtl/obj_dir/VVortex__ALL.a differ diff --git a/rtl/obj_dir/VVortex__ALLcls.o b/rtl/obj_dir/VVortex__ALLcls.o index 9f22fd7a..2b7dbaf8 100644 Binary files a/rtl/obj_dir/VVortex__ALLcls.o and b/rtl/obj_dir/VVortex__ALLcls.o differ diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat index 842d4aec..a8cb3a3c 100644 --- a/rtl/obj_dir/VVortex__verFiles.dat +++ b/rtl/obj_dir/VVortex__verFiles.dat @@ -3,24 +3,24 @@ C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_f S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" S 2782 12889318286 1553669148 0 1553669148 0 "VX_alu.v" S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v" -S 4759 12889318287 1553668670 0 1553668670 0 "VX_d_e_reg.v" -S 10698 12889318288 1553672118 0 1553672118 0 "VX_decode.v" +S 4780 12889318287 1553672988 0 1553672988 0 "VX_d_e_reg.v" +S 10713 12889318288 1553673019 0 1553673019 0 "VX_decode.v" S 1551 12889079483 1553661565 0 1553661565 0 "VX_define.v" -S 3922 12889318289 1553672147 0 1553672147 0 "VX_e_m_reg.v" -S 3350 12889318290 1553669263 0 1553669263 0 "VX_execute.v" -S 1351 12889050060 1553664431 0 1553664431 0 "VX_f_d_reg.v" -S 3931 12889047675 1553672617 0 1553672617 0 "VX_fetch.v" +S 3941 12889318289 1553673060 0 1553673060 0 "VX_e_m_reg.v" +S 3370 12889318290 1553673095 0 1553673095 0 "VX_execute.v" +S 1382 12889050060 1553673124 0 1553673124 0 "VX_f_d_reg.v" +S 3941 12889047675 1553673132 0 1553673132 0 "VX_fetch.v" S 5632 12889086478 1553672336 0 1553672336 0 "VX_forwarding.v" -S 1658 12889085814 1553671325 0 1553671325 0 "VX_m_w_reg.v" -S 2771 12889084513 1553670938 0 1553670938 0 "VX_memory.v" +S 1677 12889085814 1553673165 0 1553673165 0 "VX_m_w_reg.v" +S 2790 12889084513 1553673201 0 1553673201 0 "VX_memory.v" S 1000 12889070228 1553659195 0 1553659195 0 "VX_register_file.v" S 1010 12889086287 1553671609 0 1553671609 0 "VX_writeback.v" -S 15561 12889318291 1553672234 0 1553672234 0 "Vortex.v" -T 173538 12889376662 1553672623 0 1553672623 0 "obj_dir/VVortex.cpp" -T 13367 12889376661 1553672623 0 1553672623 0 "obj_dir/VVortex.h" -T 1800 12889376664 1553672623 0 1553672623 0 "obj_dir/VVortex.mk" -T 530 12889376660 1553672623 0 1553672623 0 "obj_dir/VVortex__Syms.cpp" -T 711 12889376659 1553672623 0 1553672623 0 "obj_dir/VVortex__Syms.h" -T 464 12889376665 1553672623 0 1553672623 0 "obj_dir/VVortex__ver.d" -T 0 0 1553672623 0 1553672623 0 "obj_dir/VVortex__verFiles.dat" -T 1159 12889376663 1553672623 0 1553672623 0 "obj_dir/VVortex_classes.mk" +S 15611 12889318291 1553672889 0 1553672889 0 "Vortex.v" +T 190167 12889376837 1553673213 0 1553673213 0 "obj_dir/VVortex.cpp" +T 14844 12889376836 1553673213 0 1553673213 0 "obj_dir/VVortex.h" +T 1800 12889376839 1553673213 0 1553673213 0 "obj_dir/VVortex.mk" +T 530 12889376835 1553673213 0 1553673213 0 "obj_dir/VVortex__Syms.cpp" +T 711 12889376834 1553673213 0 1553673213 0 "obj_dir/VVortex__Syms.h" +T 464 12889376840 1553673213 0 1553673213 0 "obj_dir/VVortex__ver.d" +T 0 0 1553673213 0 1553673213 0 "obj_dir/VVortex__verFiles.dat" +T 1159 12889376838 1553673213 0 1553673213 0 "obj_dir/VVortex_classes.mk" diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o index 7e8cd0cb..090e350b 100644 Binary files a/rtl/obj_dir/test_bench.o and b/rtl/obj_dir/test_bench.o differ diff --git a/rtl/test_bench.h b/rtl/test_bench.h index f88dd7e3..48f133bc 100644 --- a/rtl/test_bench.h +++ b/rtl/test_bench.h @@ -172,80 +172,84 @@ bool Vortex::dbus_driver() // std::cout << "DBUS DRIVER\n" << std::endl; ////////////////////// DBUS ////////////////////// - - if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid) + for (unsigned curr_th = 0; curr_th < NT; curr_th++) { - for (unsigned curr_th = 0; curr_th < NT; curr_th++) + if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid[curr_th]) { - data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th]; - addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th]; + data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th]; + addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th]; - if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE) - { - data_write = ( data_write) & 0xFF; - ram.writeByte( addr, &data_write); + if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE) + { + data_write = ( data_write) & 0xFF; + ram.writeByte( addr, &data_write); + + } else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE) + { + data_write = ( data_write) & 0xFFFF; + ram.writeHalf( addr, &data_write); + } else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE) + { + data_write = data_write; + ram.writeWord( addr, &data_write); + } - } else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE) - { - data_write = ( data_write) & 0xFFFF; - ram.writeHalf( addr, &data_write); - } else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE) - { - data_write = data_write; - ram.writeWord( addr, &data_write); - } } } - if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid) + + for (unsigned curr_th = 0; curr_th < NT; curr_th++) { - for (unsigned curr_th = 0; curr_th < NT; curr_th++) + if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th]) { - addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th]; - ram.getWord(addr, &data_read); - if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ) - { - vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF); + addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th]; + ram.getWord(addr, &data_read); - } else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ) - { + if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ) + { - vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF); + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF); - } else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ) - { - // printf("Reading mem - Addr: %h = %h\n", addr, data_read); - // std::cout << "Reading mem - Addr: " << std::hex << addr << " = " << data_read << "\n"; - std::cout << std::dec; - vortex->in_cache_driver_out_data[curr_th] = data_read; + } else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ) + { - } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ) - { + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF); - vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF); + } else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ) + { + // printf("Reading mem - Addr: %h = %h\n", addr, data_read); + // std::cout << "Reading mem - Addr: " << std::hex << addr << " = " << data_read << "\n"; + std::cout << std::dec; + vortex->in_cache_driver_out_data[curr_th] = data_read; - } else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ) - { + } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ) + { - vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF); + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF); - } - else - { - vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe; - } + } else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ) + { + + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF); + + } + else + { + vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe; + } } - } - else - { - for (unsigned curr_th = 0; curr_th < NT; curr_th++) + else + { vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe; + } + } + return false; }