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added support for write-through cache, removed cache snooping support

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This commit is contained in:
Blaise Tine
2020-12-23 23:51:02 -08:00
parent d956e268b9
commit 703a861fe9
55 changed files with 1077 additions and 2178 deletions
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217
hw/rtl/VX_cluster.v
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@@ -24,30 +24,18 @@ module VX_cluster #(
input wire [`L2DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Snoop request
input wire snp_req_valid,
input wire [`L2DRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire snp_req_inv,
input wire [`L2SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// Snoop response
output wire snp_rsp_valid,
output wire [`L2SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// CSR Request
input wire csr_io_req_valid,
input wire [`NC_BITS-1:0] csr_io_req_coreid,
input wire [11:0] csr_io_req_addr,
input wire csr_io_req_rw,
input wire [31:0] csr_io_req_data,
output wire csr_io_req_ready,
input wire csr_req_valid,
input wire [`NC_BITS-1:0] csr_req_coreid,
input wire [11:0] csr_req_addr,
input wire csr_req_rw,
input wire [31:0] csr_req_data,
output wire csr_req_ready,
// CSR Response
output wire csr_io_rsp_valid,
output wire [31:0] csr_io_rsp_data,
input wire csr_io_rsp_ready,
output wire csr_rsp_valid,
output wire [31:0] csr_rsp_data,
input wire csr_rsp_ready,
// Status
output wire busy,
@@ -66,25 +54,15 @@ module VX_cluster #(
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] per_core_dram_rsp_tag;
wire [`NUM_CORES-1:0] per_core_dram_rsp_ready;
wire [`NUM_CORES-1:0] per_core_snp_req_valid;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_snp_req_addr;
wire [`NUM_CORES-1:0] per_core_snp_req_inv;
wire [`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] per_core_snp_req_tag;
wire [`NUM_CORES-1:0] per_core_snp_req_ready;
wire [`NUM_CORES-1:0] per_core_snp_rsp_valid;
wire [`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] per_core_snp_rsp_tag;
wire [`NUM_CORES-1:0] per_core_snp_rsp_ready;
wire [`NUM_CORES-1:0] per_core_csr_req_valid;
wire [`NUM_CORES-1:0][11:0] per_core_csr_req_addr;
wire [`NUM_CORES-1:0] per_core_csr_req_rw;
wire [`NUM_CORES-1:0][31:0] per_core_csr_req_data;
wire [`NUM_CORES-1:0] per_core_csr_req_ready;
wire [`NUM_CORES-1:0] per_core_csr_io_req_valid;
wire [`NUM_CORES-1:0][11:0] per_core_csr_io_req_addr;
wire [`NUM_CORES-1:0] per_core_csr_io_req_rw;
wire [`NUM_CORES-1:0][31:0] per_core_csr_io_req_data;
wire [`NUM_CORES-1:0] per_core_csr_io_req_ready;
wire [`NUM_CORES-1:0] per_core_csr_io_rsp_valid;
wire [`NUM_CORES-1:0][31:0] per_core_csr_io_rsp_data;
wire [`NUM_CORES-1:0] per_core_csr_io_rsp_ready;
wire [`NUM_CORES-1:0] per_core_csr_rsp_valid;
wire [`NUM_CORES-1:0][31:0] per_core_csr_rsp_data;
wire [`NUM_CORES-1:0] per_core_csr_rsp_ready;
wire [`NUM_CORES-1:0] per_core_busy;
wire [`NUM_CORES-1:0] per_core_ebreak;
@@ -95,129 +73,77 @@ module VX_cluster #(
) core (
`SCOPE_BIND_VX_cluster_core(i)
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
.dram_req_valid (per_core_dram_req_valid [i]),
.dram_req_rw (per_core_dram_req_rw [i]),
.dram_req_byteen (per_core_dram_req_byteen [i]),
.dram_req_addr (per_core_dram_req_addr [i]),
.dram_req_data (per_core_dram_req_data [i]),
.dram_req_tag (per_core_dram_req_tag [i]),
.dram_req_ready (per_core_dram_req_ready [i]),
.dram_req_valid (per_core_dram_req_valid[i]),
.dram_req_rw (per_core_dram_req_rw [i]),
.dram_req_byteen(per_core_dram_req_byteen[i]),
.dram_req_addr (per_core_dram_req_addr [i]),
.dram_req_data (per_core_dram_req_data [i]),
.dram_req_tag (per_core_dram_req_tag [i]),
.dram_req_ready (per_core_dram_req_ready[i]),
.dram_rsp_valid (per_core_dram_rsp_valid [i]),
.dram_rsp_data (per_core_dram_rsp_data [i]),
.dram_rsp_tag (per_core_dram_rsp_tag [i]),
.dram_rsp_ready (per_core_dram_rsp_ready [i]),
.dram_rsp_valid (per_core_dram_rsp_valid[i]),
.dram_rsp_data (per_core_dram_rsp_data [i]),
.dram_rsp_tag (per_core_dram_rsp_tag [i]),
.dram_rsp_ready (per_core_dram_rsp_ready[i]),
.snp_req_valid (per_core_snp_req_valid [i]),
.snp_req_addr (per_core_snp_req_addr [i]),
.snp_req_inv (per_core_snp_req_inv [i]),
.snp_req_tag (per_core_snp_req_tag [i]),
.snp_req_ready (per_core_snp_req_ready [i]),
.csr_req_valid (per_core_csr_req_valid [i]),
.csr_req_rw (per_core_csr_req_rw [i]),
.csr_req_addr (per_core_csr_req_addr [i]),
.csr_req_data (per_core_csr_req_data [i]),
.csr_req_ready (per_core_csr_req_ready [i]),
.snp_rsp_valid (per_core_snp_rsp_valid [i]),
.snp_rsp_tag (per_core_snp_rsp_tag [i]),
.snp_rsp_ready (per_core_snp_rsp_ready [i]),
.csr_rsp_valid (per_core_csr_rsp_valid [i]),
.csr_rsp_data (per_core_csr_rsp_data [i]),
.csr_rsp_ready (per_core_csr_rsp_ready [i]),
.csr_io_req_valid (per_core_csr_io_req_valid[i]),
.csr_io_req_rw (per_core_csr_io_req_rw [i]),
.csr_io_req_addr (per_core_csr_io_req_addr [i]),
.csr_io_req_data (per_core_csr_io_req_data [i]),
.csr_io_req_ready (per_core_csr_io_req_ready[i]),
.csr_io_rsp_valid (per_core_csr_io_rsp_valid[i]),
.csr_io_rsp_data (per_core_csr_io_rsp_data [i]),
.csr_io_rsp_ready (per_core_csr_io_rsp_ready[i]),
.busy (per_core_busy [i]),
.ebreak (per_core_ebreak [i])
.busy (per_core_busy [i]),
.ebreak (per_core_ebreak [i])
);
end
VX_csr_io_arb #(
VX_csr_arb #(
.NUM_REQS (`NUM_CORES),
.DATA_WIDTH (32),
.ADDR_WIDTH (12),
.BUFFERED_REQ (1),
.BUFFERED_RSP (`NUM_CORES >= 4)
) csr_io_arb (
) csr_arb (
.clk (clk),
.reset (reset),
.request_id (csr_io_req_coreid),
.request_id (csr_req_coreid),
// input requests
.req_valid_in (csr_io_req_valid),
.req_addr_in (csr_io_req_addr),
.req_rw_in (csr_io_req_rw),
.req_data_in (csr_io_req_data),
.req_ready_in (csr_io_req_ready),
.req_valid_in (csr_req_valid),
.req_addr_in (csr_req_addr),
.req_rw_in (csr_req_rw),
.req_data_in (csr_req_data),
.req_ready_in (csr_req_ready),
// output request
.req_valid_out (per_core_csr_io_req_valid),
.req_addr_out (per_core_csr_io_req_addr),
.req_rw_out (per_core_csr_io_req_rw),
.req_data_out (per_core_csr_io_req_data),
.req_ready_out (per_core_csr_io_req_ready),
.req_valid_out (per_core_csr_req_valid),
.req_addr_out (per_core_csr_req_addr),
.req_rw_out (per_core_csr_req_rw),
.req_data_out (per_core_csr_req_data),
.req_ready_out (per_core_csr_req_ready),
// input responses
.rsp_valid_in (per_core_csr_io_rsp_valid),
.rsp_data_in (per_core_csr_io_rsp_data),
.rsp_ready_in (per_core_csr_io_rsp_ready),
.rsp_valid_in (per_core_csr_rsp_valid),
.rsp_data_in (per_core_csr_rsp_data),
.rsp_ready_in (per_core_csr_rsp_ready),
// output response
.rsp_valid_out (csr_io_rsp_valid),
.rsp_data_out (csr_io_rsp_data),
.rsp_ready_out (csr_io_rsp_ready)
.rsp_valid_out (csr_rsp_valid),
.rsp_data_out (csr_rsp_data),
.rsp_ready_out (csr_rsp_ready)
);
assign busy = (| per_core_busy);
assign ebreak = (| per_core_ebreak);
wire snp_fwd_rsp_valid;
wire [`L2DRAM_ADDR_WIDTH-1:0] snp_fwd_rsp_addr;
wire snp_fwd_rsp_inv;
wire [`L2SNP_TAG_WIDTH-1:0] snp_fwd_rsp_tag;
wire snp_fwd_rsp_ready;
VX_snp_forwarder #(
.CACHE_ID (`L2CACHE_ID),
.NUM_REQS (`NUM_CORES),
.SRC_ADDR_WIDTH (`L2DRAM_ADDR_WIDTH),
.DST_ADDR_WIDTH (`DDRAM_ADDR_WIDTH),
.SREQ_SIZE (`L2SREQ_SIZE),
.TAG_IN_WIDTH (`L2SNP_TAG_WIDTH),
.TAG_OUT_WIDTH (`DSNP_TAG_WIDTH),
.BUFFERED (`NUM_CORES >= 4)
) snp_forwarder (
.clk (clk),
.reset (reset),
.snp_req_valid (snp_req_valid),
.snp_req_addr (snp_req_addr),
.snp_req_inv (snp_req_inv),
.snp_req_tag (snp_req_tag),
.snp_req_ready (snp_req_ready),
.snp_rsp_valid (snp_fwd_rsp_valid),
.snp_rsp_addr (snp_fwd_rsp_addr),
.snp_rsp_inv (snp_fwd_rsp_inv),
.snp_rsp_tag (snp_fwd_rsp_tag),
.snp_rsp_ready (snp_fwd_rsp_ready),
.snp_fwdout_valid (per_core_snp_req_valid),
.snp_fwdout_addr (per_core_snp_req_addr),
.snp_fwdout_inv (per_core_snp_req_inv),
.snp_fwdout_tag (per_core_snp_req_tag),
.snp_fwdout_ready (per_core_snp_req_ready),
.snp_fwdin_valid (per_core_snp_rsp_valid),
.snp_fwdin_tag (per_core_snp_rsp_tag),
.snp_fwdin_ready (per_core_snp_rsp_ready)
);
if (`L2_ENABLE) begin
`ifdef PERF_ENABLE
VX_perf_cache_if perf_l2cache_if();
@@ -233,17 +159,13 @@ module VX_cluster #(
.CREQ_SIZE (`L2CREQ_SIZE),
.MSHR_SIZE (`L2MSHR_SIZE),
.DRSQ_SIZE (`L2DRSQ_SIZE),
.SREQ_SIZE (`L2SREQ_SIZE),
.CRSQ_SIZE (`L2CRSQ_SIZE),
.DREQ_SIZE (`L2DREQ_SIZE),
.SRSQ_SIZE (`L2SRSQ_SIZE),
.DRAM_ENABLE (1),
.FLUSH_ENABLE (1),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`XDRAM_TAG_WIDTH),
.CORE_TAG_ID_BITS (0),
.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH),
.SNP_TAG_WIDTH (`L2SNP_TAG_WIDTH)
.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH)
) l2cache (
`SCOPE_BIND_VX_cluster_l2cache
@@ -284,18 +206,6 @@ module VX_cluster #(
.dram_rsp_data (dram_rsp_data),
.dram_rsp_ready (dram_rsp_ready),
// Snoop request
.snp_req_valid (snp_fwd_rsp_valid),
.snp_req_addr (snp_fwd_rsp_addr),
.snp_req_inv (snp_fwd_rsp_inv),
.snp_req_tag (snp_fwd_rsp_tag),
.snp_req_ready (snp_fwd_rsp_ready),
// Snoop response
.snp_rsp_valid (snp_rsp_valid),
.snp_rsp_tag (snp_rsp_tag),
.snp_rsp_ready (snp_rsp_ready),
// Miss status
`UNUSED_PIN (miss_vec)
);
@@ -344,13 +254,6 @@ module VX_cluster #(
.rsp_ready_in (dram_rsp_ready)
);
`UNUSED_VAR (snp_fwd_rsp_addr)
`UNUSED_VAR (snp_fwd_rsp_inv)
assign snp_rsp_valid = snp_fwd_rsp_valid;
assign snp_rsp_tag = snp_fwd_rsp_tag;
assign snp_fwd_rsp_ready = snp_rsp_ready;
end
endmodule