Merge branch 'master' of https://github.gatech.edu/casl/Vortex
This commit is contained in:
@@ -75,6 +75,10 @@ endif
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VL_FLAGS += -DNOPAE
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CFLAGS += -DNOPAE
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# ALU backend
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VL_FLAGS += -DIMUL_DPI
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VL_FLAGS += -DIDIV_DPI
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# FPU backend
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FPU_CORE ?= FPU_DPI
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VL_FLAGS += -D$(FPU_CORE)
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@@ -154,12 +154,14 @@ void opae_sim::write_mmio64(uint32_t mmio_num, uint64_t offset, uint64_t value)
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void opae_sim::reset() {
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cci_reads_.clear();
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cci_writes_.clear();
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vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid = 0;
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vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid = 0;
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vortex_afu_->vcp2af_sRxPort_c0_rspValid = 0;
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vortex_afu_->vcp2af_sRxPort_c1_rspValid = 0;
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vortex_afu_->vcp2af_sRxPort_c0_TxAlmFull = 0;
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vortex_afu_->vcp2af_sRxPort_c1_TxAlmFull = 0;
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for (int b = 0; b < PLATFORM_PARAM_LOCAL_MEMORY_BANKS; ++b) {
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for (int b = 0; b < MEMORY_BANKS; ++b) {
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mem_reads_[b].clear();
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vortex_afu_->avs_readdatavalid[b] = 0;
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vortex_afu_->avs_waitrequest[b] = 0;
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@@ -284,7 +286,7 @@ void opae_sim::sTxPort_bus() {
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}
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void opae_sim::avs_bus() {
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for (int b = 0; b < PLATFORM_PARAM_LOCAL_MEMORY_BANKS; ++b) {
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for (int b = 0; b < MEMORY_BANKS; ++b) {
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// update memory responses schedule
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for (auto& rsp : mem_reads_[b]) {
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if (rsp.cycles_left > 0)
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@@ -18,6 +18,14 @@
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#include <list>
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#include <unordered_map>
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#ifndef MEMORY_BANKS
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#ifdef PLATFORM_PARAM_LOCAL_MEMORY_BANKS
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#define MEMORY_BANKS PLATFORM_PARAM_LOCAL_MEMORY_BANKS
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#else
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#define MEMORY_BANKS 2
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#endif
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#endif
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#undef MEM_BLOCK_SIZE
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#define MEM_BLOCK_SIZE (PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH / 8)
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@@ -81,7 +89,7 @@ private:
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std::unordered_map<int64_t, host_buffer_t> host_buffers_;
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int64_t host_buffer_ids_;
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std::list<mem_rd_req_t> mem_reads_ [PLATFORM_PARAM_LOCAL_MEMORY_BANKS];
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std::list<mem_rd_req_t> mem_reads_ [MEMORY_BANKS];
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std::list<cci_rd_req_t> cci_reads_;
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@@ -64,6 +64,10 @@ ifdef PERF
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CFLAGS += -DPERF_ENABLE
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endif
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# ALU backend
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VL_FLAGS += -DIMUL_DPI
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VL_FLAGS += -DIDIV_DPI
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# FPU backend
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FPU_CORE ?= FPU_DPI
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VL_FLAGS += -D$(FPU_CORE)
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