From 719b8048abb81c1a709e101995fdec4536a62582 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 26 Sep 2023 13:36:22 -0700 Subject: [PATCH] [debug] Print warp id for memtraces --- sim/simx/execute.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sim/simx/execute.cpp b/sim/simx/execute.cpp index a2c0ae49..56f48982 100644 --- a/sim/simx/execute.cpp +++ b/sim/simx/execute.cpp @@ -693,6 +693,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) { trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes}); DP(2, "LOAD MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles() << ", CORE=" << core_->id() + << ", WARP=" << id_ << ", THREAD=" << t << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec @@ -738,6 +739,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) { *result_ptr = mem_data; DP(2, "LOAD MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles() << ", CORE=" << core_->id() + << ", WARP=" << id_ << ", VLEN=" << vl_ << ", VID=" << i << ", ADDRESS=0x" << std::hex << mem_addr @@ -775,6 +777,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) { trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes}); DP(2, "STORE MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles() << ", CORE=" << core_->id() + << ", WARP=" << id_ << ", THREAD=" << t << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec @@ -800,6 +803,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) { core_->dcache_write(&mem_data, mem_addr, 4); DP(2, "STORE MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles() << ", CORE=" << core_->id() + << ", WARP=" << id_ << ", VLEN=" << vl_ << ", VID=" << i << ", ADDRESS=0x" << std::hex << mem_addr