fixed DRAM response backpressure inside Cache

2020-11-10 05:24:57 -08:00
parent ed69be4027
commit 725322807e
19 changed files with 69 additions and 36 deletions
--- a/hw/rtl/VX_writeback.v
+++ b/hw/rtl/VX_writeback.v
@@ -73,7 +73,7 @@ module VX_writeback #(
                                    0;

    always @(*) assert(writeback_if.ready);
-    wire stall = 0/*~writeback_if.ready && writeback_if.valid*/;
+    wire stall =~writeback_if.ready && writeback_if.valid;
    
    VX_generic_register #(
        .N(1 + `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32))