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fpu implementation (part1)

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Blaise Tine
2020-07-23 03:18:09 -07:00
parent 6836f397f8
commit 75e3c31b56
31 changed files with 662 additions and 159 deletions
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8
hw/rtl/VX_mul_unit.v
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@@ -36,7 +36,7 @@ module VX_mul_unit #(
.WIDTHB(33),
.WIDTHP(64),
.SIGNED(1),
.PIPELINE(`MUL_LATENCY)
.PIPELINE(`LATENCY_IMUL)
) multiplier (
.clk(clk),
.reset(reset),
@@ -52,7 +52,7 @@ module VX_mul_unit #(
.WIDTHR(32),
.NSIGNED(1),
.DSIGNED(1),
.PIPELINE(`DIV_LATENCY)
.PIPELINE(`LATENCY_IDIV)
) sdiv (
.clk(clk),
.reset(reset),
@@ -81,7 +81,7 @@ module VX_mul_unit #(
reg result_avail;
reg [4:0] pending_ctr;
wire [4:0] instr_delay = `IS_DIV_OP(alu_op) ? `DIV_LATENCY : `MUL_LATENCY;
wire [4:0] instr_delay = `IS_DIV_OP(alu_op) ? `LATENCY_IDIV : `LATENCY_IMUL;
always @(posedge clk) begin
if (reset) begin
@@ -112,7 +112,7 @@ module VX_mul_unit #(
wire flush = mul_commit_if.ready && pipeline_stall;
VX_generic_register #(
.N(`NUM_THREADS + `NW_BITS + 32 + `NR_BITS + `WB_BITS + (`NUM_THREADS * 32))
.N(`NUM_THREADS + `NW_BITS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32))
) mul_reg (
.clk (clk),
.reset (reset),