diff --git a/kernel/Makefile b/kernel/Makefile index a4e16460..04fa14d6 100644 --- a/kernel/Makefile +++ b/kernel/Makefile @@ -1,13 +1,13 @@ -# COMP = /opt/riscv/bin/riscv32-unknown-elf-gcc -COMP = /opt/riscv/bin/riscv32-unknown-linux-gnu-gcc +COMP = /opt/riscv/bin/riscv32-unknown-elf-gcc +# COMP = /opt/riscv/bin/riscv32-unknown-linux-gnu-gcc CC_FLAGS = -march=rv32im -mabi=ilp32 -O0 -Wl,-Bstatic,-T,linker.ld -ffreestanding -nostdlib -# DMP = /opt/riscv/bin/riscv32-unknown-elf-objdump -# CPY = /opt/riscv/bin/riscv32-unknown-elf-objcopy +DMP = /opt/riscv/bin/riscv32-unknown-elf-objdump +CPY = /opt/riscv/bin/riscv32-unknown-elf-objcopy -DMP = /opt/riscv/bin/riscv32-unknown-linux-gnu-objdump -CPY = /opt/riscv/bin/riscv32-unknown-linux-gnu-objcopy +# DMP = /opt/riscv/bin/riscv32-unknown-linux-gnu-objdump +# CPY = /opt/riscv/bin/riscv32-unknown-linux-gnu-objcopy VX_LIB = ./vx_os/vx_back/vx_back.s ./vx_os/vx_back/vx_back.c ./vx_os/vx_util/queue.s VX_IO = ./vx_os/vx_io/vx_io.s ./vx_os/vx_io/vx_io.c diff --git a/kernel/vortex_test.dump b/kernel/vortex_test.dump index c2848f9e..0befe0cf 100644 --- a/kernel/vortex_test.dump +++ b/kernel/vortex_test.dump @@ -7,7 +7,7 @@ Disassembly of section .text: 80000000 <_start>: 80000000: 00100513 li a0,1 80000004: 02051073 csrw 0x20,a0 -80000008: 00100513 li a0,1 +80000008: 00200513 li a0,2 8000000c: 02151073 csrw 0x21,a0 80000010: f1401073 csrw mhartid,zero 80000014: 30101073 csrw misa,zero diff --git a/kernel/vortex_test.elf b/kernel/vortex_test.elf index 93e53274..1bad09ba 100755 Binary files a/kernel/vortex_test.elf and b/kernel/vortex_test.elf differ diff --git a/kernel/vortex_test.hex b/kernel/vortex_test.hex index 5660a498..1e7886e6 100644 --- a/kernel/vortex_test.hex +++ b/kernel/vortex_test.hex @@ -1,5 +1,5 @@ :0200000480007A -:10000000130510007310050213051000731015027C +:10000000130510007310050213052000731015026C :10001000731040F17310103037F1FF7FEF0080193B :10002000EF10C06D73000000938B0600130D0700E6 :10003000130F01009303050013051000635C7500A6 diff --git a/kernel/vx_os/vx_back/vx_back.s b/kernel/vx_os/vx_back/vx_back.s index e9067e8b..546d309a 100644 --- a/kernel/vx_os/vx_back/vx_back.s +++ b/kernel/vx_os/vx_back/vx_back.s @@ -8,7 +8,7 @@ _start: li a0, 1 # Num Warps csrw 0x20, a0 # Setting the number of available warps - li a0, 1 # Num Threads + li a0, 2 # Num Threads csrw 0x21, a0 # Setting the number of available threads csrw mhartid,zero csrw misa,zero diff --git a/rtl/VX_context.v b/rtl/VX_context.v new file mode 100644 index 00000000..cdbc80f2 --- /dev/null +++ b/rtl/VX_context.v @@ -0,0 +1,93 @@ + +`include "VX_define.v" + +module VX_context ( + input wire clk, + input wire in_valid[`NT_M1:0], + input wire in_write_register, + input wire[4:0] in_rd, + input wire[31:0] in_write_data[`NT_M1:0], + input wire[4:0] in_src1, + input wire[4:0] in_src2, + input wire[31:0] in_curr_PC, + input wire in_is_clone, + input wire in_is_jal, + input wire in_src1_fwd, + input wire[31:0] in_src1_fwd_data[`NT_M1:0], + input wire in_src2_fwd, + input wire[31:0] in_src2_fwd_data[`NT_M1:0], + + output reg[31:0] out_a_reg_data[`NT_M1:0], + output reg[31:0] out_b_reg_data[`NT_M1:0], + output wire out_clone_stall + +); + wire[31:0] rd1_register[`NT_M1:0]; + wire[31:0] rd2_register[`NT_M1:0]; + /* verilator lint_off UNUSED */ + wire[31:0] clone_regsiters[31:0]; + /* verilator lint_on UNUSED */ + + VX_register_file vx_register_file_master( + .clk (clk), + .in_valid (in_valid[0]), + .in_write_register (in_write_register), + .in_rd (in_rd), + .in_data (in_write_data[0]), + .in_src1 (in_src1), + .in_src2 (in_src2), + .out_regs (clone_regsiters), + .out_src1_data (rd1_register[0]), + .out_src2_data (rd2_register[0]) + ); + + genvar index; + generate + for (index=1; index < `NT; index=index+1) + begin: gen_code_label + wire to_clone; + assign to_clone = (index == rd1_register[0]) && (state_stall == 1); + VX_register_file_slave vx_register_file_slave( + .clk (clk), + .in_valid (in_valid[index]), + .in_write_register (in_write_register), + .in_rd (in_rd), + .in_data (in_write_data[index]), + .in_src1 (in_src1), + .in_src2 (in_src2), + .in_clone (in_is_clone), + .in_to_clone (to_clone), + .in_regs (clone_regsiters), + .out_src1_data (rd1_register[index]), + .out_src2_data (rd2_register[index]) + ); + end + endgenerate + + + reg[5:0] state_stall = 0; + always @(posedge clk) begin + if ((in_is_clone) && state_stall == 0) begin + state_stall <= 10; + // $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, in_is_clone); + end else if (state_stall == 1) begin + // $display("ENDING CLONE, 1 =? %h = %h -- %d", rd1_register[0], to_clone_1, in_is_clone); + state_stall <= 0; + end else if (state_stall > 0) begin + state_stall <= state_stall - 1; + // $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, in_is_clone); + end + end + + genvar index_out_reg; + generate + for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) + begin + assign out_a_reg_data[index_out_reg] = ( (in_is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg])); + assign out_b_reg_data[index_out_reg] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg]; + end + endgenerate + + assign out_clone_stall = ((state_stall == 0) && in_is_clone) || ((state_stall != 1) && in_is_clone); + +endmodule \ No newline at end of file diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v index 6e3fb499..5ae64dc8 100644 --- a/rtl/VX_decode.v +++ b/rtl/VX_decode.v @@ -49,10 +49,6 @@ module VX_decode( wire[6:0] curr_opcode; - - wire[31:0] rd1_register[`NT_M1:0]; - wire[31:0] rd2_register[`NT_M1:0]; - wire is_itype; wire is_rtype; wire is_stype; @@ -107,104 +103,31 @@ module VX_decode( reg[4:0] alu_op; reg[4:0] mul_alu; - // wire[31:0] internal_rd1; - // wire[31:0] internal_rd2; + VX_context VX_Context( + .clk (clk), + .in_valid (in_wb_valid), + .in_rd (in_rd), + .in_src1 (out_rs1), + .in_src2 (out_rs2), + .in_curr_PC (in_curr_PC), + .in_is_clone (is_clone), + .in_is_jal (is_jal), + .in_src1_fwd (in_src1_fwd), + .in_src1_fwd_data (in_src1_fwd_data), + .in_src2_fwd (in_src2_fwd), + .in_src2_fwd_data (in_src2_fwd_data), + .in_write_register(write_register), + .in_write_data (in_write_data), + .out_a_reg_data (out_a_reg_data), + .out_b_reg_data (out_b_reg_data), + .out_clone_stall (out_clone_stall) + ); - // VX_register_file vx_register_file_0( - // .clk(clk), - // .in_valid(in_wb_valid[0]), - // .in_write_register(write_register), - // .in_rd(in_rd), - // .in_data(in_write_data[1:0]), - // .in_src1(out_rs1), - // .in_src2(out_rs2), - // .out_src1_data(rd1_register), - // .out_src2_data(rd2_register) - // ); - - - // VX_register_file vx_register_file_1( - // .clk(clk), - // .in_valid(in_wb_valid), - // .in_write_register(write_register), - // .in_rd(in_rd), - // .in_data(in_write_data), - // .in_src1(out_rs1), - // .in_src2(out_rs2), - // .out_src1_data(rd1_register), - // .out_src2_data(rd2_register) - // ); assign out_valid = in_valid; assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0); - // always @(*) begin - // $display("DECODE PC: %h",in_curr_PC); - // end - - - // always @(posedge clk) begin - // $display("Decode: curr_pc: %h", in_curr_PC); - // end - /* verilator lint_off UNUSED */ - wire[31:0] clone_regsiters[31:0]; - /* verilator lint_on UNUSED */ - - VX_register_file vx_register_file_master( - .clk (clk), - .in_valid (in_wb_valid[0]), - .in_write_register (write_register), - .in_rd (in_rd), - .in_data (in_write_data[0]), - .in_src1 (out_rs1), - .in_src2 (out_rs2), - .out_regs (clone_regsiters), - .out_src1_data (rd1_register[0]), - .out_src2_data (rd2_register[0]) - ); - - - // wire to_clone_1 = (1 == rd1_register[0]) && (state_stall == 1); - - - // VX_register_file_slave vx_register_file_slave( - // .clk (clk), - // .in_valid (in_wb_valid[1]), - // .in_write_register (write_register), - // .in_rd (in_rd), - // .in_data (in_write_data[1]), - // .in_src1 (out_rs1), - // .in_src2 (out_rs2), - // .in_clone (is_clone), - // .in_to_clone (to_clone_1), - // .in_regs (clone_regsiters), - // .out_src1_data (rd1_register[1]), - // .out_src2_data (rd2_register[1]) - // ); - - genvar index; - generate - for (index=1; index < `NT; index=index+1) - begin: gen_code_label - wire to_clone; - assign to_clone = (index == rd1_register[0]) && (state_stall == 1); - VX_register_file_slave vx_register_file_slave( - .clk (clk), - .in_valid (in_wb_valid[index]), - .in_write_register (write_register), - .in_rd (in_rd), - .in_data (in_write_data[index]), - .in_src1 (out_rs1), - .in_src2 (out_rs2), - .in_clone (is_clone), - .in_to_clone (to_clone), - .in_regs (clone_regsiters), - .out_src1_data (rd1_register[index]), - .out_src2_data (rd2_register[index]) - ); - end - endgenerate assign curr_opcode = in_instruction[6:0]; @@ -278,32 +201,11 @@ module VX_decode( // $display("Decode inst: %h", in_instruction); // end - reg[5:0] state_stall = 0; - always @(posedge clk) begin - if ((is_clone) && state_stall == 0) begin - state_stall <= 10; - // $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone); - end else if (state_stall == 1) begin - // $display("ENDING CLONE, 1 =? %h = %h -- %d", rd1_register[0], to_clone_1, is_clone); - state_stall <= 0; - end else if (state_stall > 0) begin - state_stall <= state_stall - 1; - // $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone); - end - end - assign out_clone_stall = ((state_stall == 0) && is_clone) || ((state_stall != 1) && is_clone); // ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction); - genvar index_out_reg; - generate - for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) - begin - assign out_a_reg_data[index_out_reg] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg])); - assign out_b_reg_data[index_out_reg] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg]; - end - endgenerate + // assign out_reg_data[0] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[0] : rd1_register[0])); // assign out_reg_data[1] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[0] : rd2_register[0]; diff --git a/rtl/VX_define.h b/rtl/VX_define.h index 7c32053f..5fb42fb8 100644 --- a/rtl/VX_define.h +++ b/rtl/VX_define.h @@ -1,7 +1,7 @@ -#define NT 1 -#define NT_M1 0 +#define NT 2 +#define NT_M1 1 #define R_INST 51 #define L_INST 3 diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 320f0bfc..377cf319 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -1,6 +1,6 @@ -`define NT 1 -`define NT_M1 0 +`define NT 2 +`define NT_M1 1 `define R_INST 7'd51 diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index 37c35540..53d2cbe9 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -2,80 +2,60 @@ `include "VX_define.v" module VX_fetch ( - input wire clk, - input wire reset, - input wire in_branch_dir, - input wire in_freeze, - input wire[31:0] in_branch_dest, - input wire in_branch_stall, - input wire in_fwd_stall, - input wire in_branch_stall_exe, - input wire in_clone_stall, - input wire in_jal, - input wire[31:0] in_jal_dest, - input wire in_interrupt, - input wire in_debug, - input wire[31:0] in_instruction, - input wire in_thread_mask[`NT_M1:0], - input wire in_change_mask, + input wire clk, + input wire reset, + input wire in_branch_dir, + input wire in_freeze, + input wire[31:0] in_branch_dest, + input wire in_branch_stall, + input wire in_fwd_stall, + input wire in_branch_stall_exe, + input wire in_clone_stall, + input wire in_jal, + input wire[31:0] in_jal_dest, + input wire in_interrupt, + input wire in_debug, + input wire[31:0] in_instruction, + input wire in_thread_mask[`NT_M1:0], + input wire in_change_mask, - output wire[31:0] out_instruction, - output wire out_delay, - output wire[31:0] out_curr_PC, - output wire out_valid[`NT_M1:0] + output wire[31:0] out_instruction, + output wire out_delay, + // output wire[1:0] out_warp_num, + output wire[31:0] out_curr_PC, + output wire out_valid[`NT_M1:0] ); - reg stall; reg[31:0] out_PC; + // reg[1:0] warp_num; - reg valid[`NT_M1:0]; - - - integer ini_cur_th = 0; - genvar out_cur_th; - - initial begin - for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1) - valid[ini_cur_th] = 0; // Thread 1 active - valid[0] = 1; - end - - - always @(*) begin : proc_ - if (in_change_mask) begin - // $display("CHANGING MASK: [%d %d]",in_thread_mask[0], in_thread_mask[1]); - assign valid = in_thread_mask; - end - end + // initial begin + // warp_num = 0; + // end - assign out_delay = 0; assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || in_freeze || in_debug; - assign out_instruction = stall ? 32'b0 : in_instruction; - // assign out_instruction = in_instruction; - - generate - for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1) - assign out_valid[out_cur_th] = in_change_mask ? in_thread_mask[out_cur_th] : stall ? 1'b0 : valid[out_cur_th]; - endgenerate - - wire[31:0] warp_pc; + wire warp_valid[`NT_M1:0]; + VX_warp VX_Warp( .clk (clk), .reset (reset), .stall (stall), + .in_thread_mask(in_thread_mask), + .in_change_mask(in_change_mask), .in_jal (in_jal), .in_jal_dest (in_jal_dest), .in_branch_dir (in_branch_dir), .in_branch_dest(in_branch_dest), - .out_PC (warp_pc) + .out_PC (warp_pc), + .out_valid (warp_valid) ); @@ -86,15 +66,11 @@ module VX_fetch ( // end - assign out_curr_PC = out_PC; - - - - - // always @(*) begin - // $display("Fetch out pc: %h", out_PC); - // end - + assign out_curr_PC = out_PC; + assign out_valid = warp_valid; + // assign out_warp_num = warp_num; + assign out_delay = 0; + assign out_instruction = stall ? 32'b0 : in_instruction; diff --git a/rtl/VX_warp.v b/rtl/VX_warp.v index 4c05005d..f81b2871 100644 --- a/rtl/VX_warp.v +++ b/rtl/VX_warp.v @@ -1,24 +1,51 @@ +`include "VX_define.v" + module VX_warp ( - input wire clk, - input wire reset, - input wire stall, - input wire in_jal, - input wire[31:0] in_jal_dest, - input wire in_branch_dir, - input wire[31:0] in_branch_dest, + input wire clk, + input wire reset, + input wire stall, + input wire in_thread_mask[`NT_M1:0], + input wire in_change_mask, + input wire in_jal, + input wire[31:0] in_jal_dest, + input wire in_branch_dir, + input wire[31:0] in_branch_dest, - output wire[31:0] out_PC + output wire[31:0] out_PC, + output wire out_valid[`NT_M1:0] ); reg[31:0] real_PC; + var[31:0] temp_PC; + var[31:0] use_PC; + reg valid[`NT_M1:0]; + + integer ini_cur_th = 0; initial begin real_PC = 0; + for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1) + valid[ini_cur_th] = 0; // Thread 1 active + valid[0] = 1; end - var[31:0] temp_PC; + + always @(*) begin + if (in_change_mask) begin + assign valid = in_thread_mask; + end + end + + + genvar out_cur_th; + generate + for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1) + assign out_valid[out_cur_th] = in_change_mask ? in_thread_mask[out_cur_th] : stall ? 1'b0 : valid[out_cur_th]; + endgenerate + + always @(*) begin if (in_jal == 1'b1) begin temp_PC = in_jal_dest; @@ -29,13 +56,16 @@ module VX_warp ( end end + assign use_PC = temp_PC; assign out_PC = temp_PC; always @(posedge clk or posedge reset) begin if (reset) begin real_PC <= 0; - end else if (stall != 1'b1) begin - real_PC <= temp_PC + 32'h4; + end else if (stall == 1'b0) begin + real_PC <= use_PC + 32'h4; + end else begin + real_PC <= use_PC; end end diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex index ac08fe27..8bc532bd 100755 Binary files a/rtl/obj_dir/VVortex and b/rtl/obj_dir/VVortex differ diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp index eac6f82d..9d9c8db9 100644 --- a/rtl/obj_dir/VVortex.cpp +++ b/rtl/obj_dir/VVortex.cpp @@ -95,12 +95,12 @@ void VVortex::_initial__TOP__1(VVortex__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_initial__TOP__1\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // INITIAL at VX_warp.v:17 + // INITIAL at VX_warp.v:27 vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC = 0U; - // INITIAL at VX_fetch.v:39 - vlTOPp->Vortex__DOT__vx_fetch__DOT__valid[0U] = 1U; - // INITIAL at VX_decode.v:281 - vlTOPp->Vortex__DOT__vx_decode__DOT__state_stall = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[0U] = 1U; + // INITIAL at VX_context.v:68 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall = 0U; // INITIAL at VX_m_w_reg.v:39 vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = 0U; vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = 0U; @@ -127,6 +127,10 @@ void VVortex::_initial__TOP__1(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[0U] = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] = 0U; // INITIAL at VX_d_e_reg.v:83 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[0U] = 0U; @@ -134,6 +138,11 @@ void VVortex::_initial__TOP__1(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[0U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[0U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[1U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = 0U; @@ -156,21 +165,136 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[0U] = 1U; + vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[1U] = 0U; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] + = vlTOPp->in_cache_driver_out_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] = vlTOPp->in_cache_driver_out_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid [0U]; - vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] - = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid [0U]; - vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] - = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[0U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result [0U]; @@ -192,7 +316,7 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U) : 0x55U)); - // ALWAYS at VX_decode.v:492 + // ALWAYS at VX_decode.v:397 vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)); vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = @@ -232,8 +356,12 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { >> 0xcU)))); vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle) @@ -258,28 +386,50 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { [vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address])))); vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read; vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid [0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [0U]; vlTOPp->Vortex__DOT__execute_branch_stall = ((0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal)); - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid - [0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data [0U]; @@ -293,18 +443,125 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data [0U]; + vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [1U]; vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0U]; + vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [1U]; vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid [0U]; + vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [1U]; vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result [0U]; + vlTOPp->Vortex__DOT__m_w_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [1U]; vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result [0U]; - // ALWAYS at VX_decode.v:423 + // ALWAYS at VX_decode.v:328 vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) ? ( @@ -440,11 +697,11 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { : 0xdeadbeefU) : 0xdeadbeefU)))))); vlTOPp->Vortex__DOT__decode_clone_stall = (((0U - == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__state_stall)) + == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall)) | (1U - != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__state_stall))) + != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall))) & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone)); - // ALWAYS at VX_decode.v:375 + // ALWAYS at VX_decode.v:280 if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { @@ -532,7 +789,7 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { } else { vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU; } - // ALWAYS at VX_decode.v:434 + // ALWAYS at VX_decode.v:339 if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { @@ -593,16 +850,28 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { } vlTOPp->Vortex__DOT__decode_change_mask = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt)); + vlTOPp->Vortex__DOT__e_m_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [1U]; vlTOPp->Vortex__DOT__e_m_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data [0U]; + vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [1U]; vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid [0U]; + vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [1U]; vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result [0U]; + vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [1U]; vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid [0U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [1U]; vlTOPp->Vortex__DOT__d_e_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data [0U]; + vlTOPp->Vortex__DOT__d_e_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [1U]; vlTOPp->Vortex__DOT__d_e_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data [0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd @@ -618,18 +887,128 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { >> 0x14U)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))); + vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [1U]; vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] + = vlTOPp->Vortex__DOT__m_w_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] = vlTOPp->Vortex__DOT__m_w_valid[0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] + = vlTOPp->Vortex__DOT__f_d_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] = vlTOPp->Vortex__DOT__f_d_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[0U] = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu @@ -713,16 +1092,28 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { >> 0x19U))) ? 0U : 1U)))))))))); + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] = vlTOPp->Vortex__DOT__e_m_b_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] + = vlTOPp->Vortex__DOT__e_m_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] = vlTOPp->Vortex__DOT__e_m_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] + = vlTOPp->Vortex__DOT__e_m_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] = vlTOPp->Vortex__DOT__e_m_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[1U] + = vlTOPp->Vortex__DOT__d_e_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] = vlTOPp->Vortex__DOT__d_e_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[0U] = vlTOPp->Vortex__DOT__d_e_a_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[0U] = vlTOPp->Vortex__DOT__d_e_b_reg_data[0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd @@ -749,14 +1140,27 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd))); + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[0U] = vlTOPp->Vortex__DOT__memory_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] = vlTOPp->Vortex__DOT__memory_mem_result[0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid [0U]; - // ALWAYS at VX_decode.v:375 + // ALWAYS at VX_decode.v:280 if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { @@ -821,7 +1225,7 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { } else { vlTOPp->Vortex__DOT__decode_jal = 0U; } - // ALWAYS at VX_decode.v:434 + // ALWAYS at VX_decode.v:339 if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { @@ -869,6 +1273,13 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { } else { vlTOPp->Vortex__DOT__decode_branch_stall = 0U; } + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [1U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [1U])); vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[0U] = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data @@ -876,19 +1287,25 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result [0U])); + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result - [0U]; - // ALWAYS at VX_warp.v:22 + // ALWAYS at VX_warp.v:49 vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC = ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest @@ -913,12 +1330,27 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { ? (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset << 1U)) : vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC)); + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data [0U]; @@ -927,32 +1359,62 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data [0U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [1U]); + vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)); vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling = (((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)) | (IData)(vlTOPp->Vortex__DOT__decode_clone_stall)); + vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)); + vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [1U]; vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid [0U]; vlTOPp->Vortex__DOT__vx_fetch__DOT__stall = ((((IData)(vlTOPp->Vortex__DOT__decode_clone_stall) | (IData)(vlTOPp->Vortex__DOT__decode_branch_stall)) | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); + vlTOPp->Vortex__DOT__writeback_write_data[1U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [1U]; vlTOPp->Vortex__DOT__writeback_write_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data [0U]; + vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [1U]; vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data [0U]; + vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [1U]; vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid [0U]; + vlTOPp->Vortex__DOT__memory_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [1U]; vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid [0U]; + vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC; + vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [1U]; vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address [0U]; - vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [1U]; vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result [0U]; + vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [1U]; vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid [0U]; + vlTOPp->Vortex__DOT__execute_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data + [1U]; vlTOPp->Vortex__DOT__execute_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data [0U]; vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result @@ -960,19 +1422,39 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U]), VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__decode_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] = vlTOPp->Vortex__DOT__decode_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] + = vlTOPp->Vortex__DOT__writeback_write_data + [1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] = vlTOPp->Vortex__DOT__writeback_write_data [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__memory_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] = vlTOPp->Vortex__DOT__memory_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__execute_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] = vlTOPp->Vortex__DOT__execute_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[0U] = vlTOPp->Vortex__DOT__execute_b_reg_data[0U]; // ALWAYS at VX_alu.v:48 @@ -1102,14 +1584,183 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))))); + // ALWAYS at VX_alu.v:48 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))))); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT__execute_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [1U]; vlTOPp->Vortex__DOT__execute_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[0U] = vlTOPp->Vortex__DOT__execute_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[0U] = vlTOPp->Vortex__DOT__execute_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[0U] = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) @@ -1138,6 +1789,34 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { [0U])) : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result [0U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[0U] = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) @@ -1166,68 +1845,163 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { [0U])) : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result [0U]))); + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [1U]; vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data [0U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [1U]; vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[0U] = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[0U] + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[0U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC - : ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)) - ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data - [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register [0U])); - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[0U] - = ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)) - ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data - [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[1U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register + [1U])); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register [0U]); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register + [1U]); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__decode_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [1U]; vlTOPp->Vortex__DOT__decode_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data [0U]; + vlTOPp->Vortex__DOT__decode_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [1U]; vlTOPp->Vortex__DOT__decode_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data [0U]; vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[0U] = VL_LTES_III(1,32,32, 0U, vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data [0U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[1U] + = VL_LTES_III(1,32,32, 1U, vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [0U]); + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[1U] + = vlTOPp->Vortex__DOT__decode_a_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[0U] = vlTOPp->Vortex__DOT__decode_a_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__decode_b_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[0U] = vlTOPp->Vortex__DOT__decode_b_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + ? vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask + [1U]); vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask[0U] = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) ? vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask [0U]); + vlTOPp->Vortex__DOT__decode_thread_mask[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask + [1U]; vlTOPp->Vortex__DOT__decode_thread_mask[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[1U] + = vlTOPp->Vortex__DOT__decode_thread_mask[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[0U] = vlTOPp->Vortex__DOT__decode_thread_mask[0U]; - // ALWAYS at VX_fetch.v:46 + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [0U]; + // ALWAYS at VX_warp.v:35 if (vlTOPp->Vortex__DOT__decode_change_mask) { - vlTOPp->Vortex__DOT__vx_fetch__DOT__valid[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask [0U]; } - vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[0U] = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) - ? vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) - & vlTOPp->Vortex__DOT__vx_fetch__DOT__valid + & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid [0U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[1U] + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask + [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid + [1U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid + [0U]; + vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [1U]; vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__fetch_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[0U] = vlTOPp->Vortex__DOT__fetch_valid[0U]; } @@ -1237,65 +2011,124 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Variables // Begin mtask footprint all: - VL_SIG8(__Vdly__Vortex__DOT__vx_decode__DOT__state_stall,5,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers__v0,4,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers__v0,0,0); + VL_SIG8(__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall,5,0); + VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0); VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1,0,0); VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1,0,0); VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1,0,0); VL_SIG8(__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0,0,0); VL_SIG16(__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0); VL_SIG16(__Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers__v0,31,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0,31,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1,31,0); // Body - __Vdly__Vortex__DOT__vx_decode__DOT__state_stall - = vlTOPp->Vortex__DOT__vx_decode__DOT__state_stall; - __Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers__v0 = 0U; + __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0 = 0U; __Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; // ALWAYS at VX_m_w_reg.v:60 __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid + [1U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1 = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid [0U]; // ALWAYS at VX_e_m_reg.v:126 __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data + [1U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1 = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data [0U]; - // ALWAYS at VX_decode.v:282 + // ALWAYS at VX_e_m_reg.v:126 + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid + [1U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid + [0U]; + // ALWAYS at VX_context.v:69 if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) - & (0U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__state_stall)))) { - __Vdly__Vortex__DOT__vx_decode__DOT__state_stall = 0xaU; + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall)))) { + __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall = 0xaU; } else { - if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__state_stall))) { - __Vdly__Vortex__DOT__vx_decode__DOT__state_stall = 0U; + if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall))) { + __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall = 0U; } else { - if ((0U < (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__state_stall))) { - __Vdly__Vortex__DOT__vx_decode__DOT__state_stall - = (0x3fU & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__state_stall) + if ((0U < (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall))) { + __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall + = (0x3fU & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall) - (IData)(1U))); } } } - // ALWAYS at VX_e_m_reg.v:126 - __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0 - = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid + // ALWAYS at VX_m_w_reg.v:60 + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result + [1U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result [0U]; // ALWAYS at VX_m_w_reg.v:60 __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result + [1U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1 = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result [0U]; - // ALWAYS at VX_m_w_reg.v:60 - __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0 - = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result - [0U]; - // ALWAYS at VX_csr_handler.v:34 - vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address - = vlTOPp->Vortex__DOT__decode_csr_address; // ALWAYS at VX_d_e_reg.v:139 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed = (0xfffffU & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) @@ -1310,6 +2143,9 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) >> 0xcU) : 0U)))); // ALWAYS at VX_csr_handler.v:34 + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address + = vlTOPp->Vortex__DOT__decode_csr_address; + // ALWAYS at VX_csr_handler.v:34 vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle); // ALWAYS at VX_csr_handler.v:34 @@ -1317,10 +2153,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret); } - // ALWAYS at VX_e_m_reg.v:126 - __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0 - = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result - [0U]; // ALWAYS at VX_d_e_reg.v:139 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src = (1U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) @@ -1328,56 +2160,67 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) | (0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) ? 1U : 0U)))); // ALWAYS at VX_e_m_reg.v:126 + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result + [1U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result + [0U]; + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal; // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type; // ALWAYS at VX_d_e_reg.v:139 __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid + [1U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1 = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid [0U]); // ALWAYS at VX_e_m_reg.v:126 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC; - // ALWAYS at VX_e_m_reg.v:126 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write; - // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read; // ALWAYS at VX_e_m_reg.v:126 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write; + // ALWAYS at VX_e_m_reg.v:126 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC; + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest = (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset); - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed; + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + // ALWAYS at VX_register_file.v:39 + if ((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid + [0U])) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data + [0U]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0 = 1U; + __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } // ALWAYS at VX_d_e_reg.v:139 __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0 = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z - [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data - [0U]); - // ALWAYS at VX_register_file.v:39 - if ((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) - & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid - [0U])) { - __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers__v0 - = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data - [0U]; - __Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers__v0 = 1U; - __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers__v0 - = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; - } - // ALWAYS at VX_d_e_reg.v:139 - __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0 + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data + [1U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1 = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z - [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data [0U]); // ALWAYS at VX_csr_handler.v:43 if (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr) { @@ -1387,60 +2230,292 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) __Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address; } - // ALWAYSPOST at VX_m_w_reg.v:69 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[0U] - = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0; - // ALWAYSPOST at VX_e_m_reg.v:137 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[0U] - = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0; - vlTOPp->Vortex__DOT__vx_decode__DOT__state_stall - = __Vdly__Vortex__DOT__vx_decode__DOT__state_stall; - // ALWAYSPOST at VX_e_m_reg.v:146 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] - = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0; - // ALWAYSPOST at VX_m_w_reg.v:63 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[0U] - = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0; - // ALWAYSPOST at VX_m_w_reg.v:62 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[0U] - = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0; - // ALWAYSPOST at VX_e_m_reg.v:128 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] - = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0; - // ALWAYSPOST at VX_d_e_reg.v:161 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] - = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0; - // ALWAYSPOST at VX_d_e_reg.v:144 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[0U] - = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0; - // ALWAYSPOST at VX_register_file.v:42 - if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers__v0) { - vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers__v0] - = __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers__v0; + // ALWAYS at VX_register_file_slave.v:44 + if (((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid + [1U]) & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone)))) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data + [1U]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & ((1U == vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register + [0U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall))))) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [9U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [8U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [7U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [6U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [5U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [4U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [3U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [2U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [1U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } } - // ALWAYSPOST at VX_d_e_reg.v:145 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[0U] - = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0; + // ALWAYS at VX_d_e_reg.v:139 + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data + [1U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data + [0U]); + // ALWAYSPOST at VX_m_w_reg.v:69 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[0U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1; + // ALWAYSPOST at VX_e_m_reg.v:137 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[1U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[0U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1; + // ALWAYSPOST at VX_e_m_reg.v:146 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1; + // ALWAYSPOST at VX_m_w_reg.v:62 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[1U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[0U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1; + // ALWAYSPOST at VX_m_w_reg.v:63 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[1U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[0U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1; + // ALWAYSPOST at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1; + // ALWAYSPOST at VX_d_e_reg.v:161 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1; + // ALWAYSPOST at VX_register_file.v:42 + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0) { + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0; + } + // ALWAYSPOST at VX_d_e_reg.v:144 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[1U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[0U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1; // ALWAYSPOST at VX_csr_handler.v:45 if (__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0) { vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr[__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0] = __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0; } + // ALWAYSPOST at VX_register_file_slave.v:47 + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall + = __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall; + // ALWAYSPOST at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[1U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[0U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[0U] - = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result - [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result [0U]; @@ -1451,20 +2526,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (IData)(vlTOPp->Vortex__DOT__decode_branch_type)); + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid [0U]; - // ALWAYS at VX_d_e_reg.v:139 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC = - ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) - ? 0U : vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC); - vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write; - // ALWAYS at VX_d_e_reg.v:139 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write - = (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) - ? 7U : ((0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) - ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xcU) : 7U))); vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read; // ALWAYS at VX_d_e_reg.v:139 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read @@ -1472,30 +2539,137 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) ? 7U : ((3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU) : 7U))); + vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write; + // ALWAYS at VX_d_e_reg.v:139 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write + = (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 7U : ((0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU) : 7U))); + // ALWAYS at VX_d_e_reg.v:139 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC = + ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC); // ALWAYS at VX_d_e_reg.v:139 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : vlTOPp->Vortex__DOT__decode_jal_offset); - vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] - = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; - vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] - = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; - // ALWAYS at VX_e_m_reg.v:126 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; // ALWAYS at VX_d_e_reg.v:139 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0xdeadbeefU : vlTOPp->Vortex__DOT__decode_itype_immed); + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + // ALWAYS at VX_e_m_reg.v:126 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data [0U]; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb; - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data - [0U]; // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address; @@ -1512,23 +2686,143 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) ? (vlTOPp->Vortex__DOT__csr_decode_csr_data & ((IData)(0xffffffffU) - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask)) : 0xdeadbeefU))); + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd; + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [0U]; + vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [1U]; vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid [0U]; + vlTOPp->Vortex__DOT__e_m_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [1U]; vlTOPp->Vortex__DOT__e_m_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data [0U]; + vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [1U]; vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid [0U]; - vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result - [0U]; + vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [1U]; vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result [0U]; + vlTOPp->Vortex__DOT__m_w_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [1U]; + vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [0U]; + vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [1U]; vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result [0U]; + vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [1U]; vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid [0U]; - vlTOPp->Vortex__DOT__d_e_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs [0U]; - vlTOPp->Vortex__DOT__d_e_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + vlTOPp->Vortex__DOT__d_e_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data [0U]; vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) @@ -1552,41 +2846,157 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) : vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr [vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address])))); + vlTOPp->Vortex__DOT__d_e_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__d_e_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] + = vlTOPp->Vortex__DOT__m_w_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] = vlTOPp->Vortex__DOT__m_w_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] = vlTOPp->Vortex__DOT__e_m_b_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] + = vlTOPp->Vortex__DOT__e_m_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] = vlTOPp->Vortex__DOT__e_m_valid[0U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[0U] - = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] - = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[0U] + = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] + = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] + = vlTOPp->Vortex__DOT__e_m_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] = vlTOPp->Vortex__DOT__e_m_alu_result[0U]; vlTOPp->Vortex__DOT__execute_branch_stall = ((0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal)); + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[1U] + = vlTOPp->Vortex__DOT__d_e_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] = vlTOPp->Vortex__DOT__d_e_valid[0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; // ALWAYS at VX_d_e_reg.v:139 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : ((IData)(4U) + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC)); + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[0U] = vlTOPp->Vortex__DOT__d_e_a_reg_data[0U]; - // ALWAYS at VX_e_m_reg.v:126 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd; - // ALWAYS at VX_e_m_reg.v:126 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[0U] - = vlTOPp->Vortex__DOT__d_e_b_reg_data[0U]; // ALWAYS at VX_d_e_reg.v:139 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) @@ -1612,15 +3022,45 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) ? (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu) : (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu))); + // ALWAYS at VX_e_m_reg.v:126 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd; + // ALWAYS at VX_e_m_reg.v:126 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [1U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [1U])); vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[0U] = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data @@ -1628,15 +3068,27 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result [0U])); + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data [0U]; @@ -1645,23 +3097,45 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data [0U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [1U]); + vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [1U]; vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data [0U]; + vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [1U]; vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid [0U]; + vlTOPp->Vortex__DOT__memory_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [1U]; vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid [0U]; + vlTOPp->Vortex__DOT__writeback_write_data[1U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [1U]; vlTOPp->Vortex__DOT__writeback_write_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data [0U]; + vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [1U]; vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address [0U]; + vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [1U]; vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result [0U]; + vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [1U]; vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid [0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; // ALWAYS at VX_d_e_reg.v:139 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = (0x1fU & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) @@ -1715,6 +3189,8 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr)) ? 1U : 0U)))); + vlTOPp->Vortex__DOT__execute_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data + [1U]; vlTOPp->Vortex__DOT__execute_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data [0U]; vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result @@ -1722,17 +3198,35 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U]), VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__memory_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] = vlTOPp->Vortex__DOT__memory_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] + = vlTOPp->Vortex__DOT__writeback_write_data + [1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] = vlTOPp->Vortex__DOT__writeback_write_data [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__execute_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] = vlTOPp->Vortex__DOT__execute_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[0U] = vlTOPp->Vortex__DOT__execute_b_reg_data[0U]; // ALWAYS at VX_alu.v:48 @@ -1862,12 +3356,153 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))))); + // ALWAYS at VX_alu.v:48 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))))); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT__execute_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [1U]; vlTOPp->Vortex__DOT__execute_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[0U] = vlTOPp->Vortex__DOT__execute_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[0U] = vlTOPp->Vortex__DOT__execute_alu_result[0U]; } @@ -1878,20 +3513,18 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp) // Variables // Begin mtask footprint all: VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0,0,0); - VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v1,0,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v1,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3,0,0); // Body __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 0U; - __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v1 = 0U; - // ALWAYS at VX_warp.v:34 - if (vlTOPp->reset) { - vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)))) { - vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC - = ((IData)(4U) + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC); - } - } + __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 0U; + // ALWAYS at VX_warp.v:62 + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC + = ((IData)(vlTOPp->reset) ? 0U : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC + : ((IData)(4U) + + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC))); // ALWAYS at VX_f_d_reg.v:33 if (vlTOPp->reset) { vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC = 0U; @@ -1908,21 +3541,27 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp) } else { if ((1U & (~ ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) | (IData)(vlTOPp->Vortex__DOT__decode_clone_stall))))) { - __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v1 + __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 + = vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid + [1U]; + __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 1U; + __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3 = vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid [0U]; - __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v1 = 1U; } } // ALWAYSPOST at VX_f_d_reg.v:38 if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0) { vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] = 0U; + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] = 0U; } - if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v1) { + if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2; vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] - = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v1; + = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3; } - // ALWAYS at VX_warp.v:22 + // ALWAYS at VX_warp.v:49 vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC = ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest @@ -1947,19 +3586,33 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp) ? (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset << 1U)) : vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC)); + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid [0U]; vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [1U]; vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] + = vlTOPp->Vortex__DOT__f_d_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] = vlTOPp->Vortex__DOT__f_d_valid[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid [0U]; + vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [1U]; vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__decode_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] = vlTOPp->Vortex__DOT__decode_valid[0U]; } @@ -1968,15 +3621,26 @@ VL_INLINE_OPT void VVortex::_combo__TOP__5(VVortex__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_combo__TOP__5\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] + = vlTOPp->in_cache_driver_out_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] = vlTOPp->in_cache_driver_out_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data [0U]; + vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [1U]; vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[0U] = vlTOPp->Vortex__DOT__memory_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] = vlTOPp->Vortex__DOT__memory_mem_result[0U]; } @@ -1985,20 +3649,34 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__6\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // ALWAYS at VX_register_file.v:46 - vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src1_data - = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers + // ALWAYS at VX_register_file_slave.v:60 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU))]; // ALWAYS at VX_register_file.v:46 - vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src2_data - = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + // ALWAYS at VX_register_file_slave.v:60 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U))]; - vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] - = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src1_data; - vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] - = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src2_data; + // ALWAYS at VX_register_file.v:46 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data; } VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) { @@ -2034,7 +3712,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U) : 0x55U)); - // ALWAYS at VX_decode.v:492 + // ALWAYS at VX_decode.v:397 vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)); vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = @@ -2068,21 +3746,21 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) & (4U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)))); - vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs = - ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) - & (6U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xcU)))); vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd = ((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs = + ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (6U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))); vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd = ((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); - // ALWAYS at VX_decode.v:423 + // ALWAYS at VX_decode.v:328 vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) ? ( @@ -2218,11 +3896,17 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) : 0xdeadbeefU) : 0xdeadbeefU)))))); vlTOPp->Vortex__DOT__decode_clone_stall = (((0U - == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__state_stall)) + == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall)) | (1U - != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__state_stall))) + != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall))) & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone)); - // ALWAYS at VX_decode.v:375 + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd + = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))); + // ALWAYS at VX_decode.v:280 if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { @@ -2310,7 +3994,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) } else { vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU; } - // ALWAYS at VX_decode.v:375 + // ALWAYS at VX_decode.v:280 if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { @@ -2375,7 +4059,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) } else { vlTOPp->Vortex__DOT__decode_jal = 0U; } - // ALWAYS at VX_decode.v:434 + // ALWAYS at VX_decode.v:339 if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { @@ -2434,7 +4118,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) } else { vlTOPp->Vortex__DOT__decode_branch_type = 0U; } - // ALWAYS at VX_decode.v:434 + // ALWAYS at VX_decode.v:339 if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { @@ -2484,12 +4168,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) } vlTOPp->Vortex__DOT__decode_change_mask = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt)); - vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd - = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) - & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) - & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))); vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) @@ -2497,6 +4175,14 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) >> 0x14U)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd + = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd))); vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu = ((0x63U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? ((5U > (IData)(vlTOPp->Vortex__DOT__decode_branch_type)) @@ -2578,14 +4264,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) >> 0x19U))) ? 0U : 1U)))))))))); - vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd - = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) - & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU)))) & (0U - != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) - & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) - & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd))); vlTOPp->Vortex__DOT__forwarding_fwd_stall = ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)) & (2U @@ -2602,6 +4280,9 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd))); + vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)); vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling = (((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)) @@ -2610,12 +4291,43 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) | (IData)(vlTOPp->Vortex__DOT__decode_branch_stall)) | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); + vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)); } VL_INLINE_OPT void VVortex::_combo__TOP__8(VVortex__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_combo__TOP__8\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[0U] = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) @@ -2644,6 +4356,34 @@ VL_INLINE_OPT void VVortex::_combo__TOP__8(VVortex__Syms* __restrict vlSymsp) { [0U])) : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result [0U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[0U] = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) @@ -2672,68 +4412,163 @@ VL_INLINE_OPT void VVortex::_combo__TOP__8(VVortex__Syms* __restrict vlSymsp) { [0U])) : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result [0U]))); + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [1U]; vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data [0U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [1U]; vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[0U] = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[0U] + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[0U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC - : ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)) - ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data - [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register [0U])); - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[0U] - = ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)) - ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data - [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[1U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register + [1U])); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register [0U]); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register + [1U]); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__decode_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [1U]; vlTOPp->Vortex__DOT__decode_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data [0U]; + vlTOPp->Vortex__DOT__decode_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [1U]; vlTOPp->Vortex__DOT__decode_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data [0U]; vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[0U] = VL_LTES_III(1,32,32, 0U, vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data [0U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[1U] + = VL_LTES_III(1,32,32, 1U, vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [0U]); + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[1U] + = vlTOPp->Vortex__DOT__decode_a_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[0U] = vlTOPp->Vortex__DOT__decode_a_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__decode_b_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[0U] = vlTOPp->Vortex__DOT__decode_b_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + ? vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask + [1U]); vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask[0U] = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) ? vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask [0U]); + vlTOPp->Vortex__DOT__decode_thread_mask[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask + [1U]; vlTOPp->Vortex__DOT__decode_thread_mask[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[1U] + = vlTOPp->Vortex__DOT__decode_thread_mask[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[0U] = vlTOPp->Vortex__DOT__decode_thread_mask[0U]; - // ALWAYS at VX_fetch.v:46 + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [0U]; + // ALWAYS at VX_warp.v:35 if (vlTOPp->Vortex__DOT__decode_change_mask) { - vlTOPp->Vortex__DOT__vx_fetch__DOT__valid[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask [0U]; } - vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[0U] = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) - ? vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) - & vlTOPp->Vortex__DOT__vx_fetch__DOT__valid + & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid [0U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[1U] + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask + [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid + [1U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid + [0U]; + vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [1U]; vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__fetch_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[0U] = vlTOPp->Vortex__DOT__fetch_valid[0U]; } @@ -2812,292 +4647,297 @@ void VVortex::_ctor_var_reset() { clk = VL_RAND_RESET_I(1); reset = VL_RAND_RESET_I(1); fe_instruction = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32); }} curr_PC = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32); }} out_cache_driver_in_mem_read = VL_RAND_RESET_I(3); out_cache_driver_in_mem_write = VL_RAND_RESET_I(3); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__fetch_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__f_d_valid[__Vi0] = VL_RAND_RESET_I(1); }} Vortex__DOT__decode_branch_stall = VL_RAND_RESET_I(1); Vortex__DOT__decode_csr_address = VL_RAND_RESET_I(12); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__decode_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__decode_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__decode_itype_immed = VL_RAND_RESET_I(32); Vortex__DOT__decode_branch_type = VL_RAND_RESET_I(3); Vortex__DOT__decode_jal = VL_RAND_RESET_I(1); Vortex__DOT__decode_jal_offset = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__decode_valid[__Vi0] = VL_RAND_RESET_I(1); }} Vortex__DOT__decode_clone_stall = VL_RAND_RESET_I(1); Vortex__DOT__decode_change_mask = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__decode_thread_mask[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__d_e_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__d_e_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__d_e_valid[__Vi0] = VL_RAND_RESET_I(1); }} Vortex__DOT__execute_branch_stall = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__execute_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__execute_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__execute_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__e_m_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__e_m_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__e_m_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__memory_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__memory_mem_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__memory_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__m_w_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__m_w_mem_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__m_w_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__writeback_write_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__csr_decode_csr_data = VL_RAND_RESET_I(32); Vortex__DOT__forwarding_fwd_stall = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + Vortex__DOT__forwarding_src1_fwd = VL_RAND_RESET_I(1); + Vortex__DOT__forwarding_src2_fwd = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__forwarding_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__forwarding_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_fetch__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_decode__out_thread_mask[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_decode__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_decode__in_write_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_decode__in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_execute__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_execute__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_execute__in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_memory__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_memory__out_mem_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_memory__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_memory__in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_memory__in_rd2[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_memory__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_writeback__out_write_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_fetch__DOT__stall = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - Vortex__DOT__vx_fetch__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__warp_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1); }} Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC = VL_RAND_RESET_I(32); Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} Vortex__DOT__vx_f_d_reg__DOT__instruction = VL_RAND_RESET_I(32); Vortex__DOT__vx_f_d_reg__DOT__curr_PC = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_f_d_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - Vortex__DOT__vx_decode__DOT__rd1_register[__Vi0] = VL_RAND_RESET_I(32); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - Vortex__DOT__vx_decode__DOT__rd2_register[__Vi0] = VL_RAND_RESET_I(32); - }} Vortex__DOT__vx_decode__DOT__is_itype = VL_RAND_RESET_I(1); Vortex__DOT__vx_decode__DOT__is_csr = VL_RAND_RESET_I(1); Vortex__DOT__vx_decode__DOT__is_clone = VL_RAND_RESET_I(1); @@ -3105,24 +4945,62 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_decode__DOT__is_jmprt = VL_RAND_RESET_I(1); Vortex__DOT__vx_decode__DOT__alu_tempp = VL_RAND_RESET_I(12); Vortex__DOT__vx_decode__DOT__mul_alu = VL_RAND_RESET_I(5); - Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src2_data = VL_RAND_RESET_I(32); - Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src1_data = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[__Vi0] = VL_RAND_RESET_I(1); }} - Vortex__DOT__vx_decode__DOT__state_stall = VL_RAND_RESET_I(6); Vortex__DOT__vx_decode__DOT__temp_final_alu = VL_RAND_RESET_I(5); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[__Vi0] = VL_RAND_RESET_I(32); + }} { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall = VL_RAND_RESET_I(6); + Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_d_e_reg__DOT__rd = VL_RAND_RESET_I(5); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_d_e_reg__DOT__alu_op = VL_RAND_RESET_I(5); @@ -3140,27 +5018,30 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_d_e_reg__DOT__curr_PC = VL_RAND_RESET_I(32); Vortex__DOT__vx_d_e_reg__DOT__jal = VL_RAND_RESET_I(1); Vortex__DOT__vx_d_e_reg__DOT__jal_offset = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_d_e_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_d_e_reg__DOT__valid_z[__Vi0] = VL_RAND_RESET_I(1); }} Vortex__DOT__vx_d_e_reg__DOT__stalling = VL_RAND_RESET_I(1); Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32); Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32); Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_e_m_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_e_m_reg__DOT__rd = VL_RAND_RESET_I(5); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_e_m_reg__DOT__wb = VL_RAND_RESET_I(2); @@ -3175,22 +5056,22 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_e_m_reg__DOT__branch_type = VL_RAND_RESET_I(3); Vortex__DOT__vx_e_m_reg__DOT__jal = VL_RAND_RESET_I(1); Vortex__DOT__vx_e_m_reg__DOT__jal_dest = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_e_m_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_m_w_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_m_w_reg__DOT__mem_result[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_m_w_reg__DOT__rd = VL_RAND_RESET_I(5); Vortex__DOT__vx_m_w_reg__DOT__wb = VL_RAND_RESET_I(2); Vortex__DOT__vx_m_w_reg__DOT__PC_next = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_m_w_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_writeback__DOT__out_pc_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd = VL_RAND_RESET_I(1); @@ -3199,13 +5080,13 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd = VL_RAND_RESET_I(1); Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd = VL_RAND_RESET_I(1); Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<4096; ++__Vi0) { diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h index 87d5c4cb..ddbe3dd4 100644 --- a/rtl/obj_dir/VVortex.h +++ b/rtl/obj_dir/VVortex.h @@ -27,10 +27,10 @@ VL_MODULE(VVortex) { VL_OUT8(out_cache_driver_in_mem_write,2,0); VL_IN(fe_instruction,31,0); VL_OUT(curr_PC,31,0); - VL_IN(in_cache_driver_out_data[1],31,0); - VL_OUT(out_cache_driver_in_address[1],31,0); - VL_OUT8(out_cache_driver_in_valid[1],0,0); - VL_OUT(out_cache_driver_in_data[1],31,0); + VL_IN(in_cache_driver_out_data[2],31,0); + VL_OUT(out_cache_driver_in_address[2],31,0); + VL_OUT8(out_cache_driver_in_valid[2],0,0); + VL_OUT(out_cache_driver_in_data[2],31,0); // LOCAL SIGNALS // Internals; generally not touched by application code @@ -44,6 +44,8 @@ VL_MODULE(VVortex) { VL_SIG8(Vortex__DOT__decode_change_mask,0,0); VL_SIG8(Vortex__DOT__execute_branch_stall,0,0); VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0); + VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0); + VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0); @@ -51,8 +53,8 @@ VL_MODULE(VVortex) { VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jalrs,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jmprt,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0); - VL_SIG8(Vortex__DOT__vx_decode__DOT__state_stall,5,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_final_alu,4,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall,5,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,4,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0); @@ -97,133 +99,156 @@ VL_MODULE(VVortex) { VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0); VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0); + }; + struct { VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0); - }; - struct { VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0); VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0); + VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0); - VL_SIG8(Vortex__DOT__fetch_valid[1],0,0); - VL_SIG8(Vortex__DOT__f_d_valid[1],0,0); - VL_SIG(Vortex__DOT__decode_a_reg_data[1],31,0); - VL_SIG(Vortex__DOT__decode_b_reg_data[1],31,0); - VL_SIG8(Vortex__DOT__decode_valid[1],0,0); - VL_SIG8(Vortex__DOT__decode_thread_mask[1],0,0); - VL_SIG(Vortex__DOT__d_e_a_reg_data[1],31,0); - VL_SIG(Vortex__DOT__d_e_b_reg_data[1],31,0); - VL_SIG8(Vortex__DOT__d_e_valid[1],0,0); - VL_SIG(Vortex__DOT__execute_alu_result[1],31,0); - VL_SIG(Vortex__DOT__execute_b_reg_data[1],31,0); - VL_SIG8(Vortex__DOT__execute_valid[1],0,0); - VL_SIG(Vortex__DOT__e_m_alu_result[1],31,0); - VL_SIG(Vortex__DOT__e_m_b_reg_data[1],31,0); - VL_SIG8(Vortex__DOT__e_m_valid[1],0,0); - VL_SIG(Vortex__DOT__memory_alu_result[1],31,0); - VL_SIG(Vortex__DOT__memory_mem_result[1],31,0); - VL_SIG8(Vortex__DOT__memory_valid[1],0,0); - VL_SIG(Vortex__DOT__m_w_alu_result[1],31,0); - VL_SIG(Vortex__DOT__m_w_mem_result[1],31,0); - VL_SIG8(Vortex__DOT__m_w_valid[1],0,0); - VL_SIG(Vortex__DOT__writeback_write_data[1],31,0); - VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[1],31,0); - VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[1],31,0); - VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid[1],0,0); - VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[1],0,0); - VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[1],31,0); - VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[1],31,0); - VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[1],0,0); - VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[1],0,0); - VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers[32],31,0); - VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[1],31,0); - VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[1],31,0); - VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[1],0,0); - VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[1],31,0); - VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[1],0,0); - VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[1],31,0); - VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[1],31,0); - VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[1],31,0); - VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[1],0,0); - VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[1],31,0); - VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[1],31,0); - VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[1],0,0); - VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[1],31,0); - VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1],31,0); - VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1],31,0); - VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1],31,0); + VL_SIG8(Vortex__DOT__fetch_valid[2],0,0); + VL_SIG8(Vortex__DOT__f_d_valid[2],0,0); + VL_SIG(Vortex__DOT__decode_a_reg_data[2],31,0); + VL_SIG(Vortex__DOT__decode_b_reg_data[2],31,0); + VL_SIG8(Vortex__DOT__decode_valid[2],0,0); + VL_SIG8(Vortex__DOT__decode_thread_mask[2],0,0); + VL_SIG(Vortex__DOT__d_e_a_reg_data[2],31,0); + VL_SIG(Vortex__DOT__d_e_b_reg_data[2],31,0); + VL_SIG8(Vortex__DOT__d_e_valid[2],0,0); + VL_SIG(Vortex__DOT__execute_alu_result[2],31,0); + VL_SIG(Vortex__DOT__execute_b_reg_data[2],31,0); + VL_SIG8(Vortex__DOT__execute_valid[2],0,0); + VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0); + VL_SIG(Vortex__DOT__e_m_b_reg_data[2],31,0); + VL_SIG8(Vortex__DOT__e_m_valid[2],0,0); + VL_SIG(Vortex__DOT__memory_alu_result[2],31,0); + VL_SIG(Vortex__DOT__memory_mem_result[2],31,0); + VL_SIG8(Vortex__DOT__memory_valid[2],0,0); + VL_SIG(Vortex__DOT__m_w_alu_result[2],31,0); + VL_SIG(Vortex__DOT__m_w_mem_result[2],31,0); + VL_SIG8(Vortex__DOT__m_w_valid[2],0,0); + VL_SIG(Vortex__DOT__writeback_write_data[2],31,0); + VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0); + VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_valid[2],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[2],0,0); + VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[2],0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[2],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[2],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[2],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2],31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2],31,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2],31,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[2],0,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[2],31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[2],31,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[2],0,0); + VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0); + VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0); + VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[2],0,0); + VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0); + VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0); + VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0); + VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2],31,0); VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0); }; // LOCAL VARIABLES // Internals; generally not touched by application code - // Begin mtask footprint all: - VL_SIG8(__Vtableidx1,2,0); - VL_SIG8(__Vclklast__TOP__clk,0,0); - VL_SIG8(__Vclklast__TOP__reset,0,0); - VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0); - VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0); - VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[1],0,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[1],0,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1],0,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1],0,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_thread_mask[1],0,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[1],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[1],0,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[1],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[1],31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[1],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[1],31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1],31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1],31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[1],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1],31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1],31,0); + // Anonymous structures to workaround compiler member-count bugs + struct { + // Begin mtask footprint all: + VL_SIG8(__Vtableidx1,2,0); + VL_SIG8(__Vclklast__TOP__clk,0,0); + VL_SIG8(__Vclklast__TOP__reset,0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[2],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_thread_mask[2],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0); + }; + struct { + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[2],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[2],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[2],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[2],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[2],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[2],31,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[2],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0); + }; static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0); // INTERNAL VARIABLES diff --git a/rtl/obj_dir/VVortex__ALL.a b/rtl/obj_dir/VVortex__ALL.a index 1210e548..4bcfefdd 100644 Binary files a/rtl/obj_dir/VVortex__ALL.a and b/rtl/obj_dir/VVortex__ALL.a differ diff --git a/rtl/obj_dir/VVortex__ALLcls.o b/rtl/obj_dir/VVortex__ALLcls.o index 9d6eca9f..4f1428ba 100644 Binary files a/rtl/obj_dir/VVortex__ALLcls.o and b/rtl/obj_dir/VVortex__ALLcls.o differ diff --git a/rtl/obj_dir/VVortex__ver.d b/rtl/obj_dir/VVortex__ver.d index 265eb2b5..d75f342b 100644 --- a/rtl/obj_dir/VVortex__ver.d +++ b/rtl/obj_dir/VVortex__ver.d @@ -1 +1 @@ -obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v +obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat index dc5bc316..be9b1889 100644 --- a/rtl/obj_dir/VVortex__verFiles.dat +++ b/rtl/obj_dir/VVortex__verFiles.dat @@ -2,27 +2,28 @@ C "-Wall -cc Vortex.v --exe test_bench.cpp" S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" S 2785 12889457986 1554064009 0 1554064009 0 "VX_alu.v" +S 3192 12890338917 1557297615 0 1557297615 0 "VX_context.v" S 1495 12889457987 1554023089 0 1554023089 0 "VX_csr_handler.v" S 5105 12889457988 1554023089 0 1554023089 0 "VX_d_e_reg.v" -S 15170 12890307904 1557104321 0 1557104321 0 "VX_decode.v" -S 1557 12890307906 1557104321 0 1557104321 0 "VX_define.v" +S 11838 12890307904 1557297599 0 1557297599 0 "VX_decode.v" +S 1557 12890307906 1557297794 0 1557297794 0 "VX_define.v" S 4077 12889457992 1554023089 0 1554023089 0 "VX_e_m_reg.v" S 3288 12889457993 1554023938 0 1554023938 0 "VX_execute.v" S 1558 12889457994 1554064040 0 1554064040 0 "VX_f_d_reg.v" -S 2237 12890309989 1557111275 0 1557111275 0 "VX_fetch.v" +S 1816 12890309989 1557267615 0 1557267615 0 "VX_fetch.v" S 5632 12889457996 1554023089 0 1554023089 0 "VX_forwarding.v" S 1677 12889457997 1554023089 0 1554023089 0 "VX_m_w_reg.v" S 3732 12890309990 1557110604 0 1557110604 0 "VX_memory.v" S 1078 12889457999 1554023928 0 1554023928 0 "VX_register_file.v" S 1387 12889458000 1554023933 0 1554023933 0 "VX_register_file_slave.v" -S 744 12890308905 1557110557 0 1557110557 0 "VX_warp.v" +S 1499 12890308905 1557267602 0 1557267602 0 "VX_warp.v" S 1454 12890307909 1557104321 0 1557104321 0 "VX_writeback.v" S 16949 12890307910 1557104321 0 1557104321 0 "Vortex.v" -T 145644 12890311152 1557111277 0 1557111277 0 "obj_dir/VVortex.cpp" -T 14410 12890311151 1557111277 0 1557111277 0 "obj_dir/VVortex.h" -T 1800 12890311154 1557111277 0 1557111277 0 "obj_dir/VVortex.mk" -T 530 12890311150 1557111277 0 1557111277 0 "obj_dir/VVortex__Syms.cpp" -T 711 12890311149 1557111277 0 1557111277 0 "obj_dir/VVortex__Syms.h" -T 499 12890311155 1557111277 0 1557111277 0 "obj_dir/VVortex__ver.d" -T 0 0 1557111277 0 1557111277 0 "obj_dir/VVortex__verFiles.dat" -T 1159 12890311153 1557111277 0 1557111277 0 "obj_dir/VVortex_classes.mk" +T 272889 12890339974 1557297809 0 1557297809 0 "obj_dir/VVortex.cpp" +T 16351 12890339973 1557297809 0 1557297809 0 "obj_dir/VVortex.h" +T 1800 12890339976 1557297809 0 1557297809 0 "obj_dir/VVortex.mk" +T 530 12890339972 1557297809 0 1557297809 0 "obj_dir/VVortex__Syms.cpp" +T 711 12890339971 1557297809 0 1557297809 0 "obj_dir/VVortex__Syms.h" +T 512 12890339977 1557297809 0 1557297809 0 "obj_dir/VVortex__ver.d" +T 0 0 1557297809 0 1557297809 0 "obj_dir/VVortex__verFiles.dat" +T 1159 12890339975 1557297809 0 1557297809 0 "obj_dir/VVortex_classes.mk" diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o index cc3f85af..f1593fc6 100644 Binary files a/rtl/obj_dir/test_bench.o and b/rtl/obj_dir/test_bench.o differ diff --git a/rtl/results.txt b/rtl/results.txt index e10a4dd0..56fe2d32 100644 --- a/rtl/results.txt +++ b/rtl/results.txt @@ -1,7 +1,7 @@ -# Dynamic Instructions: 149108 -# of total cycles: 149120 +# Dynamic Instructions: 122612 +# of total cycles: 122624 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.00008 +# CPI: 1.0001 # time to simulate: 6.95313e-310 milliseconds # GRADE: Failed on test: 0