diff --git a/hw/rtl/VX_scoreboard.v b/hw/rtl/VX_scoreboard.v
index 19ed46b7..eb8a43bd 100644
--- a/hw/rtl/VX_scoreboard.v
+++ b/hw/rtl/VX_scoreboard.v
@@ -53,7 +53,7 @@ module VX_scoreboard  #(
             stall_ctr <= 0;
         end else if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin            
             stall_ctr <= stall_ctr + 1;
-            assert(stall_ctr < 10000) else $error("*** %t: core%0d-stalled: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
+            assert(stall_ctr < 1000) else $error("*** %t: core%0d-stalled: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
                     $time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb, 
                     deq_inuse_regs[ibuf_deq_if.rd], deq_inuse_regs[ibuf_deq_if.rs1], deq_inuse_regs[ibuf_deq_if.rs2], deq_inuse_regs[ibuf_deq_if.rs3]);            
         end else if (ibuf_deq_if.valid && ibuf_deq_if.ready) begin
diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv
index 570eab1b..75b4e628 100644
--- a/hw/rtl/afu/vortex_afu.sv
+++ b/hw/rtl/afu/vortex_afu.sv
@@ -212,8 +212,6 @@ always @(posedge clk) begin
     scope_start         <= 0;
   `endif
   end else begin
-
-
     mmio_tx.mmioRdValid <= cp2af_sRxPort.c0.mmioRdValid; 
     mmio_tx.hdr.tid     <= mmio_hdr.tid;
   `ifdef SCOPE
@@ -881,8 +879,8 @@ always @(posedge clk) begin
   end
 
   if ((STATE_CSR_READ == state)
-    && vx_csr_io_rsp_ready
-    && vx_csr_io_rsp_valid) begin
+   && vx_csr_io_rsp_ready
+   && vx_csr_io_rsp_valid) begin
     cmd_csr_rdata <= vx_csr_io_rsp_data;
   end
 end
diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v
index 0d6491d2..c8a5c1d7 100644
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -477,7 +477,7 @@ end
             .WORD_SIZE          (WORD_SIZE),
             .NUM_REQS           (NUM_REQS),
             .MSHR_SIZE          (MSHR_SIZE),
-            .ALM_FULL           (MSHR_SIZE-1),
+            .ALM_FULL           (MSHR_SIZE-2),
             .CORE_TAG_WIDTH     (CORE_TAG_WIDTH)
         ) miss_resrv (
             .clk                (clk),
@@ -628,7 +628,7 @@ end
         VX_fifo_queue_xt #(
             .DATAW    (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH), 
             .SIZE     (DREQ_SIZE),
-            .ALM_FULL (DREQ_SIZE-1),
+            .ALM_FULL (DREQ_SIZE-2),
             .FASTRAM  (1)
         ) dram_req_queue (
             .clk     (clk),
@@ -693,8 +693,8 @@ end
             $display("%t: miss with incoming fill - addr=%0h", $time, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
             assert(!is_mshr_st1);
         end
-        if (pipeline_stall) begin
-            $display("%t: cache%0d:%0d pipeline-stall: mshr=%b, cwbq=%b, dwbq=%b", $time, CACHE_ID, BANK_ID, mshr_push_stall, crsq_push_stall, dreq_push_stall);
+        if (crsq_push_stall || mshr_almost_full || dreq_almost_full) begin
+            $display("%t: cache%0d:%0d pipeline-stall: mshr=%b, cwbq=%b, dwbq=%b", $time, CACHE_ID, BANK_ID, mshr_almost_full, crsq_push_stall, dreq_almost_full);
         end
         if (drsq_pop) begin
             $display("%t: cache%0d:%0d fill-rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), filldata_st0);