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tensor: Remove old ready_reg DPI code

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Hansung Kim
2024-07-27 17:36:02 -07:00
parent 01f6024a76
commit 7ad3f64528
1 changed files with 2 additions and 13 deletions
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15
hw/rtl/fpu/VX_tensor_dpu.sv
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@@ -14,6 +14,7 @@ module VX_tensor_dpu #(
input valid_in, input valid_in,
output ready_in, output ready_in,
// [rows][cols][dtype]
input [3:0][1:0][31:0] A_tile, input [3:0][1:0][31:0] A_tile,
input [1:0][3:0][31:0] B_tile, input [1:0][3:0][31:0] B_tile,
input [3:0][3:0][31:0] C_tile, input [3:0][3:0][31:0] C_tile,
@@ -30,18 +31,6 @@ module VX_tensor_dpu #(
// dpi_hmma(valid_in, A_tile, B_tile, C_tile, result_hmma); // dpi_hmma(valid_in, A_tile, B_tile, C_tile, result_hmma);
// end // end
// logic ready_reg;
// always @(posedge clk) begin
// if (reset) begin
// ready_reg <= '1;
// end else if (valid_in && ready_in) begin
// ready_reg <= '0;
// dpi_print_results(int'(ISW), int'(OCTET), A_tile, B_tile, C_tile, result_hmma);
// end else if (valid_out && ready_out) begin
// ready_reg <= '1;
// end
// end
// // fixed-latency queue // // fixed-latency queue
// VX_shift_register #( // VX_shift_register #(
// .DATAW (1 + $bits(wid)/* + $bits(D_tile)*/), // .DATAW (1 + $bits(wid)/* + $bits(D_tile)*/),
@@ -56,7 +45,7 @@ module VX_tensor_dpu #(
// ); // );
// ready as soon as valid_out // ready as soon as valid_out
// assign ready_in = ready_reg || valid_out; // assign ready_in = valid_out;
// fully pipelined; ready_in is coupled to ready_out by immediately // fully pipelined; ready_in is coupled to ready_out by immediately
// stalling // stalling