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tensor: Fix elaboration error on VCS

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This commit is contained in:
Hansung Kim
2024-05-01 21:35:53 -07:00
parent 675e8ea130
commit 7fc5b6a374
3 changed files with 8 additions and 7 deletions
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9
hw/rtl/core/VX_operands.sv
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@@ -308,10 +308,11 @@ module VX_operands import VX_gpu_pkg::*; #(
if (cycle == 32'd25000) begin
for (integer k = 0; k < `NUM_REGS * ISSUE_RATIO; ++k) begin
integer warp = i * ISSUE_RATIO + (k / `NUM_REGS);
integer thread = j;
integer register = k % `NUM_REGS;
$display("warp %0d, thread %0d, register %0d: %0x", warp, thread, register, gpr_ram.ram[k]);
$display("warp %0d, thread %0d, register %0d: %0x",
i * ISSUE_RATIO + (k / `NUM_REGS),
j,
k % `NUM_REGS,
gpr_ram.ram[k]);
end
end
end

2
hw/rtl/core/VX_reduce_unit.sv
View File

@@ -252,7 +252,7 @@ module VX_reduce_unit #(
VX_elastic_buffer #(
.DATAW(NUM_LANES + PID_WIDTH + 1 + 1),
.SIZE(NUM_PACKETS),
.SIZE(NUM_PACKETS)
) tmask_pid_store (
.clk(clk),
.reset(reset),

4
hw/rtl/core/VX_uop_sequencer.sv
View File

@@ -63,6 +63,8 @@ module VX_uop_sequencer import VX_gpu_pkg::*; (
localparam HMMA_SET3_STEP3_1 = UPC_BITS'(38);
// register layout: f0-f7 used for A, f8-f15 used for B, f16-f23 used for C
logic [UPC_BITS-1:0] upc, upc_r, upc_n;
always @(*) begin
case (upc)
`include "VX_tensor_ucode.vh"
@@ -72,8 +74,6 @@ module VX_uop_sequencer import VX_gpu_pkg::*; (
endcase
end
logic [UPC_BITS-1:0] upc, upc_r, upc_n;
wire [UBR_BITS-1:0] ubr = uop[UOP_TABLE_WIDTH-1:UOP_TABLE_WIDTH-UBR_BITS];
wire [UPC_BITS-1:0] next_upc = uop[UOP_TABLE_WIDTH-UBR_BITS-1:UOP_TABLE_WIDTH-UBR_BITS-UPC_BITS];