simx timing simulation refactoring
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@@ -20,11 +20,7 @@ struct CacheConfig {
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uint8_t latency; // pipeline latency
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};
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class Cache : public SimObject<Cache> {
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private:
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class Impl;
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Impl* impl_;
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class Cache : public SimObject<Cache> {
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public:
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Cache(const SimContext& ctx, const char* name, const CacheConfig& config);
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~Cache();
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@@ -35,6 +31,10 @@ public:
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std::vector<MasterPort<MemRsp>> CoreRspPorts;
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MasterPort<MemReq> MemReqPort;
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SlavePort<MemRsp> MemRspPort;
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private:
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class Impl;
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Impl* impl_;
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};
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}
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