simx timing simulation refactoring

This commit is contained in:
Blaise Tine
2021-11-14 08:52:34 -05:00
parent 9656779d48
commit 808bddb586
22 changed files with 1123 additions and 903 deletions

View File

@@ -20,11 +20,7 @@ struct CacheConfig {
uint8_t latency; // pipeline latency
};
class Cache : public SimObject<Cache> {
private:
class Impl;
Impl* impl_;
class Cache : public SimObject<Cache> {
public:
Cache(const SimContext& ctx, const char* name, const CacheConfig& config);
~Cache();
@@ -35,6 +31,10 @@ public:
std::vector<MasterPort<MemRsp>> CoreRspPorts;
MasterPort<MemReq> MemReqPort;
SlavePort<MemRsp> MemRspPort;
private:
class Impl;
Impl* impl_;
};
}