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added config.vh

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This commit is contained in:
Blaise Tine
2020-04-16 07:49:19 -04:00
parent c913e542e9
commit 81745f08c9
109 changed files with 1426 additions and 1544 deletions
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115
hw/rtl/Vortex.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "VX_cache_config.v"
`include "VX_define.vh"
`include "VX_cache_config.vh"
module Vortex
#(
@@ -13,24 +13,24 @@ module Vortex
// IO
output wire io_valid,
output wire[31:0] io_data,
output wire [31:0] io_data,
// DRAM Dcache Req
output wire dram_req,
output wire dram_req_write,
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG],
output wire [31:0] dram_expected_lat,
output wire dram_req,
output wire dram_req_write,
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`DBANK_LINE_SIZE-1:0] dram_req_data,
output wire [31:0] dram_expected_lat,
input wire dram_req_delay,
input wire dram_req_delay,
// DRAM Dcache Res
output wire dram_fill_accept,
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
output wire dram_fill_accept,
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [`DBANK_LINE_SIZE-1:0] dram_fill_rsp_data,
// DRAM Icache Req
output wire I_dram_req,
@@ -38,25 +38,25 @@ module Vortex
output wire I_dram_req_read,
output wire [31:0] I_dram_req_addr,
output wire [31:0] I_dram_req_size,
output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
output wire [`IBANK_LINE_SIZE-1:0] I_dram_req_data,
output wire [31:0] I_dram_expected_lat,
// DRAM Icache Res
output wire I_dram_fill_accept,
input wire I_dram_fill_rsp,
input wire [31:0] I_dram_fill_rsp_addr,
input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
input wire [`IBANK_LINE_SIZE-1:0] I_dram_fill_rsp_data,
// LLC Snooping
input wire snp_req,
input wire [31:0] snp_req_addr,
output wire snp_req_delay,
input wire snp_req,
input wire [31:0] snp_req_addr,
output wire snp_req_delay,
input wire I_snp_req,
input wire [31:0] I_snp_req_addr,
output wire I_snp_req_delay,
output wire out_ebreak
output wire out_ebreak
`else
@@ -72,14 +72,14 @@ module Vortex
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire [`DBANK_LINE_SIZE-1:0] dram_req_data,
output wire [31:0] dram_expected_lat,
// DRAM Dcache Res
output wire dram_fill_accept,
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
input wire [`DBANK_LINE_SIZE-1:0] dram_fill_rsp_data,
// DRAM Icache Req
@@ -88,16 +88,16 @@ module Vortex
output wire I_dram_req_read,
output wire [31:0] I_dram_req_addr,
output wire [31:0] I_dram_req_size,
output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
output wire [`IBANK_LINE_SIZE-1:0] I_dram_req_data,
output wire [31:0] I_dram_expected_lat,
// DRAM Icache Res
output wire I_dram_fill_accept,
input wire I_dram_fill_rsp,
input wire [31:0] I_dram_fill_rsp_addr,
input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
input wire [`IBANK_LINE_SIZE-1:0] I_dram_fill_rsp_data,
input wire dram_req_delay,
input wire dram_req_delay,
input wire snp_req,
input wire [31:0] snp_req_addr,
@@ -110,27 +110,24 @@ module Vortex
output wire out_ebreak
`endif
);
wire scheduler_empty;
wire out_ebreak_unqual;
// assign out_ebreak = out_ebreak_unqual && (scheduler_empty && 1);
assign out_ebreak = out_ebreak_unqual;
wire memory_delay;
wire exec_delay;
wire gpr_stage_delay;
wire schedule_delay;
// Dcache Interface
VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp();
VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req();
VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req_qual();
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_req();
VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_res();
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) VX_gpu_dcache_dram_req();
VX_gpu_dcache_dram_res_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) VX_gpu_dcache_dram_res();
assign VX_gpu_dcache_dram_res.dram_fill_rsp = dram_fill_rsp;
@@ -146,36 +143,40 @@ module Vortex
assign VX_gpu_dcache_dram_req.dram_req_delay = dram_req_delay;
genvar wordy;
genvar i;
generate
for (wordy = 0; wordy < `DBANK_LINE_SIZE_WORDS; wordy=wordy+1) begin
assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[wordy] = dram_fill_rsp_data[wordy];
assign dram_req_data[wordy] = VX_gpu_dcache_dram_req.dram_req_data[wordy];
for (i = 0; i < `DBANK_LINE_WORDS; i=i+1) begin
assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[i] = dram_fill_rsp_data[i * 32 +: 32];
assign dram_req_data[i * 32 +: 32] = VX_gpu_dcache_dram_req.dram_req_data[i];
end
endgenerate
wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write[0] != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000);
wire temp_io_valid = (!memory_delay)
&& (|VX_dcache_req.core_req_valid)
&& (VX_dcache_req.core_req_mem_write[0] != `NO_MEM_WRITE)
&& (VX_dcache_req.core_req_addr[0] == 32'h00010000);
wire[31:0] temp_io_data = VX_dcache_req.core_req_writedata[0];
assign io_valid = temp_io_valid;
assign io_data = temp_io_data;
assign VX_dcache_req_qual.core_req_valid = VX_dcache_req.core_req_valid & {`NT{~io_valid}};
assign VX_dcache_req_qual.core_req_addr = VX_dcache_req.core_req_addr;
assign VX_dcache_req_qual.core_req_writedata = VX_dcache_req.core_req_writedata;
assign VX_dcache_req_qual.core_req_mem_read = VX_dcache_req.core_req_mem_read;
assign VX_dcache_req_qual.core_req_mem_write = VX_dcache_req.core_req_mem_write;
assign VX_dcache_req_qual.core_req_rd = VX_dcache_req.core_req_rd;
assign VX_dcache_req_qual.core_req_wb = VX_dcache_req.core_req_wb;
assign VX_dcache_req_qual.core_req_warp_num = VX_dcache_req.core_req_warp_num;
assign VX_dcache_req_qual.core_req_pc = VX_dcache_req.core_req_pc;
assign VX_dcache_req_qual.core_no_wb_slot = VX_dcache_req.core_no_wb_slot;
assign VX_dcache_req_qual.core_req_valid = VX_dcache_req.core_req_valid & {`NUM_THREADS{~io_valid}};
assign VX_dcache_req_qual.core_req_addr = VX_dcache_req.core_req_addr;
assign VX_dcache_req_qual.core_req_writedata = VX_dcache_req.core_req_writedata;
assign VX_dcache_req_qual.core_req_mem_read = VX_dcache_req.core_req_mem_read;
assign VX_dcache_req_qual.core_req_mem_write = VX_dcache_req.core_req_mem_write;
assign VX_dcache_req_qual.core_req_rd = VX_dcache_req.core_req_rd;
assign VX_dcache_req_qual.core_req_wb = VX_dcache_req.core_req_wb;
assign VX_dcache_req_qual.core_req_warp_num = VX_dcache_req.core_req_warp_num;
assign VX_dcache_req_qual.core_req_pc = VX_dcache_req.core_req_pc;
assign VX_dcache_req_qual.core_no_wb_slot = VX_dcache_req.core_no_wb_slot;
VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`INUMBER_REQUESTS)) VX_icache_rsp();
VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`INUMBER_REQUESTS)) VX_icache_req();
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`IBANK_LINE_SIZE_WORDS)) VX_gpu_icache_dram_req();
VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`IBANK_LINE_SIZE_WORDS)) VX_gpu_icache_dram_res();
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) VX_gpu_icache_dram_req();
VX_gpu_dcache_dram_res_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) VX_gpu_icache_dram_res();
assign VX_gpu_icache_dram_res.dram_fill_rsp = I_dram_fill_rsp;
@@ -191,11 +192,11 @@ module Vortex
assign VX_gpu_icache_dram_req.dram_req_delay = dram_req_delay;
genvar iwordy;
genvar j;
generate
for (iwordy = 0; iwordy < `IBANK_LINE_SIZE_WORDS; iwordy=iwordy+1) begin
assign VX_gpu_icache_dram_res.dram_fill_rsp_data[iwordy] = I_dram_fill_rsp_data[iwordy];
assign I_dram_req_data[iwordy] = VX_gpu_icache_dram_req.dram_req_data[iwordy];
for (j = 0; j < `IBANK_LINE_WORDS; j = j + 1) begin
assign VX_gpu_icache_dram_res.dram_fill_rsp_data[j] = I_dram_fill_rsp_data[j * 32 +: 32];
assign I_dram_req_data[j * 32 +: 32] = VX_gpu_icache_dram_req.dram_req_data[j];
end
endgenerate
@@ -239,7 +240,7 @@ VX_front_end vx_front_end(
.VX_jal_rsp (VX_jal_rsp),
.VX_branch_rsp (VX_branch_rsp),
.fetch_ebreak (out_ebreak_unqual)
);
);
VX_scheduler schedule(
.clk (clk),
@@ -251,7 +252,7 @@ VX_scheduler schedule(
.VX_writeback_inter(VX_writeback_inter),
.schedule_delay (schedule_delay),
.is_empty (scheduler_empty)
);
);
VX_back_end #(.CORE_ID(CORE_ID)) vx_back_end(
.clk (clk),
@@ -267,7 +268,7 @@ VX_back_end #(.CORE_ID(CORE_ID)) vx_back_end(
.out_mem_delay (memory_delay),
.out_exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay)
);
);
VX_dmem_controller VX_dmem_controller(
@@ -291,7 +292,7 @@ VX_dmem_controller VX_dmem_controller(
// Core <-> Dcache
.VX_dcache_req (VX_dcache_req_qual),
.VX_dcache_rsp (VX_dcache_rsp)
);
);
// VX_csr_handler vx_csr_handler(
// .clk (clk),
@@ -300,7 +301,7 @@ VX_dmem_controller VX_dmem_controller(
// .in_wb_valid (VX_writeback_inter.wb_valid[0]),
// .out_decode_csr_data (csr_decode_csr_data)
// );
// );
endmodule // Vortex