From 8296e6be0fb39e151f84784e060f7a6e3fccfcea Mon Sep 17 00:00:00 2001 From: Nico Castaneda Date: Fri, 6 Oct 2023 13:20:31 -0700 Subject: [PATCH] relu test added --- tests/regression/Makefile | 6 + tests/regression/relu/.depend | 2 + tests/regression/relu/Makefile | 77 + tests/regression/relu/common.h | 12 + tests/regression/relu/kernel.bin | Bin 0 -> 5172 bytes tests/regression/relu/kernel.c | 26 + tests/regression/relu/kernel.dump | 1815 ++++++++++++++++++++++ tests/regression/relu/kernel.elf | Bin 0 -> 12116 bytes tests/regression/relu/main.cpp | 218 +++ tests/regression/relu/ramulator.ddr4.log | 278 ++++ tests/regression/relu/relu | Bin 0 -> 27424 bytes 11 files changed, 2434 insertions(+) create mode 100644 tests/regression/relu/.depend create mode 100644 tests/regression/relu/Makefile create mode 100644 tests/regression/relu/common.h create mode 100755 tests/regression/relu/kernel.bin create mode 100644 tests/regression/relu/kernel.c create mode 100644 tests/regression/relu/kernel.dump create mode 100755 tests/regression/relu/kernel.elf create mode 100644 tests/regression/relu/main.cpp create mode 100644 tests/regression/relu/ramulator.ddr4.log create mode 100755 tests/regression/relu/relu diff --git a/tests/regression/Makefile b/tests/regression/Makefile index 157d74a6..63ca6070 100644 --- a/tests/regression/Makefile +++ b/tests/regression/Makefile @@ -11,6 +11,7 @@ all: $(MAKE) -C no_mf_ext $(MAKE) -C no_smem $(MAKE) -C prefetch + $(MAKE) -C relu run-simx: $(MAKE) -C basic run-simx @@ -25,6 +26,7 @@ run-simx: $(MAKE) -C no_mf_ext run-simx $(MAKE) -C no_smem run-simx $(MAKE) -C prefetch run-simx + $(MAKE) -C relu run-simx run-rtlsim: $(MAKE) -C basic run-rtlsim @@ -39,6 +41,7 @@ run-rtlsim: $(MAKE) -C no_mf_ext run-rtlsim $(MAKE) -C no_smem run-rtlsim $(MAKE) -C prefetch run-rtlsim + $(MAKE) -C relu run-rtlsim run-vlsim: $(MAKE) -C basic run-vlsim @@ -53,6 +56,7 @@ run-vlsim: $(MAKE) -C no_mf_ext run-vlsim $(MAKE) -C no_smem run-vlsim $(MAKE) -C prefetch run-vlsim + $(MAKE) -C relu run-vlsim clean: $(MAKE) -C basic clean @@ -67,6 +71,7 @@ clean: $(MAKE) -C no_mf_ext clean $(MAKE) -C no_smem clean $(MAKE) -C prefetch clean + $(MAKE) -C relu clean clean-all: $(MAKE) -C basic clean-all @@ -81,3 +86,4 @@ clean-all: $(MAKE) -C no_mf_ext clean-all $(MAKE) -C no_smem clean-all $(MAKE) -C prefetch clean-all + $(MAKE) -C relu clean-all diff --git a/tests/regression/relu/.depend b/tests/regression/relu/.depend new file mode 100644 index 00000000..b65090d5 --- /dev/null +++ b/tests/regression/relu/.depend @@ -0,0 +1,2 @@ +main.o: main.cpp \ + /home/eecs/nicolas.a.castaneda/vortex/driver/include/vortex.h common.h diff --git a/tests/regression/relu/Makefile b/tests/regression/relu/Makefile new file mode 100644 index 00000000..ff8d8671 --- /dev/null +++ b/tests/regression/relu/Makefile @@ -0,0 +1,77 @@ +XLEN ?= 32 + +VORTEX_DRV_PATH ?= $(realpath ../../../driver) +VORTEX_RT_PATH ?= $(realpath ../../../runtime) + +OPTS ?= -n64 + +VX_CC = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-gcc +VX_CXX = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-g++ +VX_DP = $(LLVM_PREFIX)/bin/llvm-objdump +VX_CP = $(LLVM_PREFIX)/bin/llvm-objcopy + +VX_CFLAGS += -march=rv32imf -mabi=ilp32f -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections +VX_CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw + +VX_LDFLAGS += -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link$(XLEN).ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a + +VX_SRCS = kernel.c + +CXXFLAGS += -std=c++11 -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I$(VORTEX_DRV_PATH)/include + +LDFLAGS += -L$(VORTEX_DRV_PATH)/stub -lvortex + +# Debugigng +ifdef DEBUG + CXXFLAGS += -g -O0 +else + CXXFLAGS += -O2 -DNDEBUG +endif + +PROJECT = relu + +SRCS = main.cpp + +all: $(PROJECT) kernel.bin kernel.dump + +kernel.dump: kernel.elf + $(VX_DP) -D kernel.elf > kernel.dump + +kernel.bin: kernel.elf + $(VX_CP) -O binary kernel.elf kernel.bin + +kernel.elf: $(VX_SRCS) + $(VX_CC) $(VX_CFLAGS) $(VX_SRCS) $(VX_LDFLAGS) -o kernel.elf + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ + +run-simx: $(PROJECT) kernel.bin + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +run-fpga: $(PROJECT) kernel.bin + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +run-asesim: $(PROJECT) kernel.bin + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +run-vlsim: $(PROJECT) kernel.bin + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +run-rtlsim: $(PROJECT) kernel.bin + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $^ > .depend; + +clean: + rm -rf $(PROJECT) *.o .depend + +clean-all: clean + rm -rf *.elf *.bin *.dump + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif \ No newline at end of file diff --git a/tests/regression/relu/common.h b/tests/regression/relu/common.h new file mode 100644 index 00000000..ccb28bb9 --- /dev/null +++ b/tests/regression/relu/common.h @@ -0,0 +1,12 @@ +#ifndef _COMMON_H_ +#define _COMMON_H_ + +#define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 + +typedef struct { + uint32_t num_points; + uint32_t src_addr; + uint32_t dst_addr; +} kernel_arg_t; + +#endif \ No newline at end of file diff --git a/tests/regression/relu/kernel.bin b/tests/regression/relu/kernel.bin new file mode 100755 index 0000000000000000000000000000000000000000..db8bddc49176d762cbe7debcb7cacc15be66dd29 GIT binary patch literal 5172 zcmeH}ZERat8ONXd?zE$Gd!0Bzpn1JcoMcrMbcZ7C3l1a=l_nIV34}mUbXkiOjTC~G zeq!!!95)3`WoJsV3DHugaRjJyWU3?*A5t}`yD6X`DA5pVD@>Do0L3Gz-G$7T|Km8J zYuP70FripF`pf5@-+5lnb6$Gu{hPxYk%-6lcl)o7`b48W9t7)+2+9?lRcP-Iy{~%#}cp$z0`@dzDXwt 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zjlLmbGT-YSY9VUt1);twU{6@Z<2Y`R$+Z-J~>~4Se9fI{YcgYW|{x zyFs!Vz6(E3OAb}3=3eZPAENE?lc>sjZulsf{p+6dSydLVg(;)HPEP+`)lIegomih{ zs_UNUpY?JzPkRra>2A|iNohVUxy@~o@{}aGPvQM^sQi8^-#KpNDDL5QwH{8fztv!4eV~*iHM##$iX7#}$sZ~_S_*B^N=cgDDH4jR06_uR-^wRk7^ zY##p!e#h?R_2X}w*1 +#include +#include +#include "common.h" + +void kernel_body(int __DIVERGENT__ task_id, kernel_arg_t* arg) { + uint32_t num_points = arg->num_points; + uint32_t points_per_core = num_points / vx_num_warps(); + int tid = vx_thread_lid(); + int32_t* src_ptr = (int32_t*)arg->src_addr; + int32_t* dst_ptr = (int32_t*)arg->dst_addr; + + int32_t ref_value = src_ptr[task_id]; + int ref_negative = ref_value < 0; + if (ref_negative) { + ref_value = 0; + } + + dst_ptr[task_id] = ref_value; +} + +void main() { + kernel_arg_t* arg = (kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + int num_warps = vx_num_warps(); + vx_spawn_tasks(arg->num_points, (vx_spawn_tasks_cb)kernel_body, arg); +} \ No newline at end of file diff --git a/tests/regression/relu/kernel.dump b/tests/regression/relu/kernel.dump new file mode 100644 index 00000000..3e6daac7 --- /dev/null +++ b/tests/regression/relu/kernel.dump @@ -0,0 +1,1815 @@ + +kernel.elf: file format ELF32-riscv + + +Disassembly of section .init: + +80000000 _start: +80000000: 73 25 10 fc csrr a0, 4033 +80000004: 97 05 00 00 auipc a1, 0 +80000008: 93 85 85 11 addi a1, a1, 280 +8000000c: 6b 10 b5 00 vx_wspawn a0, a1 +80000010: ef 00 c0 10 jal 268 +80000014: 13 05 10 00 addi a0, zero, 1 +80000018: 6b 00 05 00 vx_tmc a0 +8000001c: 73 25 10 fc csrr a0, 4033 +80000020: 97 05 00 00 auipc a1, 0 +80000024: 93 85 85 14 addi a1, a1, 328 +80000028: 6b 10 b5 00 vx_wspawn a0, a1 +8000002c: ef 00 c0 13 jal 316 +80000030: 13 05 10 00 addi a0, zero, 1 +80000034: 6b 00 05 00 vx_tmc a0 +80000038: 17 15 00 00 auipc a0, 1 +8000003c: 13 05 c5 3f addi a0, a0, 1020 +80000040: 17 16 00 00 auipc a2, 1 +80000044: 13 06 46 47 addi a2, a2, 1140 +80000048: 33 06 a6 40 sub a2, a2, a0 +8000004c: 93 05 00 00 mv a1, zero +80000050: ef 00 50 09 jal 2196 +80000054: 17 05 00 00 auipc a0, 0 +80000058: 13 05 45 20 addi a0, a0, 516 +8000005c: ef 00 00 6d jal 1744 +80000060: ef 00 40 16 jal 356 +80000064: ef 00 c0 03 jal 60 +80000068: 6f 00 40 00 j 4 + +Disassembly of section .text: + +8000006c exit: +8000006c: 13 01 01 ff addi sp, sp, -16 +80000070: 93 05 00 00 mv a1, zero +80000074: 23 24 81 00 sw s0, 8(sp) +80000078: 23 26 11 00 sw ra, 12(sp) +8000007c: 13 04 05 00 mv s0, a0 +80000080: ef 00 d0 1d jal 2524 +80000084: 17 15 00 00 auipc a0, 1 +80000088: 03 25 c5 3a lw a0, 940(a0) +8000008c: 83 27 c5 03 lw a5, 60(a0) +80000090: 63 84 07 00 beqz a5, 8 +80000094: e7 80 07 00 jalr a5 +80000098: 13 05 04 00 mv a0, s0 +8000009c: ef 00 c0 06 jal 108 + +800000a0 main: +800000a0: f3 27 10 fc csrr a5, 4033 +800000a4: b7 f7 ff 7f lui a5, 524287 +800000a8: 03 a5 07 00 lw a0, 0(a5) +800000ac: b7 05 00 80 lui a1, 524288 +800000b0: 37 f6 ff 7f lui a2, 524287 +800000b4: 93 85 45 0d addi a1, a1, 212 +800000b8: 6f 00 80 30 j 776 + +800000bc register_fini: +800000bc: 93 07 00 00 mv a5, zero +800000c0: 63 88 07 00 beqz a5, 16 +800000c4: 17 05 00 00 auipc a0, 0 +800000c8: 13 05 45 19 addi a0, a0, 404 +800000cc: 6f 00 00 66 j 1632 +800000d0: 67 80 00 00 ret + +800000d4 kernel_body: +800000d4: f3 27 10 fc csrr a5, 4033 +800000d8: f3 27 10 cc csrr a5, 3265 +800000dc: 83 a7 45 00 lw a5, 4(a1) +800000e0: 13 15 25 00 slli a0, a0, 2 +800000e4: 03 a7 85 00 lw a4, 8(a1) +800000e8: b3 87 a7 00 add a5, a5, a0 +800000ec: 83 a7 07 00 lw a5, 0(a5) +800000f0: 33 07 a7 00 add a4, a4, a0 +800000f4: 93 c6 f7 ff not a3, a5 +800000f8: 93 d6 f6 41 srai a3, a3, 31 +800000fc: b3 f7 d7 00 and a5, a5, a3 +80000100: 23 20 f7 00 sw a5, 0(a4) +80000104: 67 80 00 00 ret + +80000108 _exit: +80000108: 13 04 05 00 mv s0, a0 +8000010c: ef 00 c0 40 jal 1036 +80000110: 93 01 04 00 mv gp, s0 +80000114: 13 05 00 00 mv a0, zero +80000118: 6b 00 05 00 vx_tmc a0 + +8000011c init_regs: +8000011c: 13 05 f0 ff addi a0, zero, -1 +80000120: 6b 00 05 00 vx_tmc a0 +80000124: 97 11 00 00 auipc gp, 1 +80000128: 93 81 41 6e addi gp, gp, 1764 +8000012c: 37 01 00 ff lui sp, 1044480 +80000130: 73 25 10 cc csrr a0, 3265 +80000134: 93 15 a5 00 slli a1, a0, 10 +80000138: 33 01 b1 40 sub sp, sp, a1 +8000013c: 93 05 00 00 mv a1, zero +80000140: 33 05 b5 02 +80000144: 17 12 00 00 auipc tp, 1 +80000148: 13 02 f2 3a addi tp, tp, 943 +8000014c: 33 02 a2 00 add tp, tp, a0 +80000150: 13 72 02 fc andi tp, tp, -64 +80000154: f3 26 30 cc csrr a3, 3267 +80000158: 63 86 06 00 beqz a3, 12 +8000015c: 13 05 00 00 mv a0, zero +80000160: 6b 00 05 00 vx_tmc a0 + +80000164 RETURN: +80000164: 67 80 00 00 ret + +80000168 __init_tls: +80000168: 13 01 01 ff addi sp, sp, -16 +8000016c: 23 26 11 00 sw ra, 12(sp) +80000170: 23 24 81 00 sw s0, 8(sp) +80000174: 93 07 f0 ff addi a5, zero, -1 +80000178: 6b 80 07 00 vx_tmc a5 +8000017c: 13 06 00 00 mv a2, zero +80000180: 13 05 02 00 mv a0, tp +80000184: 97 15 00 00 auipc a1, 1 +80000188: 93 85 c5 e7 addi a1, a1, -388 +8000018c: 13 04 02 00 mv s0, tp +80000190: ef 00 00 5b jal 1456 +80000194: 13 05 00 00 mv a0, zero +80000198: 13 06 00 00 mv a2, zero +8000019c: 93 05 00 00 mv a1, zero +800001a0: 33 05 a4 00 add a0, s0, a0 +800001a4: ef 00 00 74 jal 1856 +800001a8: f3 27 30 cc csrr a5, 3267 +800001ac: 93 b7 17 00 seqz a5, a5 +800001b0: 6b 80 07 00 vx_tmc a5 +800001b4: 83 20 c1 00 lw ra, 12(sp) +800001b8: 03 24 81 00 lw s0, 8(sp) +800001bc: 13 01 01 01 addi sp, sp, 16 +800001c0: 67 80 00 00 ret + +800001c4 __libc_init_array: +800001c4: 13 01 01 ff addi sp, sp, -16 +800001c8: 23 24 81 00 sw s0, 8(sp) +800001cc: 23 20 21 01 sw s2, 0(sp) +800001d0: 97 17 00 00 auipc a5, 1 +800001d4: 93 87 07 e3 addi a5, a5, -464 +800001d8: 17 14 00 00 auipc s0, 1 +800001dc: 13 04 84 e2 addi s0, s0, -472 +800001e0: 23 26 11 00 sw ra, 12(sp) +800001e4: 23 22 91 00 sw s1, 4(sp) +800001e8: 33 89 87 40 sub s2, a5, s0 +800001ec: 63 80 87 02 beq a5, s0, 32 +800001f0: 13 59 29 40 srai s2, s2, 2 +800001f4: 93 04 00 00 mv s1, zero +800001f8: 83 27 04 00 lw a5, 0(s0) +800001fc: 93 84 14 00 addi s1, s1, 1 +80000200: 13 04 44 00 addi s0, s0, 4 +80000204: e7 80 07 00 jalr a5 +80000208: e3 e8 24 ff bltu s1, s2, -16 +8000020c: 97 17 00 00 auipc a5, 1 +80000210: 93 87 87 df addi a5, a5, -520 +80000214: 17 14 00 00 auipc s0, 1 +80000218: 13 04 c4 de addi s0, s0, -532 +8000021c: 33 89 87 40 sub s2, a5, s0 +80000220: 13 59 29 40 srai s2, s2, 2 +80000224: 63 8e 87 00 beq a5, s0, 28 +80000228: 93 04 00 00 mv s1, zero +8000022c: 83 27 04 00 lw a5, 0(s0) +80000230: 93 84 14 00 addi s1, s1, 1 +80000234: 13 04 44 00 addi s0, s0, 4 +80000238: e7 80 07 00 jalr a5 +8000023c: e3 e8 24 ff bltu s1, s2, -16 +80000240: 83 20 c1 00 lw ra, 12(sp) +80000244: 03 24 81 00 lw s0, 8(sp) +80000248: 83 24 41 00 lw s1, 4(sp) +8000024c: 03 29 01 00 lw s2, 0(sp) +80000250: 13 01 01 01 addi sp, sp, 16 +80000254: 67 80 00 00 ret + +80000258 __libc_fini_array: +80000258: 13 01 01 ff addi sp, sp, -16 +8000025c: 23 24 81 00 sw s0, 8(sp) +80000260: 97 17 00 00 auipc a5, 1 +80000264: 93 87 47 da addi a5, a5, -604 +80000268: 17 14 00 00 auipc s0, 1 +8000026c: 13 04 c4 d9 addi s0, s0, -612 +80000270: 33 04 f4 40 sub s0, s0, a5 +80000274: 23 22 91 00 sw s1, 4(sp) +80000278: 23 26 11 00 sw ra, 12(sp) +8000027c: 93 54 24 40 srai s1, s0, 2 +80000280: 63 80 04 02 beqz s1, 32 +80000284: 13 04 c4 ff addi s0, s0, -4 +80000288: 33 04 f4 00 add s0, s0, a5 +8000028c: 83 27 04 00 lw a5, 0(s0) +80000290: 93 84 f4 ff addi s1, s1, -1 +80000294: 13 04 c4 ff addi s0, s0, -4 +80000298: e7 80 07 00 jalr a5 +8000029c: e3 98 04 fe bnez s1, -16 +800002a0: 83 20 c1 00 lw ra, 12(sp) +800002a4: 03 24 81 00 lw s0, 8(sp) +800002a8: 83 24 41 00 lw s1, 4(sp) +800002ac: 13 01 01 01 addi sp, sp, 16 +800002b0: 67 80 00 00 ret + +800002b4 spawn_tasks_all_stub: +800002b4: 13 01 01 ff addi sp, sp, -16 +800002b8: 23 26 11 00 sw ra, 12(sp) +800002bc: 23 24 81 00 sw s0, 8(sp) +800002c0: 23 22 91 00 sw s1, 4(sp) +800002c4: 23 20 21 01 sw s2, 0(sp) +800002c8: 73 26 50 cc csrr a2, 3269 +800002cc: 73 27 30 cc csrr a4, 3267 +800002d0: f3 26 00 cc csrr a3, 3264 +800002d4: f3 25 00 fc csrr a1, 4032 +800002d8: 97 17 00 00 auipc a5, 1 +800002dc: 93 87 c7 15 addi a5, a5, 348 +800002e0: 13 16 26 00 slli a2, a2, 2 +800002e4: b3 87 c7 00 add a5, a5, a2 +800002e8: 83 a4 07 00 lw s1, 0(a5) +800002ec: 83 a7 04 01 lw a5, 16(s1) +800002f0: 03 a6 c4 00 lw a2, 12(s1) +800002f4: 33 29 f7 00 slt s2, a4, a5 +800002f8: 33 04 e6 02 +800002fc: 33 09 c9 00 add s2, s2, a2 +80000300: 63 54 f7 00 bge a4, a5, 8 +80000304: 93 07 07 00 mv a5, a4 +80000308: 33 04 f4 00 add s0, s0, a5 +8000030c: 03 a7 84 00 lw a4, 8(s1) +80000310: 33 04 b4 02 +80000314: b3 07 d9 02 +80000318: 33 04 e4 00 add s0, s0, a4 +8000031c: 33 04 f4 00 add s0, s0, a5 +80000320: 33 09 89 00 add s2, s2, s0 +80000324: 63 5e 24 01 bge s0, s2, 28 +80000328: 83 a7 04 00 lw a5, 0(s1) +8000032c: 83 a5 44 00 lw a1, 4(s1) +80000330: 13 05 04 00 mv a0, s0 +80000334: 13 04 14 00 addi s0, s0, 1 +80000338: e7 80 07 00 jalr a5 +8000033c: e3 16 89 fe bne s2, s0, -20 +80000340: 03 a7 44 01 lw a4, 20(s1) +80000344: 93 07 00 00 mv a5, zero +80000348: 6b c0 e7 00 vx_bar a5, a4 +8000034c: 83 20 c1 00 lw ra, 12(sp) +80000350: 03 24 81 00 lw s0, 8(sp) +80000354: 83 24 41 00 lw s1, 4(sp) +80000358: 03 29 01 00 lw s2, 0(sp) +8000035c: 13 01 01 01 addi sp, sp, 16 +80000360: 67 80 00 00 ret + +80000364 spawn_tasks_rem_stub: +80000364: 73 27 50 cc csrr a4, 3269 +80000368: 73 25 20 cc csrr a0, 3266 +8000036c: 97 17 00 00 auipc a5, 1 +80000370: 93 87 87 0c addi a5, a5, 200 +80000374: 13 17 27 00 slli a4, a4, 2 +80000378: b3 87 e7 00 add a5, a5, a4 +8000037c: 83 a7 07 00 lw a5, 0(a5) +80000380: 83 a6 87 00 lw a3, 8(a5) +80000384: 03 a7 07 00 lw a4, 0(a5) +80000388: 83 a5 47 00 lw a1, 4(a5) +8000038c: 33 05 d5 00 add a0, a0, a3 +80000390: 67 00 07 00 jr a4 + +80000394 spawn_tasks_all_cb: +80000394: 13 01 01 ff addi sp, sp, -16 +80000398: 23 26 11 00 sw ra, 12(sp) +8000039c: 93 07 f0 ff addi a5, zero, -1 +800003a0: 6b 80 07 00 vx_tmc a5 +800003a4: ef f0 1f f1 jal -240 +800003a8: f3 27 30 cc csrr a5, 3267 +800003ac: 93 b7 17 00 seqz a5, a5 +800003b0: 6b 80 07 00 vx_tmc a5 +800003b4: 83 20 c1 00 lw ra, 12(sp) +800003b8: 13 01 01 01 addi sp, sp, 16 +800003bc: 67 80 00 00 ret + +800003c0 vx_spawn_tasks: +800003c0: 13 01 01 fd addi sp, sp, -48 +800003c4: 23 26 11 02 sw ra, 44(sp) +800003c8: 23 24 81 02 sw s0, 40(sp) +800003cc: 23 22 91 02 sw s1, 36(sp) +800003d0: 23 20 21 03 sw s2, 32(sp) +800003d4: f3 26 20 fc csrr a3, 4034 +800003d8: f3 28 10 fc csrr a7, 4033 +800003dc: f3 24 00 fc csrr s1, 4032 +800003e0: f3 27 50 cc csrr a5, 3269 +800003e4: 13 07 f0 01 addi a4, zero, 31 +800003e8: 63 48 f7 08 blt a4, a5, 144 +800003ec: 33 88 14 03 +800003f0: 13 07 10 00 addi a4, zero, 1 +800003f4: 63 54 a8 00 bge a6, a0, 8 +800003f8: 33 47 05 03 +800003fc: 63 ca e6 08 blt a3, a4, 148 +80000400: 63 dc e7 06 bge a5, a4, 120 +80000404: 93 86 f6 ff addi a3, a3, -1 +80000408: 33 43 e5 02 +8000040c: 13 08 03 00 mv a6, t1 +80000410: 63 96 f6 00 bne a3, a5, 12 +80000414: 33 65 e5 02 +80000418: 33 08 65 00 add a6, a0, t1 +8000041c: 33 49 98 02 +80000420: 33 64 98 02 +80000424: 63 4c 19 07 blt s2, a7, 120 +80000428: 13 05 10 00 addi a0, zero, 1 +8000042c: b3 46 19 03 +80000430: 63 86 06 00 beqz a3, 12 +80000434: 13 85 06 00 mv a0, a3 +80000438: b3 66 19 03 +8000043c: 17 17 00 00 auipc a4, 1 +80000440: 13 07 87 ff addi a4, a4, -8 +80000444: 23 24 b1 00 sw a1, 8(sp) +80000448: 23 26 c1 00 sw a2, 12(sp) +8000044c: 23 2a a1 00 sw a0, 20(sp) +80000450: 23 2c d1 00 sw a3, 24(sp) +80000454: 23 2e 01 00 sw zero, 28(sp) +80000458: 33 03 f3 02 +8000045c: 93 97 27 00 slli a5, a5, 2 +80000460: b3 07 f7 00 add a5, a4, a5 +80000464: 13 07 81 00 addi a4, sp, 8 +80000468: 23 a0 e7 00 sw a4, 0(a5) +8000046c: 23 28 61 00 sw t1, 16(sp) +80000470: 63 4c 20 03 bgtz s2, 56 +80000474: 63 16 04 06 bnez s0, 108 +80000478: 83 20 c1 02 lw ra, 44(sp) +8000047c: 03 24 81 02 lw s0, 40(sp) +80000480: 83 24 41 02 lw s1, 36(sp) +80000484: 03 29 01 02 lw s2, 32(sp) +80000488: 13 01 01 03 addi sp, sp, 48 +8000048c: 67 80 00 00 ret +80000490: 13 87 06 00 mv a4, a3 +80000494: e3 c8 e7 f6 blt a5, a4, -144 +80000498: 6f f0 1f fe j -32 +8000049c: 93 06 00 00 mv a3, zero +800004a0: 13 05 10 00 addi a0, zero, 1 +800004a4: 6f f0 9f f9 j -104 +800004a8: 93 07 09 00 mv a5, s2 +800004ac: 63 d4 28 01 bge a7, s2, 8 +800004b0: 93 87 08 00 mv a5, a7 +800004b4: 23 2e f1 00 sw a5, 28(sp) +800004b8: 17 07 00 00 auipc a4, 0 +800004bc: 13 07 c7 ed addi a4, a4, -292 +800004c0: 6b 90 e7 00 vx_wspawn a5, a4 +800004c4: 93 07 f0 ff addi a5, zero, -1 +800004c8: 6b 80 07 00 vx_tmc a5 +800004cc: ef f0 9f de jal -536 +800004d0: f3 27 30 cc csrr a5, 3267 +800004d4: 93 b7 17 00 seqz a5, a5 +800004d8: 6b 80 07 00 vx_tmc a5 +800004dc: e3 0e 04 f8 beqz s0, -100 +800004e0: 33 09 99 02 +800004e4: 93 04 10 00 addi s1, zero, 1 +800004e8: 33 98 84 00 sll a6, s1, s0 +800004ec: 13 08 f8 ff addi a6, a6, -1 +800004f0: 23 28 21 01 sw s2, 16(sp) +800004f4: 6b 00 08 00 vx_tmc a6 +800004f8: ef f0 df e6 jal -404 +800004fc: 6b 80 04 00 vx_tmc s1 +80000500: 83 20 c1 02 lw ra, 44(sp) +80000504: 03 24 81 02 lw s0, 40(sp) +80000508: 83 24 41 02 lw s1, 36(sp) +8000050c: 03 29 01 02 lw s2, 32(sp) +80000510: 13 01 01 03 addi sp, sp, 48 +80000514: 67 80 00 00 ret + +80000518 vx_perf_dump: +80000518: f3 27 50 cc csrr a5, 3269 +8000051c: 37 07 ff 00 lui a4, 4080 +80000520: b3 87 e7 00 add a5, a5, a4 +80000524: 93 97 87 00 slli a5, a5, 8 +80000528: 73 27 00 b0 csrr a4, mcycle +8000052c: 23 a0 e7 00 sw a4, 0(a5) +80000530: 73 27 10 b0 csrr a4, 2817 +80000534: 23 a2 e7 00 sw a4, 4(a5) +80000538: 73 27 20 b0 csrr a4, minstret +8000053c: 23 a4 e7 00 sw a4, 8(a5) +80000540: 73 27 30 b0 csrr a4, mhpmcounter3 +80000544: 23 a6 e7 00 sw a4, 12(a5) +80000548: 73 27 40 b0 csrr a4, mhpmcounter4 +8000054c: 23 a8 e7 00 sw a4, 16(a5) +80000550: 73 27 50 b0 csrr a4, mhpmcounter5 +80000554: 23 aa e7 00 sw a4, 20(a5) +80000558: 73 27 60 b0 csrr a4, mhpmcounter6 +8000055c: 23 ac e7 00 sw a4, 24(a5) +80000560: 73 27 70 b0 csrr a4, mhpmcounter7 +80000564: 23 ae e7 00 sw a4, 28(a5) +80000568: 73 27 80 b0 csrr a4, mhpmcounter8 +8000056c: 23 a0 e7 02 sw a4, 32(a5) +80000570: 73 27 90 b0 csrr a4, mhpmcounter9 +80000574: 23 a2 e7 02 sw a4, 36(a5) +80000578: 73 27 a0 b0 csrr a4, mhpmcounter10 +8000057c: 23 a4 e7 02 sw a4, 40(a5) +80000580: 73 27 b0 b0 csrr a4, mhpmcounter11 +80000584: 23 a6 e7 02 sw a4, 44(a5) +80000588: 73 27 c0 b0 csrr a4, mhpmcounter12 +8000058c: 23 a8 e7 02 sw a4, 48(a5) +80000590: 73 27 d0 b0 csrr a4, mhpmcounter13 +80000594: 23 aa e7 02 sw a4, 52(a5) +80000598: 73 27 e0 b0 csrr a4, mhpmcounter14 +8000059c: 23 ac e7 02 sw a4, 56(a5) +800005a0: 73 27 f0 b0 csrr a4, mhpmcounter15 +800005a4: 23 ae e7 02 sw a4, 60(a5) +800005a8: 73 27 00 b1 csrr a4, mhpmcounter16 +800005ac: 23 a0 e7 04 sw a4, 64(a5) +800005b0: 73 27 10 b1 csrr a4, mhpmcounter17 +800005b4: 23 a2 e7 04 sw a4, 68(a5) +800005b8: 73 27 20 b1 csrr a4, mhpmcounter18 +800005bc: 23 a4 e7 04 sw a4, 72(a5) +800005c0: 73 27 30 b1 csrr a4, mhpmcounter19 +800005c4: 23 a6 e7 04 sw a4, 76(a5) +800005c8: 73 27 40 b1 csrr a4, mhpmcounter20 +800005cc: 23 a8 e7 04 sw a4, 80(a5) +800005d0: 73 27 50 b1 csrr a4, mhpmcounter21 +800005d4: 23 aa e7 04 sw a4, 84(a5) +800005d8: 73 27 60 b1 csrr a4, mhpmcounter22 +800005dc: 23 ac e7 04 sw a4, 88(a5) +800005e0: 73 27 70 b1 csrr a4, mhpmcounter23 +800005e4: 23 ae e7 04 sw a4, 92(a5) +800005e8: 73 27 80 b1 csrr a4, mhpmcounter24 +800005ec: 23 a0 e7 06 sw a4, 96(a5) +800005f0: 73 27 90 b1 csrr a4, mhpmcounter25 +800005f4: 23 a2 e7 06 sw a4, 100(a5) +800005f8: 73 27 a0 b1 csrr a4, mhpmcounter26 +800005fc: 23 a4 e7 06 sw a4, 104(a5) +80000600: 73 27 b0 b1 csrr a4, mhpmcounter27 +80000604: 23 a6 e7 06 sw a4, 108(a5) +80000608: 73 27 c0 b1 csrr a4, mhpmcounter28 +8000060c: 23 a8 e7 06 sw a4, 112(a5) +80000610: 73 27 d0 b1 csrr a4, mhpmcounter29 +80000614: 23 aa e7 06 sw a4, 116(a5) +80000618: 73 27 e0 b1 csrr a4, mhpmcounter30 +8000061c: 23 ac e7 06 sw a4, 120(a5) +80000620: 73 27 f0 b1 csrr a4, mhpmcounter31 +80000624: 23 ae e7 06 sw a4, 124(a5) +80000628: 73 27 00 b8 csrr a4, mcycleh +8000062c: 23 a0 e7 08 sw a4, 128(a5) +80000630: 73 27 10 b8 csrr a4, 2945 +80000634: 23 a2 e7 08 sw a4, 132(a5) +80000638: 73 27 20 b8 csrr a4, minstreth +8000063c: 23 a4 e7 08 sw a4, 136(a5) +80000640: 73 27 30 b8 csrr a4, mhpmcounter3h +80000644: 23 a6 e7 08 sw a4, 140(a5) +80000648: 73 27 40 b8 csrr a4, mhpmcounter4h +8000064c: 23 a8 e7 08 sw a4, 144(a5) +80000650: 73 27 50 b8 csrr a4, mhpmcounter5h +80000654: 23 aa e7 08 sw a4, 148(a5) +80000658: 73 27 60 b8 csrr a4, mhpmcounter6h +8000065c: 23 ac e7 08 sw a4, 152(a5) +80000660: 73 27 70 b8 csrr a4, mhpmcounter7h +80000664: 23 ae e7 08 sw a4, 156(a5) +80000668: 73 27 80 b8 csrr a4, mhpmcounter8h +8000066c: 23 a0 e7 0a sw a4, 160(a5) +80000670: 73 27 90 b8 csrr a4, mhpmcounter9h +80000674: 23 a2 e7 0a sw a4, 164(a5) +80000678: 73 27 a0 b8 csrr a4, mhpmcounter10h +8000067c: 23 a4 e7 0a sw a4, 168(a5) +80000680: 73 27 b0 b8 csrr a4, mhpmcounter11h +80000684: 23 a6 e7 0a sw a4, 172(a5) +80000688: 73 27 c0 b8 csrr a4, mhpmcounter12h +8000068c: 23 a8 e7 0a sw a4, 176(a5) +80000690: 73 27 d0 b8 csrr a4, mhpmcounter13h +80000694: 23 aa e7 0a sw a4, 180(a5) +80000698: 73 27 e0 b8 csrr a4, mhpmcounter14h +8000069c: 23 ac e7 0a sw a4, 184(a5) +800006a0: 73 27 f0 b8 csrr a4, mhpmcounter15h +800006a4: 23 ae e7 0a sw a4, 188(a5) +800006a8: 73 27 00 b9 csrr a4, mhpmcounter16h +800006ac: 23 a0 e7 0c sw a4, 192(a5) +800006b0: 73 27 10 b9 csrr a4, mhpmcounter17h +800006b4: 23 a2 e7 0c sw a4, 196(a5) +800006b8: 73 27 20 b9 csrr a4, mhpmcounter18h +800006bc: 23 a4 e7 0c sw a4, 200(a5) +800006c0: 73 27 30 b9 csrr a4, mhpmcounter19h +800006c4: 23 a6 e7 0c sw a4, 204(a5) +800006c8: 73 27 40 b9 csrr a4, mhpmcounter20h +800006cc: 23 a8 e7 0c sw a4, 208(a5) +800006d0: 73 27 50 b9 csrr a4, mhpmcounter21h +800006d4: 23 aa e7 0c sw a4, 212(a5) +800006d8: 73 27 60 b9 csrr a4, mhpmcounter22h +800006dc: 23 ac e7 0c sw a4, 216(a5) +800006e0: 73 27 70 b9 csrr a4, mhpmcounter23h +800006e4: 23 ae e7 0c sw a4, 220(a5) +800006e8: 73 27 80 b9 csrr a4, mhpmcounter24h +800006ec: 23 a0 e7 0e sw a4, 224(a5) +800006f0: 73 27 90 b9 csrr a4, mhpmcounter25h +800006f4: 23 a2 e7 0e sw a4, 228(a5) +800006f8: 73 27 a0 b9 csrr a4, mhpmcounter26h +800006fc: 23 a4 e7 0e sw a4, 232(a5) +80000700: 73 27 b0 b9 csrr a4, mhpmcounter27h +80000704: 23 a6 e7 0e sw a4, 236(a5) +80000708: 73 27 c0 b9 csrr a4, mhpmcounter28h +8000070c: 23 a8 e7 0e sw a4, 240(a5) +80000710: 73 27 d0 b9 csrr a4, mhpmcounter29h +80000714: 23 aa e7 0e sw a4, 244(a5) +80000718: 73 27 e0 b9 csrr a4, mhpmcounter30h +8000071c: 23 ac e7 0e sw a4, 248(a5) +80000720: 73 27 f0 b9 csrr a4, mhpmcounter31h +80000724: 23 ae e7 0e sw a4, 252(a5) +80000728: 67 80 00 00 ret + +8000072c atexit: +8000072c: 93 05 05 00 mv a1, a0 +80000730: 93 06 00 00 mv a3, zero +80000734: 13 06 00 00 mv a2, zero +80000738: 13 05 00 00 mv a0, zero +8000073c: 6f 00 40 28 j 644 + +80000740 memcpy: +80000740: b3 47 b5 00 xor a5, a0, a1 +80000744: 93 f7 37 00 andi a5, a5, 3 +80000748: b3 08 c5 00 add a7, a0, a2 +8000074c: 63 94 07 06 bnez a5, 104 +80000750: 93 07 30 00 addi a5, zero, 3 +80000754: 63 f0 c7 06 bgeu a5, a2, 96 +80000758: 93 77 35 00 andi a5, a0, 3 +8000075c: 13 07 05 00 mv a4, a0 +80000760: 63 9a 07 06 bnez a5, 116 +80000764: 13 f6 c8 ff andi a2, a7, -4 +80000768: b3 06 e6 40 sub a3, a2, a4 +8000076c: 93 07 00 02 addi a5, zero, 32 +80000770: 63 ce d7 08 blt a5, a3, 156 +80000774: 93 86 05 00 mv a3, a1 +80000778: 93 07 07 00 mv a5, a4 +8000077c: 63 78 c7 02 bgeu a4, a2, 48 +80000780: 03 a8 06 00 lw a6, 0(a3) +80000784: 93 87 47 00 addi a5, a5, 4 +80000788: 93 86 46 00 addi a3, a3, 4 +8000078c: 23 ae 07 ff sw a6, -4(a5) +80000790: e3 e8 c7 fe bltu a5, a2, -16 +80000794: 93 07 f6 ff addi a5, a2, -1 +80000798: b3 87 e7 40 sub a5, a5, a4 +8000079c: 93 f7 c7 ff andi a5, a5, -4 +800007a0: 93 87 47 00 addi a5, a5, 4 +800007a4: 33 07 f7 00 add a4, a4, a5 +800007a8: b3 85 f5 00 add a1, a1, a5 +800007ac: 63 68 17 01 bltu a4, a7, 16 +800007b0: 67 80 00 00 ret +800007b4: 13 07 05 00 mv a4, a0 +800007b8: 63 78 15 05 bgeu a0, a7, 80 +800007bc: 83 c7 05 00 lbu a5, 0(a1) +800007c0: 13 07 17 00 addi a4, a4, 1 +800007c4: 93 85 15 00 addi a1, a1, 1 +800007c8: a3 0f f7 fe sb a5, -1(a4) +800007cc: e3 98 e8 fe bne a7, a4, -16 +800007d0: 67 80 00 00 ret +800007d4: 83 c6 05 00 lbu a3, 0(a1) +800007d8: 13 07 17 00 addi a4, a4, 1 +800007dc: 93 77 37 00 andi a5, a4, 3 +800007e0: a3 0f d7 fe sb a3, -1(a4) +800007e4: 93 85 15 00 addi a1, a1, 1 +800007e8: e3 8e 07 f6 beqz a5, -132 +800007ec: 83 c6 05 00 lbu a3, 0(a1) +800007f0: 13 07 17 00 addi a4, a4, 1 +800007f4: 93 77 37 00 andi a5, a4, 3 +800007f8: a3 0f d7 fe sb a3, -1(a4) +800007fc: 93 85 15 00 addi a1, a1, 1 +80000800: e3 9a 07 fc bnez a5, -44 +80000804: 6f f0 1f f6 j -160 +80000808: 67 80 00 00 ret +8000080c: 13 01 01 ff addi sp, sp, -16 +80000810: 23 26 81 00 sw s0, 12(sp) +80000814: 13 04 00 02 addi s0, zero, 32 +80000818: 83 a3 05 00 lw t2, 0(a1) +8000081c: 83 a2 45 00 lw t0, 4(a1) +80000820: 83 af 85 00 lw t6, 8(a1) +80000824: 03 af c5 00 lw t5, 12(a1) +80000828: 83 ae 05 01 lw t4, 16(a1) +8000082c: 03 ae 45 01 lw t3, 20(a1) +80000830: 03 a3 85 01 lw t1, 24(a1) +80000834: 03 a8 c5 01 lw a6, 28(a1) +80000838: 83 a6 05 02 lw a3, 32(a1) +8000083c: 13 07 47 02 addi a4, a4, 36 +80000840: b3 07 e6 40 sub a5, a2, a4 +80000844: 23 2e 77 fc sw t2, -36(a4) +80000848: 23 20 57 fe sw t0, -32(a4) +8000084c: 23 22 f7 ff sw t6, -28(a4) +80000850: 23 24 e7 ff sw t5, -24(a4) +80000854: 23 26 d7 ff sw t4, -20(a4) +80000858: 23 28 c7 ff sw t3, -16(a4) +8000085c: 23 2a 67 fe sw t1, -12(a4) +80000860: 23 2c 07 ff sw a6, -8(a4) +80000864: 23 2e d7 fe sw a3, -4(a4) +80000868: 93 85 45 02 addi a1, a1, 36 +8000086c: e3 46 f4 fa blt s0, a5, -84 +80000870: 93 86 05 00 mv a3, a1 +80000874: 93 07 07 00 mv a5, a4 +80000878: 63 78 c7 02 bgeu a4, a2, 48 +8000087c: 03 a8 06 00 lw a6, 0(a3) +80000880: 93 87 47 00 addi a5, a5, 4 +80000884: 93 86 46 00 addi a3, a3, 4 +80000888: 23 ae 07 ff sw a6, -4(a5) +8000088c: e3 e8 c7 fe bltu a5, a2, -16 +80000890: 93 07 f6 ff addi a5, a2, -1 +80000894: b3 87 e7 40 sub a5, a5, a4 +80000898: 93 f7 c7 ff andi a5, a5, -4 +8000089c: 93 87 47 00 addi a5, a5, 4 +800008a0: 33 07 f7 00 add a4, a4, a5 +800008a4: b3 85 f5 00 add a1, a1, a5 +800008a8: 63 68 17 01 bltu a4, a7, 16 +800008ac: 03 24 c1 00 lw s0, 12(sp) +800008b0: 13 01 01 01 addi sp, sp, 16 +800008b4: 67 80 00 00 ret +800008b8: 83 c7 05 00 lbu a5, 0(a1) +800008bc: 13 07 17 00 addi a4, a4, 1 +800008c0: 93 85 15 00 addi a1, a1, 1 +800008c4: a3 0f f7 fe sb a5, -1(a4) +800008c8: e3 82 e8 fe beq a7, a4, -28 +800008cc: 83 c7 05 00 lbu a5, 0(a1) +800008d0: 13 07 17 00 addi a4, a4, 1 +800008d4: 93 85 15 00 addi a1, a1, 1 +800008d8: a3 0f f7 fe sb a5, -1(a4) +800008dc: e3 9e e8 fc bne a7, a4, -36 +800008e0: 6f f0 df fc j -52 + +800008e4 memset: +800008e4: 13 03 f0 00 addi t1, zero, 15 +800008e8: 13 07 05 00 mv a4, a0 +800008ec: 63 7e c3 02 bgeu t1, a2, 60 +800008f0: 93 77 f7 00 andi a5, a4, 15 +800008f4: 63 90 07 0a bnez a5, 160 +800008f8: 63 92 05 08 bnez a1, 132 +800008fc: 93 76 06 ff andi a3, a2, -16 +80000900: 13 76 f6 00 andi a2, a2, 15 +80000904: b3 86 e6 00 add a3, a3, a4 +80000908: 23 20 b7 00 sw a1, 0(a4) +8000090c: 23 22 b7 00 sw a1, 4(a4) +80000910: 23 24 b7 00 sw a1, 8(a4) +80000914: 23 26 b7 00 sw a1, 12(a4) +80000918: 13 07 07 01 addi a4, a4, 16 +8000091c: e3 66 d7 fe bltu a4, a3, -20 +80000920: 63 14 06 00 bnez a2, 8 +80000924: 67 80 00 00 ret +80000928: b3 06 c3 40 sub a3, t1, a2 +8000092c: 93 96 26 00 slli a3, a3, 2 +80000930: 97 02 00 00 auipc t0, 0 +80000934: b3 86 56 00 add a3, a3, t0 +80000938: 67 80 c6 00 jr 12(a3) +8000093c: 23 07 b7 00 sb a1, 14(a4) +80000940: a3 06 b7 00 sb a1, 13(a4) +80000944: 23 06 b7 00 sb a1, 12(a4) +80000948: a3 05 b7 00 sb a1, 11(a4) +8000094c: 23 05 b7 00 sb a1, 10(a4) +80000950: a3 04 b7 00 sb a1, 9(a4) +80000954: 23 04 b7 00 sb a1, 8(a4) +80000958: a3 03 b7 00 sb a1, 7(a4) +8000095c: 23 03 b7 00 sb a1, 6(a4) +80000960: a3 02 b7 00 sb a1, 5(a4) +80000964: 23 02 b7 00 sb a1, 4(a4) +80000968: a3 01 b7 00 sb a1, 3(a4) +8000096c: 23 01 b7 00 sb a1, 2(a4) +80000970: a3 00 b7 00 sb a1, 1(a4) +80000974: 23 00 b7 00 sb a1, 0(a4) +80000978: 67 80 00 00 ret +8000097c: 93 f5 f5 0f andi a1, a1, 255 +80000980: 93 96 85 00 slli a3, a1, 8 +80000984: b3 e5 d5 00 or a1, a1, a3 +80000988: 93 96 05 01 slli a3, a1, 16 +8000098c: b3 e5 d5 00 or a1, a1, a3 +80000990: 6f f0 df f6 j -148 +80000994: 93 96 27 00 slli a3, a5, 2 +80000998: 97 02 00 00 auipc t0, 0 +8000099c: b3 86 56 00 add a3, a3, t0 +800009a0: 93 82 00 00 mv t0, ra +800009a4: e7 80 06 fa jalr -96(a3) +800009a8: 93 80 02 00 mv ra, t0 +800009ac: 93 87 07 ff addi a5, a5, -16 +800009b0: 33 07 f7 40 sub a4, a4, a5 +800009b4: 33 06 f6 00 add a2, a2, a5 +800009b8: e3 78 c3 f6 bgeu t1, a2, -144 +800009bc: 6f f0 df f3 j -196 + +800009c0 __register_exitproc: +800009c0: 17 17 00 00 auipc a4, 1 +800009c4: 03 27 07 a7 lw a4, -1424(a4) +800009c8: 83 27 87 14 lw a5, 328(a4) +800009cc: 63 8c 07 04 beqz a5, 88 +800009d0: 03 a7 47 00 lw a4, 4(a5) +800009d4: 13 08 f0 01 addi a6, zero, 31 +800009d8: 63 4e e8 06 blt a6, a4, 124 +800009dc: 13 18 27 00 slli a6, a4, 2 +800009e0: 63 06 05 02 beqz a0, 44 +800009e4: 33 83 07 01 add t1, a5, a6 +800009e8: 23 24 c3 08 sw a2, 136(t1) +800009ec: 83 a8 87 18 lw a7, 392(a5) +800009f0: 13 06 10 00 addi a2, zero, 1 +800009f4: 33 16 e6 00 sll a2, a2, a4 +800009f8: b3 e8 c8 00 or a7, a7, a2 +800009fc: 23 a4 17 19 sw a7, 392(a5) +80000a00: 23 24 d3 10 sw a3, 264(t1) +80000a04: 93 06 20 00 addi a3, zero, 2 +80000a08: 63 04 d5 02 beq a0, a3, 40 +80000a0c: 13 07 17 00 addi a4, a4, 1 +80000a10: 23 a2 e7 00 sw a4, 4(a5) +80000a14: b3 87 07 01 add a5, a5, a6 +80000a18: 23 a4 b7 00 sw a1, 8(a5) +80000a1c: 13 05 00 00 mv a0, zero +80000a20: 67 80 00 00 ret +80000a24: 93 07 c7 14 addi a5, a4, 332 +80000a28: 23 24 f7 14 sw a5, 328(a4) +80000a2c: 6f f0 5f fa j -92 +80000a30: 83 a6 c7 18 lw a3, 396(a5) +80000a34: 13 07 17 00 addi a4, a4, 1 +80000a38: 23 a2 e7 00 sw a4, 4(a5) +80000a3c: b3 e6 c6 00 or a3, a3, a2 +80000a40: 23 a6 d7 18 sw a3, 396(a5) +80000a44: b3 87 07 01 add a5, a5, a6 +80000a48: 23 a4 b7 00 sw a1, 8(a5) +80000a4c: 13 05 00 00 mv a0, zero +80000a50: 67 80 00 00 ret +80000a54: 13 05 f0 ff addi a0, zero, -1 +80000a58: 67 80 00 00 ret + +80000a5c __call_exitprocs: +80000a5c: 13 01 01 fd addi sp, sp, -48 +80000a60: 23 2c 41 01 sw s4, 24(sp) +80000a64: 17 1a 00 00 auipc s4, 1 +80000a68: 03 2a ca 9c lw s4, -1588(s4) +80000a6c: 23 20 21 03 sw s2, 32(sp) +80000a70: 03 29 8a 14 lw s2, 328(s4) +80000a74: 23 26 11 02 sw ra, 44(sp) +80000a78: 23 24 81 02 sw s0, 40(sp) +80000a7c: 23 22 91 02 sw s1, 36(sp) +80000a80: 23 2e 31 01 sw s3, 28(sp) +80000a84: 23 2a 51 01 sw s5, 20(sp) +80000a88: 23 28 61 01 sw s6, 16(sp) +80000a8c: 23 26 71 01 sw s7, 12(sp) +80000a90: 23 24 81 01 sw s8, 8(sp) +80000a94: 63 00 09 04 beqz s2, 64 +80000a98: 13 0b 05 00 mv s6, a0 +80000a9c: 93 8b 05 00 mv s7, a1 +80000aa0: 93 0a 10 00 addi s5, zero, 1 +80000aa4: 93 09 f0 ff addi s3, zero, -1 +80000aa8: 83 24 49 00 lw s1, 4(s2) +80000aac: 13 84 f4 ff addi s0, s1, -1 +80000ab0: 63 42 04 02 bltz s0, 36 +80000ab4: 93 94 24 00 slli s1, s1, 2 +80000ab8: b3 04 99 00 add s1, s2, s1 +80000abc: 63 84 0b 04 beqz s7, 72 +80000ac0: 83 a7 44 10 lw a5, 260(s1) +80000ac4: 63 80 77 05 beq a5, s7, 64 +80000ac8: 13 04 f4 ff addi s0, s0, -1 +80000acc: 93 84 c4 ff addi s1, s1, -4 +80000ad0: e3 16 34 ff bne s0, s3, -20 +80000ad4: 83 20 c1 02 lw ra, 44(sp) +80000ad8: 03 24 81 02 lw s0, 40(sp) +80000adc: 83 24 41 02 lw s1, 36(sp) +80000ae0: 03 29 01 02 lw s2, 32(sp) +80000ae4: 83 29 c1 01 lw s3, 28(sp) +80000ae8: 03 2a 81 01 lw s4, 24(sp) +80000aec: 83 2a 41 01 lw s5, 20(sp) +80000af0: 03 2b 01 01 lw s6, 16(sp) +80000af4: 83 2b c1 00 lw s7, 12(sp) +80000af8: 03 2c 81 00 lw s8, 8(sp) +80000afc: 13 01 01 03 addi sp, sp, 48 +80000b00: 67 80 00 00 ret +80000b04: 83 27 49 00 lw a5, 4(s2) +80000b08: 83 a6 44 00 lw a3, 4(s1) +80000b0c: 93 87 f7 ff addi a5, a5, -1 +80000b10: 63 8e 87 04 beq a5, s0, 92 +80000b14: 23 a2 04 00 sw zero, 4(s1) +80000b18: e3 88 06 fa beqz a3, -80 +80000b1c: 83 27 89 18 lw a5, 392(s2) +80000b20: 33 97 8a 00 sll a4, s5, s0 +80000b24: 03 2c 49 00 lw s8, 4(s2) +80000b28: b3 77 f7 00 and a5, a4, a5 +80000b2c: 63 92 07 02 bnez a5, 36 +80000b30: e7 80 06 00 jalr a3 +80000b34: 03 27 49 00 lw a4, 4(s2) +80000b38: 83 27 8a 14 lw a5, 328(s4) +80000b3c: 63 14 87 01 bne a4, s8, 8 +80000b40: e3 84 27 f9 beq a5, s2, -120 +80000b44: e3 88 07 f8 beqz a5, -112 +80000b48: 13 89 07 00 mv s2, a5 +80000b4c: 6f f0 df f5 j -164 +80000b50: 83 27 c9 18 lw a5, 396(s2) +80000b54: 83 a5 44 08 lw a1, 132(s1) +80000b58: 33 77 f7 00 and a4, a4, a5 +80000b5c: 63 1c 07 00 bnez a4, 24 +80000b60: 13 05 0b 00 mv a0, s6 +80000b64: e7 80 06 00 jalr a3 +80000b68: 6f f0 df fc j -52 +80000b6c: 23 22 89 00 sw s0, 4(s2) +80000b70: 6f f0 9f fa j -88 +80000b74: 13 85 05 00 mv a0, a1 +80000b78: e7 80 06 00 jalr a3 +80000b7c: 6f f0 9f fb j -72 + +Disassembly of section .init_array: + +80001000 __tdata_start: +80001000: bc 00 +80001002: 00 80 + +Disassembly of section .data: + +80001008 impure_data: +80001008: 00 00 +8000100a: 00 00 +8000100c: f4 12 +8000100e: 00 80 +80001010: 5c 13 +80001012: 00 80 +80001014: c4 13 +80001016: 00 80 + ... +800010b0: 01 00 +800010b2: 00 00 +800010b4: 00 00 +800010b6: 00 00 +800010b8: 0e 33 +800010ba: cd ab +800010bc: 34 12 +800010be: 6d e6 +800010c0: ec de +800010c2: 05 00 +800010c4: 0b 00 00 00 + ... + +Disassembly of section .sdata: + +80001430 _global_impure_ptr: +80001430: 08 10 +80001432: 00 80 + +Disassembly of section .bss: + +80001434 g_wspawn_args: +... + +Disassembly of section .comment: + +00000000 .comment: + 0: 47 43 43 3a + 4: 20 28 + 6: 67 32 65 65 + a: 35 65 + c: 34 33 + e: 30 30 + 10: 31 38 + 12: 2d 64 + 14: 69 72 + 16: 74 79 + 18: 29 20 + 1a: 31 32 + 1c: 2e 32 + 1e: 2e 30 + 20: 00 47 + 22: 43 43 3a 20 + 26: 28 47 + 28: 4e 55 + 2a: 29 20 + 2c: 31 32 + 2e: 2e 32 + 30: 2e 30 + 32: 00 + +Disassembly of section .riscv.attributes: + +00000000 .riscv.attributes: + 0: 41 3b + 2: 00 00 + 4: 00 72 + 6: 69 73 + 8: 63 76 00 01 bgeu zero, a6, 12 + c: 31 00 + e: 00 00 + 10: 04 10 + 12: 05 72 + 14: 76 33 + 16: 32 69 + 18: 32 70 + 1a: 31 5f + 1c: 6d 32 + 1e: 70 30 + 20: 5f 66 32 70 + 24: 32 5f + 26: 7a 69 + 28: 63 73 72 32 bgeu tp, t2, 806 + 2c: 70 30 + 2e: 5f 7a 6d 6d + 32: 75 6c + 34: 31 70 + 36: 30 00 + 38: 08 01 + 3a: 0a 0b + +Disassembly of section .symtab: + +00000000 .symtab: + ... + 14: 00 00 + 16: 00 80 + 18: 00 00 + 1a: 00 00 + 1c: 03 00 01 00 lb zero, 0(sp) + 20: 00 00 + 22: 00 00 + 24: 6c 00 + 26: 00 80 + 28: 00 00 + 2a: 00 00 + 2c: 03 00 02 00 lb zero, 0(tp) + 30: 00 00 + 32: 00 00 + 34: 00 10 + 36: 00 80 + 38: 00 00 + 3a: 00 00 + 3c: 03 00 03 00 lb zero, 0(t1) + 40: 00 00 + 42: 00 00 + 44: 08 10 + 46: 00 80 + 48: 00 00 + 4a: 00 00 + 4c: 03 00 04 00 lb zero, 0(s0) + 50: 00 00 + 52: 00 00 + 54: 30 14 + 56: 00 80 + 58: 00 00 + 5a: 00 00 + 5c: 03 00 05 00 lb zero, 0(a0) + 60: 00 00 + 62: 00 00 + 64: 34 14 + 66: 00 80 + 68: 00 00 + 6a: 00 00 + 6c: 03 00 06 00 lb zero, 0(a2) + ... + 7c: 03 00 07 00 lb zero, 0(a4) + ... + 8c: 03 00 08 00 lb zero, 0(a6) + 90: 01 00 + ... + 9a: 00 00 + 9c: 04 00 + 9e: f1 ff + a0: 0e 00 + a2: 00 00 + a4: 00 00 + a6: 00 80 + a8: 00 00 + aa: 00 00 + ac: 00 00 + ae: 01 00 + b0: 0e 00 + b2: 00 00 + b4: 08 01 + b6: 00 80 + b8: 00 00 + ba: 00 00 + bc: 00 00 + be: 02 00 + c0: 35 00 + c2: 00 00 + c4: 64 01 + c6: 00 80 + c8: 00 00 + ca: 00 00 + cc: 00 00 + ce: 02 00 + d0: df 00 00 00 + ... + dc: 04 00 + de: f1 ff + e0: 0e 00 + e2: 00 00 + e4: 6c 00 + e6: 00 80 + e8: 00 00 + ea: 00 00 + ec: 00 00 + ee: 02 00 + f0: 3c 00 + ... + fa: 00 00 + fc: 04 00 + fe: f1 ff + 100: 0e 00 + 102: 00 00 + 104: d4 00 + 106: 00 80 + 108: 00 00 + 10a: 00 00 + 10c: 00 00 + 10e: 02 00 + 110: 0e 00 + 112: 00 00 + 114: a0 00 + 116: 00 80 + 118: 00 00 + 11a: 00 00 + 11c: 00 00 + 11e: 02 00 + 120: 45 00 + ... + 12a: 00 00 + 12c: 04 00 + 12e: f1 ff + 130: 55 00 + 132: 00 00 + 134: bc 00 + 136: 00 80 + 138: 18 00 + 13a: 00 00 + 13c: 02 00 + 13e: 02 00 + 140: 0e 00 + 142: 00 00 + 144: bc 00 + 146: 00 80 + 148: 00 00 + 14a: 00 00 + 14c: 00 00 + 14e: 02 00 + 150: 0e 00 + 152: 00 00 + 154: 5c 0a + 156: 00 80 + 158: 00 00 + 15a: 00 00 + 15c: 00 00 + 15e: 02 00 + 160: 63 00 00 00 beqz zero, 0 + ... + 16c: 04 00 + 16e: f1 ff + 170: 0e 00 + 172: 00 00 + 174: 68 01 + 176: 00 80 + 178: 00 00 + 17a: 00 00 + 17c: 00 00 + 17e: 02 00 + 180: 0e 00 + 182: 00 00 + 184: c4 01 + 186: 00 80 + 188: 00 00 + 18a: 00 00 + 18c: 00 00 + 18e: 02 00 + 190: 0e 00 + 192: 00 00 + 194: 58 02 + 196: 00 80 + 198: 00 00 + 19a: 00 00 + 19c: 00 00 + 19e: 02 00 + 1a0: 71 00 + ... + 1aa: 00 00 + 1ac: 04 00 + 1ae: f1 ff + 1b0: 7c 00 + 1b2: 00 00 + 1b4: b4 02 + 1b6: 00 80 + 1b8: b0 00 + 1ba: 00 00 + 1bc: 02 00 + 1be: 02 00 + 1c0: 0e 00 + 1c2: 00 00 + 1c4: b4 02 + 1c6: 00 80 + 1c8: 00 00 + 1ca: 00 00 + 1cc: 00 00 + 1ce: 02 00 + 1d0: 91 00 + 1d2: 00 00 + 1d4: 64 03 + 1d6: 00 80 + 1d8: 30 00 + 1da: 00 00 + 1dc: 02 00 + 1de: 02 00 + 1e0: 0e 00 + 1e2: 00 00 + 1e4: 64 03 + 1e6: 00 80 + 1e8: 00 00 + 1ea: 00 00 + 1ec: 00 00 + 1ee: 02 00 + 1f0: a6 00 + 1f2: 00 00 + 1f4: 94 03 + 1f6: 00 80 + 1f8: 2c 00 + 1fa: 00 00 + 1fc: 02 00 + 1fe: 02 00 + 200: 0e 00 + 202: 00 00 + 204: 94 03 + 206: 00 80 + 208: 00 00 + 20a: 00 00 + 20c: 00 00 + 20e: 02 00 + 210: 0e 00 + 212: 00 00 + 214: c0 03 + 216: 00 80 + 218: 00 00 + 21a: 00 00 + 21c: 00 00 + 21e: 02 00 + 220: b9 00 + ... + 22a: 00 00 + 22c: 04 00 + 22e: f1 ff + 230: 0e 00 + 232: 00 00 + 234: 18 05 + 236: 00 80 + 238: 00 00 + 23a: 00 00 + 23c: 00 00 + 23e: 02 00 + 240: dd 00 + ... + 24a: 00 00 + 24c: 04 00 + 24e: f1 ff + 250: 0e 00 + 252: 00 00 + 254: 2c 07 + 256: 00 80 + 258: 00 00 + 25a: 00 00 + 25c: 00 00 + 25e: 02 00 + 260: c3 00 00 00 + ... + 26c: 04 00 + 26e: f1 ff + 270: 0e 00 + 272: 00 00 + 274: 40 07 + 276: 00 80 + 278: 00 00 + 27a: 00 00 + 27c: 00 00 + 27e: 02 00 + 280: cc 00 + ... + 28a: 00 00 + 28c: 04 00 + 28e: f1 ff + 290: 0e 00 + 292: 00 00 + 294: e4 08 + 296: 00 80 + 298: 00 00 + 29a: 00 00 + 29c: 00 00 + 29e: 02 00 + 2a0: db 00 00 00 + ... + 2ac: 04 00 + 2ae: f1 ff + 2b0: 0e 00 + 2b2: 00 00 + 2b4: c0 09 + 2b6: 00 80 + 2b8: 00 00 + 2ba: 00 00 + 2bc: 00 00 + 2be: 02 00 + 2c0: e6 00 + ... + 2ca: 00 00 + 2cc: 04 00 + 2ce: f1 ff + 2d0: ef 00 00 00 jal 0 + 2d4: 08 10 + 2d6: 00 80 + 2d8: 28 04 + 2da: 00 00 + 2dc: 01 00 + 2de: 04 00 + ... + 2ec: 04 00 + 2ee: f1 ff + 2f0: fb 00 00 00 + 2f4: 04 10 + 2f6: 00 80 + 2f8: 00 00 + 2fa: 00 00 + 2fc: 00 00 + 2fe: 03 00 0c 01 lb zero, 16(s8) + 302: 00 00 + 304: 00 10 + 306: 00 80 + 308: 00 00 + 30a: 00 00 + 30c: 00 00 + 30e: 03 00 19 01 lb zero, 17(s2) + 312: 00 00 + 314: 04 10 + 316: 00 80 + 318: 00 00 + 31a: 00 00 + 31c: 00 00 + 31e: 03 00 2c 01 lb zero, 18(s8) + 322: 00 00 + 324: 00 10 + 326: 00 80 + 328: 00 00 + 32a: 00 00 + 32c: 00 00 + 32e: 03 00 3a 01 lb zero, 19(s4) + 332: 00 00 + 334: 04 10 + 336: 00 80 + 338: 00 00 + 33a: 00 00 + 33c: 00 00 + 33e: 03 00 4b 01 lb zero, 20(s6) + ... + 34e: f1 ff + 350: 59 01 + 352: 00 00 + 354: 00 10 + 356: 00 80 + 358: 00 00 + 35a: 00 00 + 35c: 00 00 + 35e: 03 00 6d 01 lb zero, 22(s10) + 362: 00 00 + 364: 00 10 + 366: 00 80 + 368: 00 00 + 36a: 00 00 + 36c: 00 00 + 36e: 03 00 78 01 lb zero, 23(a6) + 372: 00 00 + 374: 00 10 + 376: 00 80 + 378: 00 00 + 37a: 00 00 + 37c: 00 00 + 37e: 03 00 8b 01 lb zero, 24(s6) + 382: 00 00 + 384: 00 10 + 386: 00 80 + 388: 00 00 + 38a: 00 00 + 38c: 00 00 + 38e: 03 00 a1 01 lb zero, 26(sp) + 392: 00 00 + 394: c0 03 + 396: 00 80 + 398: 58 01 + 39a: 00 00 + 39c: 12 00 + 39e: 02 00 + 3a0: b0 01 + ... + 3aa: 00 00 + 3ac: 10 00 + 3ae: f1 ff + 3b0: be 01 + 3b2: 00 00 + 3b4: 00 04 + 3b6: 00 00 + 3b8: 00 00 + 3ba: 00 00 + 3bc: 10 00 + 3be: f1 ff + 3c0: cb 01 00 00 + 3c4: 34 14 + 3c6: 00 80 + 3c8: 80 00 + 3ca: 00 00 + 3cc: 11 00 + 3ce: 06 00 + 3d0: d9 01 + 3d2: 00 00 + 3d4: 30 14 + 3d6: 00 80 + 3d8: 00 00 + 3da: 00 00 + 3dc: 10 00 + 3de: 05 00 + 3e0: e9 01 + 3e2: 00 00 + 3e4: 40 07 + 3e6: 00 80 + 3e8: a4 01 + 3ea: 00 00 + 3ec: 12 00 + 3ee: 02 00 + 3f0: f0 01 + 3f2: 00 00 + 3f4: 08 18 + 3f6: 00 80 + 3f8: 00 00 + 3fa: 00 00 + 3fc: 10 00 + 3fe: f1 ff + 400: 01 02 + 402: 00 00 + 404: 30 14 + 406: 00 80 + 408: 04 00 + 40a: 00 00 + 40c: 11 00 + 40e: 05 00 + 410: 14 02 + 412: 00 00 + 414: c4 01 + 416: 00 80 + 418: 94 00 + 41a: 00 00 + 41c: 12 00 + 41e: 02 00 + 420: 26 02 + 422: 00 00 + 424: 68 01 + 426: 00 80 + 428: 5c 00 + 42a: 00 00 + 42c: 12 00 + 42e: 02 00 + 430: 31 02 + 432: 00 00 + 434: 58 02 + 436: 00 80 + 438: 5c 00 + 43a: 00 00 + 43c: 12 00 + 43e: 02 00 + 440: 43 02 00 00 + ... + 44c: 10 00 + 44e: f1 ff + 450: 50 02 + ... + 45a: 00 00 + 45c: 10 00 + 45e: f1 ff + 460: 5c 02 + 462: 00 00 + 464: 5c 0a + 466: 00 80 + 468: 24 01 + 46a: 00 00 + 46c: 12 00 + 46e: 02 00 + 470: 33 01 00 00 add sp, zero, zero + 474: 00 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+uint32_t count = 0; + +std::vector src_data; +std::vector ref_data; + +vx_device_h device = nullptr; +vx_buffer_h staging_buf = nullptr; +kernel_arg_t kernel_arg; + +static void show_usage() { + std::cout << "Vortex Test." << std::endl; + std::cout << "Usage: [-k: kernel] [-n words] [-h: help]" << std::endl; +} + +static void parse_args(int argc, char **argv) { + int c; + while ((c = getopt(argc, argv, "n:k:h?")) != -1) { + switch (c) { + case 'n': + count = atoi(optarg); + break; + case 'k': + kernel_file = optarg; + break; + case 'h': + case '?': { + show_usage(); + exit(0); + } break; + default: + show_usage(); + exit(-1); + } + } +} + +void cleanup() { + if (staging_buf) { + vx_buf_free(staging_buf); + } + if (device) { + vx_mem_free(device, kernel_arg.src_addr); + vx_mem_free(device, kernel_arg.dst_addr); + vx_dev_close(device); + } +} + +void gen_input_data(uint32_t num_points) { + src_data.resize(num_points); + + for (uint32_t i = 0; i < src_data.size(); ++i) { + int value = std::rand() - (RAND_MAX / 2); + src_data[i] = value; + } +} + +void gen_ref_data(uint32_t num_points) { + ref_data.resize(num_points); + + for (uint32_t i = 0; i < num_points; ++i) { + int32_t ref_value = src_data.at(i); + ref_data.at(i) = std::max(0, ref_value); + } +} + +int run_test(const kernel_arg_t& kernel_arg, + uint32_t buf_size, + uint32_t num_points) { + // start device + std::cout << "start device" << std::endl; + RT_CHECK(vx_start(device)); + + // wait for completion + std::cout << "wait for completion" << std::endl; + RT_CHECK(vx_ready_wait(device, MAX_TIMEOUT)); + + // download destination buffer + std::cout << "download destination buffer" << std::endl; + RT_CHECK(vx_copy_from_dev(staging_buf, kernel_arg.dst_addr, buf_size, 0)); + + // verify result + std::cout << "verify result" << std::endl; + { + int errors = 0; + auto buf_ptr = (int32_t*)vx_host_ptr(staging_buf); + for (uint32_t i = 0; i < num_points; ++i) { + int ref = ref_data.at(i); + int cur = buf_ptr[i]; + if (cur != ref) { + std::cout << "error at result #" << std::dec << i + << std::hex << ": actual 0x" << cur << ", expected 0x" << ref << std::endl; + ++errors; + } + } + if (errors != 0) { + std::cout << "Found " << std::dec << errors << " errors!" << std::endl; + std::cout << "FAILED!" << std::endl; + return 1; + } + } + + return 0; +} + +int main(int argc, char *argv[]) { + size_t value; + + // parse command arguments + parse_args(argc, argv); + + if (count == 0) { + count = 1; + } + + std::srand(50); + + // open device connection + std::cout << "open device connection" << std::endl; + RT_CHECK(vx_dev_open(&device)); + + uint32_t num_points = 256; + + // generate input data + gen_input_data(num_points); + + // generate reference data + gen_ref_data(num_points); + + uint32_t src_buf_size = src_data.size() * sizeof(int32_t); + uint32_t dst_buf_size = ref_data.size() * sizeof(int32_t); + + std::cout << "number of points: " << num_points << std::endl; + std::cout << "buffer size: " << dst_buf_size << " bytes" << std::endl; + + // upload program + std::cout << "upload program" << std::endl; + RT_CHECK(vx_upload_kernel_file(device, kernel_file)); + + // allocate device memory + std::cout << "allocate device memory" << std::endl; + + RT_CHECK(vx_mem_alloc(device, src_buf_size, &value)); + kernel_arg.src_addr = value; + RT_CHECK(vx_mem_alloc(device, dst_buf_size, &value)); + kernel_arg.dst_addr = value; + + kernel_arg.num_points = num_points; + + std::cout << "dev_src=" << std::hex << kernel_arg.src_addr << std::endl; + std::cout << "dev_dst=" << std::hex << kernel_arg.dst_addr << std::endl; + + // allocate shared memory + std::cout << "allocate shared memory" << std::endl; + uint32_t staging_buf_size = std::max(src_buf_size, + std::max(dst_buf_size, + sizeof(kernel_arg_t))); + RT_CHECK(vx_buf_alloc(device, staging_buf_size, &staging_buf)); + + // upload kernel argument + std::cout << "upload kernel argument" << std::endl; + { + auto buf_ptr = (int*)vx_host_ptr(staging_buf); + memcpy(buf_ptr, &kernel_arg, sizeof(kernel_arg_t)); + RT_CHECK(vx_copy_to_dev(staging_buf, KERNEL_ARG_DEV_MEM_ADDR, sizeof(kernel_arg_t), 0)); + } + + // upload source buffer + { + auto buf_ptr = (int32_t*)vx_host_ptr(staging_buf); + for (uint32_t i = 0; i < num_points; ++i) { + buf_ptr[i] = src_data.at(i); + } + } + std::cout << "upload source buffer" << std::endl; + RT_CHECK(vx_copy_to_dev(staging_buf, kernel_arg.src_addr, src_buf_size, 0)); + + // clear destination buffer + { + auto buf_ptr = (int32_t*)vx_host_ptr(staging_buf); + for (uint32_t i = 0; i < num_points; ++i) { + buf_ptr[i] = 0xdeadbeef; + } + } + std::cout << "clear destination buffer" << std::endl; + RT_CHECK(vx_copy_to_dev(staging_buf, kernel_arg.dst_addr, dst_buf_size, 0)); + + // run tests + std::cout << "run tests" << std::endl; + RT_CHECK(run_test(kernel_arg, dst_buf_size, num_points)); + + // cleanup + std::cout << "cleanup" << std::endl; + cleanup(); + + std::cout << "PASSED!" << std::endl; + + return 0; +} \ No newline at end of file diff --git a/tests/regression/relu/ramulator.ddr4.log b/tests/regression/relu/ramulator.ddr4.log new file mode 100644 index 00000000..1825f82d --- /dev/null +++ b/tests/regression/relu/ramulator.ddr4.log @@ -0,0 +1,278 @@ + ramulator.active_cycles_0 1072 # Total active cycles for level _0 + ramulator.busy_cycles_0 1072 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 1496 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.130336 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 1072 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 1384 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 1496 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.130336 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 1030 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 1030 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 1440 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.125457 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 1030 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 1030 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 1440 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.125457 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 0 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 0 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 0 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 0 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 0 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 0 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 0 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 0 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 0 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 0 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 0 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 0 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 0 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 42 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 42 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 56 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.004879 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 0 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 0 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 0 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 42 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 42 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 56 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.004879 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 3712 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 16000 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 296 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 3 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 9 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 51 # Number of row hits for read requests per channel per core + [0] 51.0 # +ramulator.read_row_misses_channel_0_core 2 # Number of row misses for read requests per channel per core + [0] 2.0 # +ramulator.read_row_conflicts_channel_0_core 5 # Number of row conflicts for read requests per channel per core + [0] 5.0 # + ramulator.write_row_hits_channel_0_core 245 # Number of row hits for write requests per channel per core + [0] 245.0 # +ramulator.write_row_misses_channel_0_core 1 # Number of row misses for write requests per channel per core + [0] 1.0 # +ramulator.write_row_conflicts_channel_0_core 4 # Number of row conflicts for write requests per channel per core + [0] 4.0 # + ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 41.689655 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 2418 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 0.993466 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 11403 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.200906 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 2306 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 0.792560 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 9097 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.active_cycles_1 1071 # Total active cycles for level _1 + ramulator.busy_cycles_1 1071 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1 + ramulator.serving_requests_1 1472 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1 + ramulator.average_serving_requests_1 0.128245 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1 + ramulator.active_cycles_1_0 1071 # Total active cycles for level _1_0 + ramulator.busy_cycles_1_0 1383 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0 + ramulator.serving_requests_1_0 1472 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0 + ramulator.average_serving_requests_1_0 0.128245 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0 + ramulator.active_cycles_1_0_0 1071 # Total active cycles for level _1_0_0 + ramulator.busy_cycles_1_0_0 1071 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0 + ramulator.serving_requests_1_0_0 1472 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0 +ramulator.average_serving_requests_1_0_0 0.128245 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0 + ramulator.active_cycles_1_0_0_0 1071 # Total active cycles for level _1_0_0_0 + ramulator.busy_cycles_1_0_0_0 1071 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_0 + ramulator.serving_requests_1_0_0_0 1472 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_0 +ramulator.average_serving_requests_1_0_0_0 0.128245 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_0 + ramulator.active_cycles_1_0_0_1 0 # Total active cycles for level _1_0_0_1 + ramulator.busy_cycles_1_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_1 + ramulator.serving_requests_1_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_1 +ramulator.average_serving_requests_1_0_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_1 + ramulator.active_cycles_1_0_0_2 0 # Total active cycles for level _1_0_0_2 + ramulator.busy_cycles_1_0_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_2 + ramulator.serving_requests_1_0_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_2 +ramulator.average_serving_requests_1_0_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_2 + ramulator.active_cycles_1_0_0_3 0 # Total active cycles for level _1_0_0_3 + ramulator.busy_cycles_1_0_0_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_3 + ramulator.serving_requests_1_0_0_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_3 +ramulator.average_serving_requests_1_0_0_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_3 + ramulator.active_cycles_1_0_1 0 # Total active cycles for level _1_0_1 + ramulator.busy_cycles_1_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1 + ramulator.serving_requests_1_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1 +ramulator.average_serving_requests_1_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1 + ramulator.active_cycles_1_0_1_0 0 # Total active cycles for level _1_0_1_0 + ramulator.busy_cycles_1_0_1_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_0 + ramulator.serving_requests_1_0_1_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_0 +ramulator.average_serving_requests_1_0_1_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_0 + ramulator.active_cycles_1_0_1_1 0 # Total active cycles for level _1_0_1_1 + ramulator.busy_cycles_1_0_1_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_1 + ramulator.serving_requests_1_0_1_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_1 +ramulator.average_serving_requests_1_0_1_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_1 + ramulator.active_cycles_1_0_1_2 0 # Total active cycles for level _1_0_1_2 + ramulator.busy_cycles_1_0_1_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_2 + ramulator.serving_requests_1_0_1_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_2 +ramulator.average_serving_requests_1_0_1_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_2 + ramulator.active_cycles_1_0_1_3 0 # Total active cycles for level _1_0_1_3 + ramulator.busy_cycles_1_0_1_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_3 + ramulator.serving_requests_1_0_1_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_3 +ramulator.average_serving_requests_1_0_1_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_3 + ramulator.active_cycles_1_0_2 0 # Total active cycles for level _1_0_2 + ramulator.busy_cycles_1_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2 + ramulator.serving_requests_1_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2 +ramulator.average_serving_requests_1_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2 + ramulator.active_cycles_1_0_2_0 0 # Total active cycles for level _1_0_2_0 + ramulator.busy_cycles_1_0_2_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_0 + ramulator.serving_requests_1_0_2_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_0 +ramulator.average_serving_requests_1_0_2_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_0 + ramulator.active_cycles_1_0_2_1 0 # Total active cycles for level _1_0_2_1 + ramulator.busy_cycles_1_0_2_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_1 + ramulator.serving_requests_1_0_2_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_1 +ramulator.average_serving_requests_1_0_2_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_1 + ramulator.active_cycles_1_0_2_2 0 # Total active cycles for level _1_0_2_2 + ramulator.busy_cycles_1_0_2_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_2 + ramulator.serving_requests_1_0_2_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_2 +ramulator.average_serving_requests_1_0_2_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_2 + ramulator.active_cycles_1_0_2_3 0 # Total active cycles for level _1_0_2_3 + ramulator.busy_cycles_1_0_2_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_3 + ramulator.serving_requests_1_0_2_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_3 +ramulator.average_serving_requests_1_0_2_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_3 + ramulator.active_cycles_1_0_3 0 # Total active cycles for level _1_0_3 + ramulator.busy_cycles_1_0_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3 + ramulator.serving_requests_1_0_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3 +ramulator.average_serving_requests_1_0_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3 + ramulator.active_cycles_1_0_3_0 0 # Total active cycles for level _1_0_3_0 + ramulator.busy_cycles_1_0_3_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_0 + ramulator.serving_requests_1_0_3_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_0 +ramulator.average_serving_requests_1_0_3_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_0 + ramulator.active_cycles_1_0_3_1 0 # Total active cycles for level _1_0_3_1 + ramulator.busy_cycles_1_0_3_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_1 + ramulator.serving_requests_1_0_3_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_1 +ramulator.average_serving_requests_1_0_3_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_1 + ramulator.active_cycles_1_0_3_2 0 # Total active cycles for level _1_0_3_2 + ramulator.busy_cycles_1_0_3_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_2 + ramulator.serving_requests_1_0_3_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_2 +ramulator.average_serving_requests_1_0_3_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_2 + ramulator.active_cycles_1_0_3_3 0 # Total active cycles for level _1_0_3_3 + ramulator.busy_cycles_1_0_3_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_3 + ramulator.serving_requests_1_0_3_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_3 +ramulator.average_serving_requests_1_0_3_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_3 + ramulator.read_transaction_bytes_1 3584 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_1 14848 # The total byte of write transaction per channel + ramulator.row_hits_channel_1_core 276 # Number of row hits per channel per core + ramulator.row_misses_channel_1_core 2 # Number of row misses per channel per core + ramulator.row_conflicts_channel_1_core 10 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_1_core 49 # Number of row hits for read requests per channel per core + [0] 49.0 # +ramulator.read_row_misses_channel_1_core 1 # Number of row misses for read requests per channel per core + [0] 1.0 # +ramulator.read_row_conflicts_channel_1_core 6 # Number of row conflicts for read requests per channel per core + [0] 6.0 # + ramulator.write_row_hits_channel_1_core 227 # Number of row hits for write requests per channel per core + [0] 227.0 # +ramulator.write_row_misses_channel_1_core 1 # Number of row misses for write requests per channel per core + [0] 1.0 # +ramulator.write_row_conflicts_channel_1_core 4 # Number of row conflicts for write requests per channel per core + [0] 4.0 # + ramulator.useless_activates_1_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_1 34.642857 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_1 1940 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_1 0.524830 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_1 6024 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_1 0.159261 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_1 1828 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_1 0.365569 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_1 4196 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 11478 # Number of DRAM cycles simulated + ramulator.incoming_requests 596 # Number of incoming requests to DRAM + ramulator.read_requests 114 # Number of incoming read requests to DRAM per core + [0] 114.0 # + ramulator.write_requests 482 # Number of incoming write requests to DRAM per core + [0] 482.0 # + ramulator.ramulator_active_cycles 2049 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 596.0 # Number of incoming requests to each DRAM channel + [0] 308.0 # + [1] 288.0 # +ramulator.incoming_read_reqs_per_channel 114.0 # Number of incoming read requests to each DRAM channel + [0] 58.0 # + [1] 56.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 38400000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 17427 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 4134 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 13293 # Sum of write queue length + ramulator.in_queue_req_num_avg 1.518296 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.360167 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 1.158129 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/tests/regression/relu/relu b/tests/regression/relu/relu new file mode 100755 index 0000000000000000000000000000000000000000..2b4a12c4c0dae9672db7cc8638d176d23301f801 GIT binary patch literal 27424 zcmeHwdvqMdnQ!Zb1-3^ru|R$h+KwO+wuQ#FjAfWuBTIG<9vQ{5z+g;kG&8a$NHb!l z#}7yrfh3m6FvNK+++>qD8@TZ~S@xP7vH>p`8RG}LK+G=Tc)@_fUcKPA!BSBn39WJzn?5g>>$^D{J}Bzl$DBf$@RPzt zat{i*2Zfx3r6QgZ%6O8GbS)Kn?NCJ-C6)auid}BKkh8-^!7m}%pw#+~5%^2&wFtQ< zg+e>LkE>TCl=i+3If~1FHi>X5YlXdB?a(LNK|ty!l&Kyty2M*XWtzx&*E{{6Sy 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