code refactoring: DRAM => MEM renaming
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2
hw/unit_tests/cache/testbench.cpp
vendored
2
hw/unit_tests/cache/testbench.cpp
vendored
@@ -175,7 +175,7 @@ int FLUSH(CacheSim *sim){
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int BACK_PRESSURE(CacheSim *sim){
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//happens whenever the core is stalled or DRAM is stalled
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//happens whenever the core is stalled or memory is stalled
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unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
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unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
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unsigned int rsp[4] = {0,0,0,0};
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