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Added prefix DCACHE_

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This commit is contained in:
Savan Roshan
2019-11-05 08:33:38 -05:00
parent cb3e2da584
commit 8468e7d4d9
9 changed files with 148 additions and 148 deletions
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52
rtl/VX_define.v
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@@ -12,10 +12,10 @@
// `define SYN 1 // `define SYN 1
`define ASIC 1 `define ASIC 1
`define CACHE_NUM_BANKS 8 `define DCACHE_NUM_BANKS 8
`define NUMBER_BANKS 8 `define DCACHE_NUMBER_BANKS 8
`define NUM_WORDS_PER_BLOCK 4 `define DCACHE_NUM_WORDS_PER_BLOCK 4
`define NUM_BARRIERS 4 `define NUM_BARRIERS 4
@@ -121,46 +121,46 @@
// `define PARAM // `define PARAM
//Cache configurations //Cache configurations
`define CACHE_SIZE 4096 //Bytes `define DCACHE_SIZE 4096 //Bytes
`ifdef SYN `ifdef SYN
`define CACHE_WAYS 1 `define DCACHE_WAYS 1
`else `else
`define CACHE_WAYS 2 `define DCACHE_WAYS 2
`endif `endif
`define CACHE_BLOCK 128 //Bytes `define DCACHE_BLOCK 128 //Bytes
`define CACHE_BANKS 8 `define DCACHE_BANKS 8
`define NUM_WORDS_PER_BLOCK 4 `define DCACHE_NUM_WORDS_PER_BLOCK 4
`define NUM_REQ `NT `define DCACHE_NUM_REQ `NT
`define CACHE_WAY_INDEX $clog2(`CACHE_WAYS) //set this to 1 if CACHE_WAYS is 1 `define DCACHE_WAY_INDEX $clog2(`DCACHE_WAYS) //set this to 1 if CACHE_WAYS is 1
//`define CACHE_WAY_INDEX 1 //`define DCACHE_WAY_INDEX 1
`define CACHE_BLOCK_PER_BANK (`CACHE_BLOCK / `CACHE_BANKS) `define DCACHE_BLOCK_PER_BANK (`DCACHE_BLOCK / `DCACHE_BANKS)
// Offset // Offset
`define CACHE_OFFSET_NB ($clog2(`NUM_WORDS_PER_BLOCK)) `define DCACHE_OFFSET_NB ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK))
`define CACHE_OFFSET_ST (2+$clog2(`NUMBER_BANKS)) `define DCACHE_OFFSET_ST (2+$clog2(`DCACHE_NUMBER_BANKS))
`define CACHE_OFFSET_ED (`CACHE_OFFSET_ST+(`CACHE_OFFSET_NB)-1) `define DCACHE_OFFSET_ED (`DCACHE_OFFSET_ST+(`DCACHE_OFFSET_NB)-1)
`define CACHE_ADDR_OFFSET_RNG `CACHE_OFFSET_ED:`CACHE_OFFSET_ST `define DCACHE_ADDR_OFFSET_RNG `DCACHE_OFFSET_ED:`DCACHE_OFFSET_ST
`define CACHE_OFFSET_SIZE_RNG ($clog2(`NUM_WORDS_PER_BLOCK)-1):0 `define DCACHE_OFFSET_SIZE_RNG ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)-1):0
// Index // Index
`define NUM_IND (`CACHE_SIZE / (`CACHE_WAYS * `CACHE_BLOCK_PER_BANK)) `define DCACHE_NUM_IND (`DCACHE_SIZE / (`DCACHE_WAYS * `DCACHE_BLOCK_PER_BANK))
`define CACHE_IND_NB ($clog2(`NUM_IND)) `define DCACHE_IND_NB ($clog2(`DCACHE_NUM_IND))
`define CACHE_IND_ST (`CACHE_OFFSET_ED+1) `define DCACHE_IND_ST (`DCACHE_OFFSET_ED+1)
`define CACHE_IND_ED (`CACHE_IND_ST+`CACHE_IND_NB-1) `define DCACHE_IND_ED (`DCACHE_IND_ST+`DCACHE_IND_NB-1)
`define CACHE_ADDR_IND_RNG `CACHE_IND_ED:`CACHE_IND_ST `define DCACHE_ADDR_IND_RNG `DCACHE_IND_ED:`DCACHE_IND_ST
`define CACHE_IND_SIZE_RNG `CACHE_IND_NB-1:0 `define DCACHE_IND_SIZE_RNG `DCACHE_IND_NB-1:0
// Tag // Tag
`define CACHE_ADDR_TAG_RNG 31:(`CACHE_IND_ED+1) `define DCACHE_ADDR_TAG_RNG 31:(`DCACHE_IND_ED+1)
`define CACHE_TAG_SIZE_RNG (32-(`CACHE_IND_ED+1)-1):0 `define DCACHE_TAG_SIZE_RNG (32-(`DCACHE_IND_ED+1)-1):0

8
rtl/Vortex.v
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@@ -22,11 +22,11 @@ module Vortex
output reg [31:0] o_m_read_addr, output reg [31:0] o_m_read_addr,
output reg [31:0] o_m_evict_addr, output reg [31:0] o_m_evict_addr,
output reg o_m_valid, output reg o_m_valid,
output reg [31:0] o_m_writedata[`CACHE_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0], output reg [31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
output reg o_m_read_or_write, output reg o_m_read_or_write,
// Rsp // Rsp
input wire [31:0] i_m_readdata[`CACHE_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0], input wire [31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
input wire i_m_ready, input wire i_m_ready,
output wire out_ebreak output wire out_ebreak
); );
@@ -59,9 +59,9 @@ assign VX_dram_req_rsp.i_m_ready = i_m_ready;
genvar curr_bank; genvar curr_bank;
genvar curr_word; genvar curr_word;
for (curr_bank = 0; curr_bank < `CACHE_BANKS; curr_bank = curr_bank + 1) begin for (curr_bank = 0; curr_bank < `DCACHE_BANKS; curr_bank = curr_bank + 1) begin
for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin for (curr_word = 0; curr_word < `DCACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
assign o_m_writedata[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word]; assign o_m_writedata[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];
assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word]; assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];

30
rtl/cache/VX_Cache_Bank.v vendored
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@@ -58,25 +58,25 @@ module VX_Cache_Bank
//input wire write_from_mem; //input wire write_from_mem;
// Reading Data // Reading Data
input wire[`CACHE_IND_SIZE_RNG] actual_index; input wire[`DCACHE_IND_SIZE_RNG] actual_index;
input wire[`CACHE_TAG_SIZE_RNG] o_tag; // When write_from_mem = 1, o_tag is the new tag input wire[`DCACHE_TAG_SIZE_RNG] o_tag; // When write_from_mem = 1, o_tag is the new tag
input wire[`CACHE_OFFSET_SIZE_RNG] block_offset; input wire[`DCACHE_OFFSET_SIZE_RNG] block_offset;
input wire[31:0] writedata; input wire[31:0] writedata;
input wire valid_in; input wire valid_in;
input wire read_or_write; // Specifies if it is a read or write operation input wire read_or_write; // Specifies if it is a read or write operation
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata; input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata;
input wire[2:0] i_p_mem_read; input wire[2:0] i_p_mem_read;
input wire[2:0] i_p_mem_write; input wire[2:0] i_p_mem_write;
input wire[1:0] byte_select; input wire[1:0] byte_select;
input wire[`CACHE_WAY_INDEX-1:0] evicted_way; input wire[`DCACHE_WAY_INDEX-1:0] evicted_way;
output wire[`CACHE_WAY_INDEX-1:0] way_use; output wire[`DCACHE_WAY_INDEX-1:0] way_use;
// Outputs // Outputs
// Normal shit // Normal shit
@@ -89,13 +89,13 @@ module VX_Cache_Bank
output wire[31:0] eviction_addr; // What's the eviction tag output wire[31:0] eviction_addr; // What's the eviction tag
// Eviction Data (Extraction) // Eviction Data (Extraction)
output wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted; output wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_use; wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_use;
wire[`CACHE_TAG_SIZE_RNG] tag_use; wire[`DCACHE_TAG_SIZE_RNG] tag_use;
wire[`CACHE_TAG_SIZE_RNG] eviction_tag; wire[`DCACHE_TAG_SIZE_RNG] eviction_tag;
wire valid_use; wire valid_use;
wire dirty_use; wire dirty_use;
wire access; wire access;
@@ -104,8 +104,8 @@ module VX_Cache_Bank
wire[`CACHE_WAY_INDEX-1:0] update_way; wire[`DCACHE_WAY_INDEX-1:0] update_way;
wire[`CACHE_WAY_INDEX-1:0] way_to_update; wire[`DCACHE_WAY_INDEX-1:0] way_to_update;
assign miss = (tag_use != o_tag) && valid_use && valid_in; assign miss = (tag_use != o_tag) && valid_use && valid_in;
@@ -180,10 +180,10 @@ module VX_Cache_Bank
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we; wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0] we;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write; wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
genvar g; genvar g;
for (g = 0; g < `NUM_WORDS_PER_BLOCK; g = g + 1) begin for (g = 0; g < `DCACHE_NUM_WORDS_PER_BLOCK; g = g + 1) begin
wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss); wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss);
assign we[g] = (write_from_mem) ? 4'b1111 : assign we[g] = (write_from_mem) ? 4'b1111 :

34
rtl/cache/VX_cache_data.v vendored
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@@ -15,17 +15,17 @@ module VX_cache_data
// `ifdef PARAM // `ifdef PARAM
// Addr // Addr
input wire[`CACHE_IND_SIZE_RNG] addr, input wire[`DCACHE_IND_SIZE_RNG] addr,
// WE // WE
input wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we, input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict, input wire evict,
// Data // Data
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_write,
input wire[`CACHE_TAG_SIZE_RNG] tag_write, input wire[`DCACHE_TAG_SIZE_RNG] tag_write,
output wire[`CACHE_TAG_SIZE_RNG] tag_use, output wire[`DCACHE_TAG_SIZE_RNG] tag_use,
output wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, output wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use, output wire valid_use,
output wire dirty_use output wire dirty_use
// `else // `else
@@ -50,7 +50,7 @@ module VX_cache_data
//localparam NUMBER_BANKS = CACHE_BANKS; //localparam NUMBER_BANKS = CACHE_BANKS;
//localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS); //localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4); // localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
//localparam NUMBER_INDEXES = `NUM_IND; //localparam NUMBER_INDEXES = `DCACHE_NUM_IND;
wire currently_writing = (|we); wire currently_writing = (|we);
wire update_dirty = ((!dirty_use) && currently_writing) || (evict); wire update_dirty = ((!dirty_use) && currently_writing) || (evict);
@@ -61,10 +61,10 @@ module VX_cache_data
`ifndef SYN `ifndef SYN
// (3:0) 4 bytes // (3:0) 4 bytes
reg[`NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[`NUM_IND-1:0]; // Actual Data reg[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[`DCACHE_NUM_IND-1:0]; // Actual Data
reg[`CACHE_TAG_SIZE_RNG] tag[`NUM_IND-1:0]; reg[`DCACHE_TAG_SIZE_RNG] tag[`DCACHE_NUM_IND-1:0];
reg valid[`NUM_IND-1:0]; reg valid[`DCACHE_NUM_IND-1:0];
reg dirty[`NUM_IND-1:0]; reg dirty[`DCACHE_NUM_IND-1:0];
// 16 bytes // 16 bytes
@@ -77,7 +77,7 @@ module VX_cache_data
integer ini_ind; integer ini_ind;
always @(posedge clk, posedge rst) begin : update_all always @(posedge clk, posedge rst) begin : update_all
if (rst) begin if (rst) begin
for (ini_ind = 0; ini_ind < `NUM_IND; ini_ind=ini_ind+1) begin for (ini_ind = 0; ini_ind < `DCACHE_NUM_IND; ini_ind=ini_ind+1) begin
data[ini_ind] <= 0; data[ini_ind] <= 0;
tag[ini_ind] <= 0; tag[ini_ind] <= 0;
valid[ini_ind] <= 0; valid[ini_ind] <= 0;
@@ -88,7 +88,7 @@ module VX_cache_data
if (evict) tag[addr] <= tag_write; if (evict) tag[addr] <= tag_write;
if (evict) valid[addr] <= 1; if (evict) valid[addr] <= 1;
for (f = 0; f < `NUM_WORDS_PER_BLOCK; f = f + 1) begin for (f = 0; f < `DCACHE_NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ]; if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ]; if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
if (we[f][2]) data[addr][f][2] <= data_write[f][23:16]; if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
@@ -103,11 +103,11 @@ module VX_cache_data
wire cena = 1; wire cena = 1;
wire cenb_d = (|we); wire cenb_d = (|we);
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write; wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d; wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d; wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d;
genvar cur_b; genvar cur_b;
for (cur_b = 0; cur_b < `NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin for (cur_b = 0; cur_b < `DCACHE_NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin
assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}}; assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}};
end end
assign data_use = data_out_d; assign data_use = data_out_d;

52
rtl/cache/VX_cache_data_per_index.v vendored
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@@ -15,52 +15,52 @@ module VX_cache_data_per_index
input wire rst, input wire rst,
input wire valid_in, input wire valid_in,
// Addr // Addr
input wire[`CACHE_IND_SIZE_RNG] addr, input wire[`DCACHE_IND_SIZE_RNG] addr,
// WE // WE
input wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we, input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict, input wire evict,
input wire[`CACHE_WAY_INDEX-1:0] way_to_update, input wire[`DCACHE_WAY_INDEX-1:0] way_to_update,
// Data // Data
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
input wire[`CACHE_TAG_SIZE_RNG] tag_write, input wire[`DCACHE_TAG_SIZE_RNG] tag_write,
output wire[`CACHE_TAG_SIZE_RNG] tag_use, output wire[`DCACHE_TAG_SIZE_RNG] tag_use,
output wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, output wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use, output wire valid_use,
output wire dirty_use, output wire dirty_use,
output wire[`CACHE_WAY_INDEX-1:0] way output wire[`DCACHE_WAY_INDEX-1:0] way
); );
//localparam NUMBER_BANKS = CACHE_BANKS; //localparam NUMBER_BANKS = CACHE_BANKS;
//localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS); //localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4); // localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
//localparam NUMBER_INDEXES = `NUM_IND; //localparam NUMBER_INDEXES = `DCACHE_NUM_IND;
wire [`CACHE_WAYS-1:0][`CACHE_TAG_SIZE_RNG] tag_use_per_way; wire [`DCACHE_WAYS-1:0][`DCACHE_TAG_SIZE_RNG] tag_use_per_way;
wire [`CACHE_WAYS-1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way; wire [`DCACHE_WAYS-1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way;
wire [`CACHE_WAYS-1:0] valid_use_per_way; wire [`DCACHE_WAYS-1:0] valid_use_per_way;
wire [`CACHE_WAYS-1:0] dirty_use_per_way; wire [`DCACHE_WAYS-1:0] dirty_use_per_way;
wire [`CACHE_WAYS-1:0] hit_per_way; wire [`DCACHE_WAYS-1:0] hit_per_way;
reg [`NUM_IND-1:0][`CACHE_WAY_INDEX-1:0] eviction_way_index; reg [`DCACHE_NUM_IND-1:0][`DCACHE_WAY_INDEX-1:0] eviction_way_index;
wire [`CACHE_WAYS-1:0][`NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way; wire [`DCACHE_WAYS-1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way;
wire [`CACHE_WAYS-1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way; wire [`DCACHE_WAYS-1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way;
wire [`CACHE_WAYS-1:0] write_from_mem_per_way; wire [`DCACHE_WAYS-1:0] write_from_mem_per_way;
wire invalid_found; wire invalid_found;
wire [`CACHE_WAY_INDEX-1:0] way_index; wire [`DCACHE_WAY_INDEX-1:0] way_index;
wire [`CACHE_WAY_INDEX-1:0] invalid_index; wire [`DCACHE_WAY_INDEX-1:0] invalid_index;
if(`CACHE_WAYS != 1) begin if(`DCACHE_WAYS != 1) begin
VX_generic_priority_encoder #(.N(`CACHE_WAYS)) valid_index VX_generic_priority_encoder #(.N(`DCACHE_WAYS)) valid_index
( (
.valids(~valid_use_per_way), .valids(~valid_use_per_way),
.index (invalid_index), .index (invalid_index),
.found (invalid_found) .found (invalid_found)
); );
VX_generic_priority_encoder #(.N(`CACHE_WAYS)) way_indexing VX_generic_priority_encoder #(.N(`DCACHE_WAYS)) way_indexing
( (
.valids(hit_per_way), .valids(hit_per_way),
.index (way_index), .index (way_index),
@@ -90,7 +90,7 @@ module VX_cache_data_per_index
genvar ways; genvar ways;
for(ways=0; ways < `CACHE_WAYS; ways = ways + 1) begin for(ways=0; ways < `DCACHE_WAYS; ways = ways + 1) begin
assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0; assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? (we) : 0) : 0; assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? (we) : 0) : 0;
@@ -99,7 +99,7 @@ module VX_cache_data_per_index
/*VX_cache_data #( /*VX_cache_data #(
.CACHE_SIZE(`CACHE_SIZE), .CACHE_SIZE(`CACHE_SIZE),
.CACHE_WAYS(`CACHE_WAYS), .CACHE_WAYS(`DCACHE_WAYS),
.CACHE_BLOCK(`CACHE_BLOCK), .CACHE_BLOCK(`CACHE_BLOCK),
.CACHE_BANKS(`CACHE_BANKS)) data_structures(*/ .CACHE_BANKS(`CACHE_BANKS)) data_structures(*/
VX_cache_data data_structures( VX_cache_data data_structures(
@@ -124,7 +124,7 @@ module VX_cache_data_per_index
eviction_way_index <= 0; eviction_way_index <= 0;
end else begin end else begin
if(miss && dirty_use && valid_use && !evict && valid_in) begin // can be either evict or invalid cache entries if(miss && dirty_use && valid_use && !evict && valid_in) begin // can be either evict or invalid cache entries
if((eviction_way_index[addr]+1) == `CACHE_WAYS) begin if((eviction_way_index[addr]+1) == `DCACHE_WAYS) begin
eviction_way_index[addr] <= 0; eviction_way_index[addr] <= 0;
end else begin end else begin
eviction_way_index[addr] <= (eviction_way_index[addr] + 1); eviction_way_index[addr] <= (eviction_way_index[addr] + 1);

86
rtl/cache/VX_d_cache.v vendored
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@@ -59,18 +59,18 @@ module VX_d_cache
//parameter cache_entry = 9; //parameter cache_entry = 9;
input wire clk, rst; input wire clk, rst;
input wire [`NUM_REQ-1:0] i_p_valid; input wire [`DCACHE_NUM_REQ-1:0] i_p_valid;
input wire [`NUM_REQ-1:0][31:0] i_p_addr; // FIXME input wire [`DCACHE_NUM_REQ-1:0][31:0] i_p_addr; // FIXME
input wire [`NUM_REQ-1:0][31:0] i_p_writedata; input wire [`DCACHE_NUM_REQ-1:0][31:0] i_p_writedata;
input wire i_p_read_or_write; //, i_p_write; input wire i_p_read_or_write; //, i_p_write;
output reg [`NUM_REQ-1:0][31:0] o_p_readdata; output reg [`DCACHE_NUM_REQ-1:0][31:0] o_p_readdata;
output wire o_p_delay; output wire o_p_delay;
output reg [31:0] o_m_evict_addr; // Address is xxxxxxxxxxoooobbbyy output reg [31:0] o_m_evict_addr; // Address is xxxxxxxxxxoooobbbyy
output reg [31:0] o_m_read_addr; output reg [31:0] o_m_read_addr;
output reg o_m_valid; output reg o_m_valid;
output reg[`CACHE_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; output reg[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
output reg o_m_read_or_write; //, o_m_write; output reg o_m_read_or_write; //, o_m_write;
input wire[`CACHE_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; input wire[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
input wire i_m_ready; input wire i_m_ready;
input wire[2:0] i_p_mem_read; input wire[2:0] i_p_mem_read;
@@ -78,41 +78,41 @@ module VX_d_cache
// Buffer for final data // Buffer for final data
reg [`NUM_REQ-1:0][31:0] final_data_read; reg [`DCACHE_NUM_REQ-1:0][31:0] final_data_read;
reg [`NUM_REQ-1:0][31:0] new_final_data_read; reg [`DCACHE_NUM_REQ-1:0][31:0] new_final_data_read;
wire[`NUM_REQ-1:0][31:0] new_final_data_read_Qual; wire[`DCACHE_NUM_REQ-1:0][31:0] new_final_data_read_Qual;
assign o_p_readdata = new_final_data_read_Qual; assign o_p_readdata = new_final_data_read_Qual;
wire[`CACHE_BANKS - 1 : 0][`NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank wire[`DCACHE_BANKS - 1 : 0][`DCACHE_NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank
wire[`CACHE_BANKS - 1 : 0][$clog2(`NUM_REQ)-1:0] index_per_bank; // Index of thread each bank will try to service wire[`DCACHE_BANKS - 1 : 0][$clog2(`DCACHE_NUM_REQ)-1:0] index_per_bank; // Index of thread each bank will try to service
wire[`CACHE_BANKS - 1 : 0][`NUM_REQ-1:0] use_mask_per_bank; // A mask of index_per_bank wire[`DCACHE_BANKS - 1 : 0][`DCACHE_NUM_REQ-1:0] use_mask_per_bank; // A mask of index_per_bank
wire[`CACHE_BANKS - 1 : 0] valid_per_bank; // Valid request going to each bank wire[`DCACHE_BANKS - 1 : 0] valid_per_bank; // Valid request going to each bank
wire[`CACHE_BANKS - 1 : 0][`NUM_REQ-1:0] threads_serviced_per_bank; // Bank successfully serviced per bank wire[`DCACHE_BANKS - 1 : 0][`DCACHE_NUM_REQ-1:0] threads_serviced_per_bank; // Bank successfully serviced per bank
wire[`CACHE_BANKS-1:0][31:0] readdata_per_bank; // Data read from each bank wire[`DCACHE_BANKS-1:0][31:0] readdata_per_bank; // Data read from each bank
wire[`CACHE_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss wire[`DCACHE_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss
wire[`CACHE_BANKS-1:0] eviction_wb; wire[`DCACHE_BANKS-1:0] eviction_wb;
reg[`CACHE_BANKS-1:0] eviction_wb_old; reg[`DCACHE_BANKS-1:0] eviction_wb_old;
wire[`CACHE_BANKS -1 : 0][`CACHE_WAY_INDEX-1:0] evicted_way_new; wire[`DCACHE_BANKS -1 : 0][`DCACHE_WAY_INDEX-1:0] evicted_way_new;
reg [`CACHE_BANKS -1 : 0][`CACHE_WAY_INDEX-1:0] evicted_way_old; reg [`DCACHE_BANKS -1 : 0][`DCACHE_WAY_INDEX-1:0] evicted_way_old;
wire[`CACHE_BANKS -1 : 0][`CACHE_WAY_INDEX-1:0] way_used; wire[`DCACHE_BANKS -1 : 0][`DCACHE_WAY_INDEX-1:0] way_used;
// Internal State // Internal State
reg [3:0] state; reg [3:0] state;
wire[3:0] new_state; wire[3:0] new_state;
wire[`NUM_REQ-1:0] use_valid; // Valid used throught the code wire[`DCACHE_NUM_REQ-1:0] use_valid; // Valid used throught the code
reg[`NUM_REQ-1:0] stored_valid; // Saving the threads still left (bank conflict or bank miss) reg[`DCACHE_NUM_REQ-1:0] stored_valid; // Saving the threads still left (bank conflict or bank miss)
wire[`NUM_REQ-1:0] new_stored_valid; // New stored valid wire[`DCACHE_NUM_REQ-1:0] new_stored_valid; // New stored valid
reg[`CACHE_BANKS - 1 : 0][31:0] eviction_addr_per_bank; reg[`DCACHE_BANKS - 1 : 0][31:0] eviction_addr_per_bank;
reg[31:0] miss_addr; reg[31:0] miss_addr;
reg[31:0] evict_addr; reg[31:0] evict_addr;
@@ -127,39 +127,39 @@ module VX_d_cache
VX_cache_bank_valid #(.NUMBER_BANKS(`CACHE_BANKS)) multip_banks( VX_cache_bank_valid #(.NUMBER_BANKS(`DCACHE_BANKS)) multip_banks(
.i_p_valid (use_valid), .i_p_valid (use_valid),
.i_p_addr (i_p_addr), .i_p_addr (i_p_addr),
.thread_track_banks(thread_track_banks) .thread_track_banks(thread_track_banks)
); );
reg[`NUM_REQ-1:0] threads_serviced_Qual; reg[`DCACHE_NUM_REQ-1:0] threads_serviced_Qual;
reg[`NUM_REQ-1:0] debug_hit_per_bank_mask[`CACHE_BANKS-1:0]; reg[`DCACHE_NUM_REQ-1:0] debug_hit_per_bank_mask[`DCACHE_BANKS-1:0];
genvar bid; genvar bid;
for (bid = 0; bid < `CACHE_BANKS; bid=bid+1) for (bid = 0; bid < `DCACHE_BANKS; bid=bid+1)
begin begin
wire[`NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid]; wire[`DCACHE_NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid];
wire[$clog2(`NUM_REQ)-1:0] use_thread_index = index_per_bank[bid]; wire[$clog2(`DCACHE_NUM_REQ)-1:0] use_thread_index = index_per_bank[bid];
wire use_write_final_data = hit_per_bank[bid]; wire use_write_final_data = hit_per_bank[bid];
wire[31:0] use_data_final_data = readdata_per_bank[bid]; wire[31:0] use_data_final_data = readdata_per_bank[bid];
VX_priority_encoder_w_mask #(.N(`NUM_REQ)) choose_thread( VX_priority_encoder_w_mask #(.N(`DCACHE_NUM_REQ)) choose_thread(
.valids(use_threads_track_banks), .valids(use_threads_track_banks),
.mask (use_mask_per_bank[bid]), .mask (use_mask_per_bank[bid]),
.index (index_per_bank[bid]), .index (index_per_bank[bid]),
.found (valid_per_bank[bid]) .found (valid_per_bank[bid])
); );
assign debug_hit_per_bank_mask[bid] = {`NUM_REQ{hit_per_bank[bid]}}; assign debug_hit_per_bank_mask[bid] = {`DCACHE_NUM_REQ{hit_per_bank[bid]}};
assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid]; assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid];
end end
integer test_bid; integer test_bid;
always @(*) begin always @(*) begin
new_final_data_read = 0; new_final_data_read = 0;
for (test_bid=0; test_bid < `CACHE_BANKS; test_bid=test_bid+1) for (test_bid=0; test_bid < `DCACHE_BANKS; test_bid=test_bid+1)
begin begin
if (hit_per_bank[test_bid]) begin if (hit_per_bank[test_bid]) begin
new_final_data_read[index_per_bank[test_bid]] = readdata_per_bank[test_bid]; new_final_data_read[index_per_bank[test_bid]] = readdata_per_bank[test_bid];
@@ -168,7 +168,7 @@ module VX_d_cache
end end
wire[`CACHE_BANKS - 1 : 0] detect_bank_miss; wire[`DCACHE_BANKS - 1 : 0] detect_bank_miss;
assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] | assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] |
threads_serviced_per_bank[2] | threads_serviced_per_bank[3] | threads_serviced_per_bank[2] | threads_serviced_per_bank[3] |
threads_serviced_per_bank[4] | threads_serviced_per_bank[5] | threads_serviced_per_bank[4] | threads_serviced_per_bank[5] |
@@ -184,7 +184,7 @@ module VX_d_cache
genvar tid; genvar tid;
for (tid = 0; tid < `NUM_REQ; tid =tid+1) for (tid = 0; tid < `DCACHE_NUM_REQ; tid =tid+1)
begin begin
assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid]; assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid];
end end
@@ -197,12 +197,12 @@ module VX_d_cache
assign o_p_delay = delay; assign o_p_delay = delay;
wire[`CACHE_BANKS - 1 : 0][$clog2(`NUM_REQ)-1:0] send_index_to_bank = index_per_bank; wire[`DCACHE_BANKS - 1 : 0][$clog2(`DCACHE_NUM_REQ)-1:0] send_index_to_bank = index_per_bank;
wire[$clog2(`CACHE_BANKS)-1:0] miss_bank_index; wire[$clog2(`DCACHE_BANKS)-1:0] miss_bank_index;
wire miss_found; wire miss_found;
VX_generic_priority_encoder #(.N(`CACHE_BANKS)) get_miss_index VX_generic_priority_encoder #(.N(`DCACHE_BANKS)) get_miss_index
( (
.valids(detect_bank_miss), .valids(detect_bank_miss),
.index (miss_bank_index), .index (miss_bank_index),
@@ -258,7 +258,7 @@ module VX_d_cache
genvar bank_id; genvar bank_id;
generate generate
for (bank_id = 0; bank_id < `CACHE_BANKS; bank_id = bank_id + 1) for (bank_id = 0; bank_id < `DCACHE_BANKS; bank_id = bank_id + 1)
begin begin
wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? evict_addr : wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? evict_addr :
(state == RECIV_MEM_RSP) ? miss_addr : (state == RECIV_MEM_RSP) ? miss_addr :
@@ -269,9 +269,9 @@ module VX_d_cache
0; 0;
wire[1:0] byte_select = bank_addr[1:0]; wire[1:0] byte_select = bank_addr[1:0];
wire[`CACHE_OFFSET_SIZE_RNG] cache_offset = bank_addr[`CACHE_ADDR_OFFSET_RNG]; wire[`DCACHE_OFFSET_SIZE_RNG] cache_offset = bank_addr[`DCACHE_ADDR_OFFSET_RNG];
wire[`CACHE_IND_SIZE_RNG] cache_index = bank_addr[`CACHE_ADDR_IND_RNG]; wire[`DCACHE_IND_SIZE_RNG] cache_index = bank_addr[`DCACHE_ADDR_IND_RNG];
wire[`CACHE_TAG_SIZE_RNG] cache_tag = bank_addr[`CACHE_ADDR_TAG_RNG]; wire[`DCACHE_TAG_SIZE_RNG] cache_tag = bank_addr[`DCACHE_ADDR_TAG_RNG];
wire normal_valid_in = valid_per_bank[bank_id]; wire normal_valid_in = valid_per_bank[bank_id];

4
rtl/interfaces/VX_dram_req_rsp_inter.v
View File

@@ -11,11 +11,11 @@ interface VX_dram_req_rsp_inter ();
wire [31:0] o_m_evict_addr; wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr; wire [31:0] o_m_read_addr;
wire o_m_valid; wire o_m_valid;
wire[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; wire[`DCACHE_NUMBER_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write; wire o_m_read_or_write;
// Rsp // Rsp
wire[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; wire[`DCACHE_NUMBER_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready; wire i_m_ready;

12
rtl/modelsim/vortex_tb.v
View File

@@ -1,8 +1,8 @@
`include "../VX_define.v" `include "../VX_define.v"
`define NUMBER_BANKS 8 //`define NUMBER_BANKS 8
`define NUM_WORDS_PER_BLOCK 4 //`define NUM_WORDS_PER_BLOCK 4
`define ARM_UD_MODEL `define ARM_UD_MODEL
@@ -17,11 +17,11 @@ import "DPI-C" dbus_driver = function void dbus_driver( input logic clk,
input int o_m_read_addr, input int o_m_read_addr,
input int o_m_evict_addr, input int o_m_evict_addr,
input logic o_m_valid, input logic o_m_valid,
input reg[31:0] o_m_writedata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0], input reg[31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
input logic o_m_read_or_write, input logic o_m_read_or_write,
// Rsp // Rsp
output reg[31:0] i_m_readdata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0], output reg[31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
output logic i_m_ready); output logic i_m_ready);
@@ -46,11 +46,11 @@ module vortex_tb (
reg [31:0] o_m_read_addr; reg [31:0] o_m_read_addr;
reg [31:0] o_m_evict_addr; reg [31:0] o_m_evict_addr;
reg o_m_valid; reg o_m_valid;
reg [31:0] o_m_writedata[8 - 1:0][4-1:0]; reg [31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0];
reg o_m_read_or_write; reg o_m_read_or_write;
// Rsp // Rsp
reg [31:0] i_m_readdata[8 - 1:0][4-1:0]; reg [31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK -1:0];
reg i_m_ready; reg i_m_ready;
reg out_ebreak; reg out_ebreak;