From 85213d287674be2b0a57ef9e4908bfd183d92802 Mon Sep 17 00:00:00 2001 From: Richard Yan Date: Wed, 17 Apr 2024 18:05:51 -0700 Subject: [PATCH] synthesizable design --- .gitmodules | 2 +- hw/rtl/VX_core_wrapper.sv | 21 +++--------------- hw/rtl/VX_platform.vh | 25 +++++++++++++++++++++ hw/rtl/cache/VX_cache.sv | 4 ++-- hw/rtl/cache/VX_cache_bank.sv | 26 +++++++++++----------- hw/rtl/cache/VX_cache_data.sv | 10 ++++----- hw/rtl/cache/VX_cache_mshr.sv | 20 ++++++++--------- hw/rtl/cache/VX_cache_tags.sv | 12 +++++----- hw/rtl/cache/VX_cache_top.sv | 6 ++--- hw/rtl/core/VX_lsu_unit.sv | 2 +- hw/rtl/core/VX_smem_unit.sv | 3 ++- hw/rtl/fpu/VX_fpu_define.vh | 2 ++ hw/rtl/libs/VX_lzc.sv | 2 +- hw/rtl/libs/VX_mem_scheduler.sv | 16 +++++++------- hw/rtl/mem/VX_smem_switch.sv | 39 +++++++++++++++++++++++---------- third_party/fpnew | 2 +- 16 files changed, 110 insertions(+), 82 deletions(-) diff --git a/.gitmodules b/.gitmodules index af1d1a47..63d4bdf1 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,6 @@ [submodule "third_party/fpnew"] path = third_party/fpnew - url = https://github.com/pulp-platform/fpnew.git + url = https://github.com/richardyrh/cvfpu.git [submodule "third_party/softfloat"] path = third_party/softfloat url = https://github.com/ucb-bar/berkeley-softfloat-3.git diff --git a/hw/rtl/VX_core_wrapper.sv b/hw/rtl/VX_core_wrapper.sv index cf8d9f53..457318ab 100644 --- a/hw/rtl/VX_core_wrapper.sv +++ b/hw/rtl/VX_core_wrapper.sv @@ -18,7 +18,7 @@ module Vortex import VX_gpu_pkg::*; #( input interrupts_mtip, input interrupts_msip, input interrupts_meip, - // input interrupts_seip, + input interrupts_seip, // imem ------------------------------------------------ @@ -297,18 +297,6 @@ module Vortex import VX_gpu_pkg::*; #( // assign {fpu_hartid, fpu_time, fpu_inst, fpu_fromint_data, fpu_fcsr_rm, fpu_dmem_resp_val, fpu_dmem_resp_type, // fpu_dmem_resp_tag, fpu_valid, fpu_killx, fpu_killm, fpu_keep_clock_enabled} = '0; - for (genvar i = 0; i < 4; i++) begin - always @(posedge clock) begin - if (dcache_bus_if[i].req_valid && dcache_bus_if[i].req_ready && dcache_bus_if[i].req_data.rw) begin - // anything that starts with 0xC is heap address - if ({dcache_bus_if[i].req_data.addr, 2'b0}[31:28] == 4'hc) begin - $display("[%d] STORE HEAP MEM: CORE=%d, THREAD=%d, ADDRESS=0x%X, DATA=0x%08X", - $time(), CORE_ID, i, {dcache_bus_if[i].req_data.addr, 2'b0}, dcache_bus_if[i].req_data.data); - end - end - end - end - logic sim_ebreak; logic [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value; @@ -398,10 +386,11 @@ module Vortex import VX_gpu_pkg::*; #( VX_mem_perf_if mem_perf_if(); + // TODO: SCOPE_IO_BIND should be socket id VX_core #( .CORE_ID (CORE_ID) ) core ( - `SCOPE_IO_BIND (0) // TODO: should be socket id + `SCOPE_IO_BIND (0) .clk (clock), .reset (core_reset), @@ -498,9 +487,6 @@ module Vortex import VX_gpu_pkg::*; #( always @(*) begin if (busy === 1'b0) begin $display("---------------- no more active warps ----------------"); - - @(negedge clock); - // TODO: lane assumed to be 4 // `ifndef SYNTHESIS // for (integer j = 0; j < `NUM_WARPS; j++) begin @@ -513,7 +499,6 @@ module Vortex import VX_gpu_pkg::*; #( // pipeline.issue.gpr_stage.iports[/*thread*/3].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k]); // end // `endif - // @(posedge clock) $finish(); end end diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index 4125b60f..9eb4d279 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -14,6 +14,27 @@ `ifndef VX_PLATFORM_VH `define VX_PLATFORM_VH +`define GPR_RESET +`define LSU_DUP_DISABLE +`define ICACHE_DISABLE +`define DCACHE_DISABLE +`define GBAR_ENABLE +`define GBAR_CLUSTER_ENABLE +`define FPU_FPNEW +`define NUM_BARRIERS 8 +`define NUM_CORES 2 +`define NUM_THREADS 8 +`define NUM_WARPS 8 + +// synthesis only +`ifndef SIMULATION +`define SYNTHESIS +`define NDEBUG +`define DPI_DISABLE +`else +`define SV_DPI +`endif + `ifdef SV_DPI `include "util_dpi.vh" `endif @@ -25,8 +46,12 @@ `ifdef VIVADO `define STRING `else +`ifdef SYNTHESIS +`define STRING +`else `define STRING string `endif +`endif `ifdef SYNTHESIS `define TRACING_ON diff --git a/hw/rtl/cache/VX_cache.sv b/hw/rtl/cache/VX_cache.sv index 891512da..755fb974 100644 --- a/hw/rtl/cache/VX_cache.sv +++ b/hw/rtl/cache/VX_cache.sv @@ -14,7 +14,7 @@ `include "VX_cache_define.vh" module VX_cache import VX_gpu_pkg::*; #( - parameter `STRING INSTANCE_ID = "", + parameter `STRING INST_ID = "", // Number of Word requests per cycle parameter NUM_REQS = 4, @@ -333,7 +333,7 @@ module VX_cache import VX_gpu_pkg::*; #( VX_cache_bank #( .BANK_ID (i), - .INSTANCE_ID (INSTANCE_ID), + .INST_ID (INST_ID), .CACHE_SIZE (CACHE_SIZE), .LINE_SIZE (LINE_SIZE), .NUM_BANKS (NUM_BANKS), diff --git a/hw/rtl/cache/VX_cache_bank.sv b/hw/rtl/cache/VX_cache_bank.sv index 937ef63b..55f5087a 100644 --- a/hw/rtl/cache/VX_cache_bank.sv +++ b/hw/rtl/cache/VX_cache_bank.sv @@ -14,7 +14,7 @@ `include "VX_cache_define.vh" module VX_cache_bank #( - parameter `STRING INSTANCE_ID= "", + parameter `STRING INST_ID = "", parameter BANK_ID = 0, // Number of Word requests per cycle @@ -243,7 +243,7 @@ module VX_cache_bank #( `RESET_RELAY (tag_reset, reset); VX_cache_tags #( - .INSTANCE_ID(INSTANCE_ID), + .INST_ID (INST_ID), .BANK_ID (BANK_ID), .CACHE_SIZE (CACHE_SIZE), .LINE_SIZE (LINE_SIZE), @@ -320,7 +320,7 @@ module VX_cache_bank #( `RESET_RELAY (data_reset, reset); VX_cache_data #( - .INSTANCE_ID (INSTANCE_ID), + .INST_ID (INST_ID), .BANK_ID (BANK_ID), .CACHE_SIZE (CACHE_SIZE), .LINE_SIZE (LINE_SIZE), @@ -370,7 +370,7 @@ module VX_cache_bank #( `RESET_RELAY (mshr_reset, reset); VX_cache_mshr #( - .INSTANCE_ID (INSTANCE_ID), + .INST_ID (INST_ID), .BANK_ID (BANK_ID), .LINE_SIZE (LINE_SIZE), .NUM_BANKS (NUM_BANKS), @@ -517,31 +517,31 @@ module VX_cache_bank #( && ~(replay_fire || mem_rsp_fire || core_req_fire); always @(posedge clk) begin if (pipeline_stall) begin - `TRACE(3, ("%d: *** %s-bank%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INSTANCE_ID, BANK_ID, crsq_stall, mreq_alm_full, mshr_alm_full)); + `TRACE(3, ("%d: *** %s-bank%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INST_ID, BANK_ID, crsq_stall, mreq_alm_full, mshr_alm_full)); end if (init_enable) begin - `TRACE(2, ("%d: %s-bank%0d init: addr=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(init_line_sel, BANK_ID))); + `TRACE(2, ("%d: %s-bank%0d init: addr=0x%0h\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(init_line_sel, BANK_ID))); end if (mem_rsp_fire) begin - `TRACE(2, ("%d: %s-bank%0d fill-rsp: addr=0x%0h, mshr_id=%0d, data=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mem_rsp_addr, BANK_ID), mem_rsp_id, mem_rsp_data)); + `TRACE(2, ("%d: %s-bank%0d fill-rsp: addr=0x%0h, mshr_id=%0d, data=0x%0h\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mem_rsp_addr, BANK_ID), mem_rsp_id, mem_rsp_data)); end if (replay_fire) begin - `TRACE(2, ("%d: %s-bank%0d mshr-pop: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(replay_addr, BANK_ID), replay_tag, replay_idx, req_uuid_sel)); + `TRACE(2, ("%d: %s-bank%0d mshr-pop: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(replay_addr, BANK_ID), replay_tag, replay_idx, req_uuid_sel)); end if (core_req_fire) begin if (core_req_rw) - `TRACE(2, ("%d: %s-bank%0d core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, core_req_byteen, core_req_data, req_uuid_sel)); + `TRACE(2, ("%d: %s-bank%0d core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, core_req_byteen, core_req_data, req_uuid_sel)); else - `TRACE(2, ("%d: %s-bank%0d core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, req_uuid_sel)); + `TRACE(2, ("%d: %s-bank%0d core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, req_uuid_sel)); end if (crsq_fire) begin - `TRACE(2, ("%d: %s-bank%0d core-rd-rsp: addr=0x%0h, tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_idx, crsq_data, req_uuid_st1)); + `TRACE(2, ("%d: %s-bank%0d core-rd-rsp: addr=0x%0h, tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_idx, crsq_data, req_uuid_st1)); end if (mreq_push) begin if (do_creq_wr_st1) - `TRACE(2, ("%d: %s-bank%0d writethrough: addr=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_byteen, mreq_data, req_uuid_st1)); + `TRACE(2, ("%d: %s-bank%0d writethrough: addr=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_byteen, mreq_data, req_uuid_st1)); else - `TRACE(2, ("%d: %s-bank%0d fill-req: addr=0x%0h, mshr_id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_id, req_uuid_st1)); + `TRACE(2, ("%d: %s-bank%0d fill-req: addr=0x%0h, mshr_id=%0d (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_id, req_uuid_st1)); end end `endif diff --git a/hw/rtl/cache/VX_cache_data.sv b/hw/rtl/cache/VX_cache_data.sv index 5106d7d5..af2bfc2d 100644 --- a/hw/rtl/cache/VX_cache_data.sv +++ b/hw/rtl/cache/VX_cache_data.sv @@ -14,7 +14,7 @@ `include "VX_cache_define.vh" module VX_cache_data #( - parameter `STRING INSTANCE_ID= "", + parameter `STRING INST_ID = "", parameter BANK_ID = 0, // Size of cache in bytes parameter CACHE_SIZE = 1024, @@ -52,7 +52,7 @@ module VX_cache_data #( output wire [`CS_WORD_WIDTH-1:0] read_data ); - `UNUSED_SPARAM (INSTANCE_ID) + `UNUSED_PARAM (INST_ID) `UNUSED_PARAM (BANK_ID) `UNUSED_PARAM (WORD_SIZE) `UNUSED_VAR (reset) @@ -138,13 +138,13 @@ module VX_cache_data #( `ifdef DBG_TRACE_CACHE_DATA always @(posedge clk) begin if (fill && ~stall) begin - `TRACE(3, ("%d: %s-bank%0d data-fill: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, fill_data)); + `TRACE(3, ("%d: %s-bank%0d data-fill: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, fill_data)); end if (read && ~stall) begin - `TRACE(3, ("%d: %s-bank%0d data-read: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, read_data, req_uuid)); + `TRACE(3, ("%d: %s-bank%0d data-read: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, read_data, req_uuid)); end if (write && ~stall) begin - `TRACE(3, ("%d: %s-bank%0d data-write: addr=0x%0h, way=%b, blk_addr=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, byteen, write_data, req_uuid)); + `TRACE(3, ("%d: %s-bank%0d data-write: addr=0x%0h, way=%b, blk_addr=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, byteen, write_data, req_uuid)); end end `endif diff --git a/hw/rtl/cache/VX_cache_mshr.sv b/hw/rtl/cache/VX_cache_mshr.sv index fa6d4147..ff794ab3 100644 --- a/hw/rtl/cache/VX_cache_mshr.sv +++ b/hw/rtl/cache/VX_cache_mshr.sv @@ -28,7 +28,7 @@ // this is enforced inside the bank by "rdw_hazard_st0". module VX_cache_mshr #( - parameter `STRING INSTANCE_ID= "", + parameter `STRING INST_ID = "", parameter BANK_ID = 0, // Size of line inside a bank in bytes parameter LINE_SIZE = 16, @@ -188,13 +188,13 @@ module VX_cache_mshr #( next_table <= next_table_n; end - `RUNTIME_ASSERT((~allocate_fire || ~valid_table[allocate_id_r]), ("%t: *** %s-bank%0d inuse allocation: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, BANK_ID, + `RUNTIME_ASSERT((~allocate_fire || ~valid_table[allocate_id_r]), ("%t: *** %s-bank%0d inuse allocation: addr=0x%0h, id=%0d (#%0d)", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_id_r, lkp_req_uuid)) - `RUNTIME_ASSERT((~finalize_valid || valid_table[finalize_id]), ("%t: *** %s-bank%0d invalid release: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, BANK_ID, + `RUNTIME_ASSERT((~finalize_valid || valid_table[finalize_id]), ("%t: *** %s-bank%0d invalid release: addr=0x%0h, id=%0d (#%0d)", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(addr_table[finalize_id], BANK_ID), finalize_id, fin_req_uuid)) - `RUNTIME_ASSERT((~fill_valid || valid_table[fill_id]), ("%t: *** %s-bank%0d invalid fill: addr=0x%0h, id=%0d", $time, INSTANCE_ID, BANK_ID, + `RUNTIME_ASSERT((~fill_valid || valid_table[fill_id]), ("%t: *** %s-bank%0d invalid fill: addr=0x%0h, id=%0d", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), fill_id)) VX_dp_ram #( @@ -236,22 +236,22 @@ module VX_cache_mshr #( show_table <= allocate_fire || lookup_valid || finalize_valid || fill_valid || dequeue_fire; end if (allocate_fire) - `TRACE(3, ("%d: %s-bank%0d mshr-allocate: addr=0x%0h, tail=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, + `TRACE(3, ("%d: %s-bank%0d mshr-allocate: addr=0x%0h, tail=%0d, id=%0d (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_tail, allocate_id, lkp_req_uuid)); if (lookup_valid) - `TRACE(3, ("%d: %s-bank%0d mshr-lookup: addr=0x%0h, matches=%b (#%0d)\n", $time, INSTANCE_ID, BANK_ID, + `TRACE(3, ("%d: %s-bank%0d mshr-lookup: addr=0x%0h, matches=%b (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(lookup_addr, BANK_ID), lookup_matches, lkp_req_uuid)); if (finalize_valid) - `TRACE(3, ("%d: %s-bank%0d mshr-finalize release=%b, pending=%b, tail=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, + `TRACE(3, ("%d: %s-bank%0d mshr-finalize release=%b, pending=%b, tail=%0d, id=%0d (#%0d)\n", $time, INST_ID, BANK_ID, finalize_release, finalize_pending, finalize_tail, finalize_id, fin_req_uuid)); if (fill_valid) - `TRACE(3, ("%d: %s-bank%0d mshr-fill: addr=0x%0h, addr=0x%0h, id=%0d\n", $time, INSTANCE_ID, BANK_ID, + `TRACE(3, ("%d: %s-bank%0d mshr-fill: addr=0x%0h, addr=0x%0h, id=%0d\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), `CS_LINE_TO_FULL_ADDR(fill_addr, BANK_ID), fill_id)); if (dequeue_fire) - `TRACE(3, ("%d: %s-bank%0d mshr-dequeue: addr=0x%0h, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, + `TRACE(3, ("%d: %s-bank%0d mshr-dequeue: addr=0x%0h, id=%0d (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(dequeue_addr, BANK_ID), dequeue_id_r, deq_req_uuid)); if (show_table) begin - `TRACE(3, ("%d: %s-bank%0d mshr-table", $time, INSTANCE_ID, BANK_ID)); + `TRACE(3, ("%d: %s-bank%0d mshr-table", $time, INST_ID, BANK_ID)); for (integer i = 0; i < MSHR_SIZE; ++i) begin if (valid_table[i]) begin `TRACE(3, (" %0d=0x%0h", i, `CS_LINE_TO_FULL_ADDR(addr_table[i], BANK_ID))); diff --git a/hw/rtl/cache/VX_cache_tags.sv b/hw/rtl/cache/VX_cache_tags.sv index dac0b6de..37eb0c42 100644 --- a/hw/rtl/cache/VX_cache_tags.sv +++ b/hw/rtl/cache/VX_cache_tags.sv @@ -14,7 +14,7 @@ `include "VX_cache_define.vh" module VX_cache_tags #( - parameter `STRING INSTANCE_ID = "", + parameter `STRING INST_ID = "", parameter BANK_ID = 0, // Size of cache in bytes parameter CACHE_SIZE = 1024, @@ -46,7 +46,7 @@ module VX_cache_tags #( output wire [NUM_WAYS-1:0] way_sel, output wire [NUM_WAYS-1:0] tag_matches ); - `UNUSED_SPARAM (INSTANCE_ID) + `UNUSED_PARAM (INST_ID) `UNUSED_PARAM (BANK_ID) `UNUSED_VAR (reset) `UNUSED_VAR (lookup) @@ -98,16 +98,16 @@ module VX_cache_tags #( `ifdef DBG_TRACE_CACHE_TAG always @(posedge clk) begin if (fill && ~stall) begin - `TRACE(3, ("%d: %s-bank%0d tag-fill: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag)); + `TRACE(3, ("%d: %s-bank%0d tag-fill: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag)); end if (init) begin - `TRACE(3, ("%d: %s-bank%0d tag-init: addr=0x%0h, blk_addr=%0d\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel)); + `TRACE(3, ("%d: %s-bank%0d tag-init: addr=0x%0h, blk_addr=%0d\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel)); end if (lookup && ~stall) begin if (tag_matches != 0) begin - `TRACE(3, ("%d: %s-bank%0d tag-hit: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag, req_uuid)); + `TRACE(3, ("%d: %s-bank%0d tag-hit: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag, req_uuid)); end else begin - `TRACE(3, ("%d: %s-bank%0d tag-miss: addr=0x%0h, blk_addr=%0d, tag_id=0x%0h, (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel, line_tag, req_uuid)); + `TRACE(3, ("%d: %s-bank%0d tag-miss: addr=0x%0h, blk_addr=%0d, tag_id=0x%0h, (#%0d)\n", $time, INST_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel, line_tag, req_uuid)); end end end diff --git a/hw/rtl/cache/VX_cache_top.sv b/hw/rtl/cache/VX_cache_top.sv index 00b2f048..c85ba686 100644 --- a/hw/rtl/cache/VX_cache_top.sv +++ b/hw/rtl/cache/VX_cache_top.sv @@ -14,7 +14,7 @@ `include "VX_cache_define.vh" module VX_cache_top import VX_gpu_pkg::*; #( - parameter `STRING INSTANCE_ID = "", + parameter `STRING INST_ID = "", // Number of Word requests per cycle parameter NUM_REQS = 4, @@ -97,7 +97,7 @@ module VX_cache_top import VX_gpu_pkg::*; #( VX_mem_bus_if #( .DATA_SIZE (WORD_SIZE), .TAG_WIDTH (TAG_WIDTH) - ) core_bus_if[NUM_REQS](); + ) core_bus_if[NUM_REQS-1:0](); VX_mem_bus_if #( .DATA_SIZE (LINE_SIZE), @@ -139,7 +139,7 @@ module VX_cache_top import VX_gpu_pkg::*; #( assign mem_rsp_ready = mem_bus_if.rsp_ready; VX_cache #( - .INSTANCE_ID (INSTANCE_ID), + .INST_ID (INST_ID), .CACHE_SIZE (CACHE_SIZE), .LINE_SIZE (LINE_SIZE), .NUM_BANKS (NUM_BANKS), diff --git a/hw/rtl/core/VX_lsu_unit.sv b/hw/rtl/core/VX_lsu_unit.sv index 7624cd11..d6798138 100644 --- a/hw/rtl/core/VX_lsu_unit.sv +++ b/hw/rtl/core/VX_lsu_unit.sv @@ -326,7 +326,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #( `RESET_RELAY (mem_scheduler_reset, reset); VX_mem_scheduler #( - .INSTANCE_ID ($sformatf("core%0d-lsu-memsched", CORE_ID)), + .INST_ID ($sformatf("core%0d-lsu-memsched", CORE_ID)), .NUM_REQS (LSU_MEM_REQS), .NUM_BANKS (DCACHE_NUM_REQS), .ADDR_WIDTH (DCACHE_ADDR_WIDTH), diff --git a/hw/rtl/core/VX_smem_unit.sv b/hw/rtl/core/VX_smem_unit.sv index 5e82a94d..c3afafae 100644 --- a/hw/rtl/core/VX_smem_unit.sv +++ b/hw/rtl/core/VX_smem_unit.sv @@ -130,7 +130,8 @@ module VX_smem_unit import VX_gpu_pkg::*; #( .clk (clk), .reset (switch_reset), .bus_in_if (dcache_bus_in_if[i]), - .bus_out_if (switch_out_bus_if[i * 2 +: 2]) + .bus_out_if_0 (switch_out_bus_if[i * 2]), + .bus_out_if_1 (switch_out_bus_if[i * 2 + 1]) ); end diff --git a/hw/rtl/fpu/VX_fpu_define.vh b/hw/rtl/fpu/VX_fpu_define.vh index 596db920..e052d5f2 100644 --- a/hw/rtl/fpu/VX_fpu_define.vh +++ b/hw/rtl/fpu/VX_fpu_define.vh @@ -17,8 +17,10 @@ `include "VX_define.vh" `ifdef SV_DPI +`ifndef FPU_FPNEW `include "float_dpi.vh" `endif +`endif `define FPU_MERGE_FFLAGS(out, in, mask, lanes) \ fflags_t __``out; \ diff --git a/hw/rtl/libs/VX_lzc.sv b/hw/rtl/libs/VX_lzc.sv index 7acff819..9261c949 100644 --- a/hw/rtl/libs/VX_lzc.sv +++ b/hw/rtl/libs/VX_lzc.sv @@ -83,7 +83,7 @@ module VX_lzc_rr #( current_idx <= 0; end else begin if (valid_out) begin - current_idx = (current_idx + 1) % N; + current_idx <= (current_idx + 1) % N; end end end diff --git a/hw/rtl/libs/VX_mem_scheduler.sv b/hw/rtl/libs/VX_mem_scheduler.sv index b76d4987..c7a46535 100644 --- a/hw/rtl/libs/VX_mem_scheduler.sv +++ b/hw/rtl/libs/VX_mem_scheduler.sv @@ -15,7 +15,7 @@ `TRACING_OFF module VX_mem_scheduler #( - parameter `STRING INSTANCE_ID = "", + parameter `STRING INST_ID = "", parameter NUM_REQS = 1, parameter NUM_BANKS = 1, parameter ADDR_WIDTH = 32, @@ -522,7 +522,7 @@ module VX_mem_scheduler #( if (pending_req_valids[i]) begin `ASSERT(($time - pending_reqs[i][0 +: 64]) < STALL_TIMEOUT, ("%t: *** %s response timeout: remaining=%b, tag=0x%0h (#%0d)", - $time, INSTANCE_ID, rsp_rem_mask[i], pending_reqs[i][64 +: TAG_ONLY_WIDTH], pending_reqs[i][64+TAG_ONLY_WIDTH +: `UP(UUID_WIDTH)])); + $time, INST_ID, rsp_rem_mask[i], pending_reqs[i][64 +: TAG_ONLY_WIDTH], pending_reqs[i][64+TAG_ONLY_WIDTH +: `UP(UUID_WIDTH)])); end end end @@ -535,39 +535,39 @@ module VX_mem_scheduler #( always @(posedge clk) begin if (req_valid && req_ready) begin if (req_rw) begin - `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INSTANCE_ID, req_mask)); + `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask)); `TRACE_ARRAY1D(1, req_addr, NUM_REQS); `TRACE(1, (", byteen=")); `TRACE_ARRAY1D(1, req_byteen, NUM_REQS); `TRACE(1, (", data=")); `TRACE_ARRAY1D(1, req_data, NUM_REQS); end else begin - `TRACE(1, ("%d: %s-core-req-rd: valid=%b, addr=", $time, INSTANCE_ID, req_mask)); + `TRACE(1, ("%d: %s-core-req-rd: valid=%b, addr=", $time, INST_ID, req_mask)); `TRACE_ARRAY1D(1, req_addr, NUM_REQS); end `TRACE(1, (", tag=0x%0h, tag_only=0x%0h (#%0d)\n", req_tag, req_tag[TAG_ONLY_WIDTH-1:0], req_dbg_uuid)); end if (rsp_valid && rsp_ready) begin - `TRACE(1, ("%d: %s-rsp: valid=%b, sop=%b, eop=%b, data=", $time, INSTANCE_ID, rsp_mask, rsp_sop, rsp_eop)); + `TRACE(1, ("%d: %s-rsp: valid=%b, sop=%b, eop=%b, data=", $time, INST_ID, rsp_mask, rsp_sop, rsp_eop)); `TRACE_ARRAY1D(1, rsp_data, NUM_REQS); `TRACE(1, (", tag=0x%0h, tag_only=0x%0h (#%0d)\n", rsp_tag, rsp_tag[TAG_ONLY_WIDTH-1:0], rsp_dbg_uuid)); end if (| mem_req_fire_s) begin if (| mem_req_rw_s) begin - `TRACE(1, ("%d: %s-mem-req-wr: valid=%b, addr=", $time, INSTANCE_ID, mem_req_fire_s)); + `TRACE(1, ("%d: %s-mem-req-wr: valid=%b, addr=", $time, INST_ID, mem_req_fire_s)); `TRACE_ARRAY1D(1, mem_req_addr_s, NUM_BANKS); `TRACE(1, (", byteen=")); `TRACE_ARRAY1D(1, mem_req_byteen_s, NUM_BANKS); `TRACE(1, (", data=")); `TRACE_ARRAY1D(1, mem_req_data_s, NUM_BANKS); end else begin - `TRACE(1, ("%d: %s-mem-req-rd: valid=%b, addr=", $time, INSTANCE_ID, mem_req_fire_s)); + `TRACE(1, ("%d: %s-mem-req-rd: valid=%b, addr=", $time, INST_ID, mem_req_fire_s)); `TRACE_ARRAY1D(1, mem_req_addr_s, NUM_BANKS); end `TRACE(1, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_waddr, req_batch_idx, mem_req_dbg_uuid)); end if (mem_rsp_fire_s) begin - `TRACE(1, ("%d: %s-mem-rsp: valid=%b, data=", $time, INSTANCE_ID, mem_rsp_mask_s)); + `TRACE(1, ("%d: %s-mem-rsp: valid=%b, data=", $time, INST_ID, mem_rsp_mask_s)); `TRACE_ARRAY1D(1, mem_rsp_data_s, NUM_BANKS); `TRACE(1, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_raddr, rsp_batch_idx, mem_rsp_dbg_uuid)); end diff --git a/hw/rtl/mem/VX_smem_switch.sv b/hw/rtl/mem/VX_smem_switch.sv index 5fb92915..11dd2514 100644 --- a/hw/rtl/mem/VX_smem_switch.sv +++ b/hw/rtl/mem/VX_smem_switch.sv @@ -27,8 +27,9 @@ module VX_smem_switch #( input wire reset, VX_mem_bus_if.slave bus_in_if, - VX_mem_bus_if.master bus_out_if [NUM_REQS] -); + VX_mem_bus_if.master bus_out_if_0, + VX_mem_bus_if.master bus_out_if_1 +); localparam ADDR_WIDTH = (MEM_ADDR_WIDTH-`CLOG2(DATA_SIZE)); localparam DATA_WIDTH = (8 * DATA_SIZE); localparam LOG_NUM_REQS = `CLOG2(NUM_REQS); @@ -77,11 +78,18 @@ module VX_smem_switch #( .ready_out (req_ready_out) ); - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign bus_out_if[i].req_valid = req_valid_out[i]; - assign {bus_out_if[i].req_data.tag, bus_out_if[i].req_data.addr, bus_out_if[i].req_data.rw, bus_out_if[i].req_data.byteen, bus_out_if[i].req_data.data} = req_data_out[i]; - assign req_ready_out[i] = bus_out_if[i].req_ready; - end + // for (genvar i = 0; i < NUM_REQS; ++i) begin + // assign bus_out_if[i].req_valid = req_valid_out[i]; + // assign {bus_out_if[i].req_data.tag, bus_out_if[i].req_data.addr, bus_out_if[i].req_data.rw, bus_out_if[i].req_data.byteen, bus_out_if[i].req_data.data} = req_data_out[i]; + // assign req_ready_out[i] = bus_out_if[i].req_ready; + // end + + assign bus_out_if_0.req_valid = req_valid_out[0]; + assign bus_out_if_1.req_valid = req_valid_out[1]; + assign {bus_out_if_0.req_data.tag, bus_out_if_0.req_data.addr, bus_out_if_0.req_data.rw, bus_out_if_0.req_data.byteen, bus_out_if_0.req_data.data} = req_data_out[0]; + assign {bus_out_if_1.req_data.tag, bus_out_if_1.req_data.addr, bus_out_if_1.req_data.rw, bus_out_if_1.req_data.byteen, bus_out_if_1.req_data.data} = req_data_out[1]; + assign req_ready_out[0] = bus_out_if_0.req_ready; + assign req_ready_out[1] = bus_out_if_1.req_ready; /////////////////////////////////////////////////////////////////////// @@ -92,11 +100,18 @@ module VX_smem_switch #( wire [TAG_OUT_WIDTH-1:0] rsp_tag_in; wire [`UP(LOG_NUM_REQS)-1:0] rsp_sel_in; - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign rsp_valid_out[i] = bus_out_if[i].rsp_valid; - assign rsp_data_out[i] = {bus_out_if[i].rsp_data.tag, bus_out_if[i].rsp_data.data}; - assign bus_out_if[i].rsp_ready = rsp_ready_out[i]; - end + // for (genvar i = 0; i < NUM_REQS; ++i) begin + // assign rsp_valid_out[i] = bus_out_if[i].rsp_valid; + // assign rsp_data_out[i] = {bus_out_if[i].rsp_data.tag, bus_out_if[i].rsp_data.data}; + // assign bus_out_if[i].rsp_ready = rsp_ready_out[i]; + // end + assign rsp_valid_out[0] = bus_out_if_0.rsp_valid; + assign rsp_valid_out[1] = bus_out_if_1.rsp_valid; + assign rsp_data_out[0] = {bus_out_if_0.rsp_data.tag, bus_out_if_0.rsp_data.data}; + assign rsp_data_out[1] = {bus_out_if_1.rsp_data.tag, bus_out_if_1.rsp_data.data}; + assign bus_out_if_0.rsp_ready = rsp_ready_out[0]; + assign bus_out_if_1.rsp_ready = rsp_ready_out[1]; + VX_stream_arb #( .NUM_INPUTS (NUM_REQS), diff --git a/third_party/fpnew b/third_party/fpnew index 79e45313..39ed2d7b 160000 --- a/third_party/fpnew +++ b/third_party/fpnew @@ -1 +1 @@ -Subproject commit 79e453139072df42c9ec8f697132ba485d74e23d +Subproject commit 39ed2d7b53723cece877b73ce4a8ae3ffc4c707e