diff --git a/simX/obj_dir/Vcache_simX b/simX/obj_dir/Vcache_simX
index c373f08a..50fe7187 100755
Binary files a/simX/obj_dir/Vcache_simX and b/simX/obj_dir/Vcache_simX differ
diff --git a/simX/obj_dir/Vcache_simX.cpp b/simX/obj_dir/Vcache_simX.cpp
index 4f758862..93d8b1b4 100644
--- a/simX/obj_dir/Vcache_simX.cpp
+++ b/simX/obj_dir/Vcache_simX.cpp
@@ -36,19 +36,26 @@ VL_ST_SIG(Vcache_simX::__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__
 VL_ST_SIG8(Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[16],1,0);
 VL_ST_SIG8(Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[16],0,0);
 VL_ST_SIG(Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[16],31,0);
+VL_ST_SIG8(Vcache_simX::__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[16],1,0);
+VL_ST_SIG8(Vcache_simX::__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[16],0,0);
+VL_ST_SIG(Vcache_simX::__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[16],31,0);
 
 //--------------------
 
 VL_CTOR_IMP(Vcache_simX) {
     Vcache_simX__Syms* __restrict vlSymsp = __VlSymsp = new Vcache_simX__Syms(this, name());
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    VL_CELL (__PVT__cache_simX__DOT__VX_dram_req_rsp_icache, Vcache_simX_VX_dram_req_rsp_inter__N1_NB4);
+    VL_CELL (__PVT__cache_simX__DOT__VX_dram_req_rsp_icache, Vcache_simX_VX_dram_req_rsp_inter__N4_NB4);
     VL_CELL (__PVT__cache_simX__DOT__VX_dcache_req, Vcache_simX_VX_dcache_request_inter);
     VL_CELL (__PVT__cache_simX__DOT__VX_dram_req_rsp, Vcache_simX_VX_dram_req_rsp_inter__N4_NB4);
     VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi8);
     VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi8);
     VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi8);
     VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi8);
+    VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi9);
+    VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi9);
+    VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi9);
+    VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi9);
     // Reset internal values
     
     // Reset structure values
@@ -132,10 +139,10 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_settle__TOP__2\n"); );
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
+    VL_SIGW(__Vtemp17,127,0,4);
+    VL_SIGW(__Vtemp18,127,0,4);
     VL_SIGW(__Vtemp19,127,0,4);
     VL_SIGW(__Vtemp20,127,0,4);
-    VL_SIGW(__Vtemp21,127,0,4);
-    VL_SIGW(__Vtemp22,127,0,4);
     // Body
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read 
 	= ((IData)(vlTOPp->in_icache_valid_pc_addr)
@@ -161,56 +168,6 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
 	= vlTOPp->in_dcache_in_address[2U];
     vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] 
 	= vlTOPp->in_dcache_in_address[3U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way 
-	= ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) 
-	   | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-	   [0U]);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way 
-	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) 
-	   | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-	      [0U] << 1U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[0U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[1U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[2U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[3U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[4U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[5U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[6U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[7U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x3fffff800000) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) 
-	   | (IData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			     [0U])));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x7fffff) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) 
-	   | ((QData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
-			      [0U])) << 0x17U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way 
-	= ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) 
-	   | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-	   [0U]);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way 
-	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) 
-	   | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
-	      [0U] << 1U));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid 
 	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid)
 	    ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid)
@@ -229,23 +186,13 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
 					      << 8U) 
 					     | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
 						>> 0x18U)))))));
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 0U;
-    if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
-		  >> 1U)))) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 1U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U;
-    }
-    if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U;
-    }
-    // ALWAYS at ../rtl/cache/VX_cache_bank_valid.v:24
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid;
+    // ALWAYS at ../rtl/cache/VX_cache_bank_valid.v:18
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks = 0U;
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1;
+	= (((~ ((IData)(1U) << (3U & (vlTOPp->in_icache_pc_addr 
+				      >> 2U)))) & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid) 
+	      << (3U & (vlTOPp->in_icache_pc_addr >> 2U))));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))
 	    ? (IData)(vlTOPp->in_dcache_mem_read) : 7U);
@@ -279,10 +226,31 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
 	    : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid));
     // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:17
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index = 0U;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 0U;
-    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) {
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found = 0U;
+    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks))) {
 	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 1U;
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found = 1U;
+    }
+    // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:17
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index = 0U;
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found = 0U;
+    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks))) {
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index = 0U;
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found = 1U;
+    }
+    // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:17
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index = 0U;
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found = 0U;
+    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks))) {
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index = 0U;
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found = 1U;
+    }
+    // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:17
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index = 0U;
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found = 0U;
+    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks))) {
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index = 0U;
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found = 1U;
     }
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
@@ -319,21 +287,56 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
 		     >> 3U)) << (0xfU & ((IData)(3U) 
 					 + (0xcU & 
 					    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U])))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in 
-	= (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-	    & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
-	   | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-		  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
-	      & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-		 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-	= ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
-	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
-	    : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
-	        ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
-	        : (vlTOPp->in_icache_pc_addr >> (0x1fU 
-						 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) 
-						    << 5U)))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank 
+	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank)) 
+	   | (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)
+		     ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index))
+		     : 0U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank 
+	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)) 
+	   | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank 
+	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank)) 
+	   | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank 
+	= ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank)) 
+	   | (2U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)
+		      ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index))
+		      : 0U) << 1U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank 
+	= ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found) 
+	      << 1U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank 
+	= ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index) 
+	      << 1U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank 
+	= ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank)) 
+	   | (4U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)
+		      ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index))
+		      : 0U) << 2U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank 
+	= ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found) 
+	      << 2U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank 
+	= ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index) 
+	      << 2U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank 
+	= ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank)) 
+	   | (8U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)
+		      ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index))
+		      : 0U) << 3U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank 
+	= ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found) 
+	      << 3U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank 
+	= ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index) 
+	      << 3U));
     // ALWAYS at ../rtl/shared_memory/VX_bank_valids.v:22
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
 	= ((0xfffeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
@@ -506,28 +509,61 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i 
 	= vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i
 	[vlTOPp->__Vtableidx9];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access 
-	= ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-	   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem 
-	= ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-	   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way 
-	= ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) 
-	   | (1U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
-		     & ((0x7fffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way)) 
-			== (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-					 >> 9U)))) ? 1U
-		     : 0U)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way 
-	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) 
-	   | (2U & (((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
-		       >> 1U) & ((0x7fffffU & (IData)(
-						      (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
-						       >> 0x17U))) 
-				 == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-						  >> 9U))))
-		      ? 1U : 0U) << 1U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in 
+	= (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+	    & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
+	   | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
+	      & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in 
+	= (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+	    & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
+	   | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
+	      & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+		    >> 1U))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in 
+	= (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+	    & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
+	   | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
+	      & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+		    >> 2U))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in 
+	= (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+	    & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
+	   | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
+	      & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+		    >> 3U))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+	= ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	    : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	        ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	        : vlTOPp->in_icache_pc_addr));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+	= ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	    : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	        ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	        : vlTOPp->in_icache_pc_addr));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+	= ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	    : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	        ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	        : vlTOPp->in_icache_pc_addr));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+	= ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	    : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	        ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	        : vlTOPp->in_icache_pc_addr));
     // ALWAYS at ../rtl/VX_countones.v:14
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids = 0U;
     if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
@@ -697,49 +733,6 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
 	= ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) 
 	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index) 
 	      << 6U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U] 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0U]
-	    : 0U);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U] 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[1U]
-	    : 0U);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U] 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[2U]
-	    : 0U);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U] 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[3U]
-	    : 0U);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
-	= ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
-	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	       ? 0xfU : 0U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
-	= ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
-	   | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	        ? 0xfU : 0U) << 4U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
-	= ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
-	   | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	        ? 0xfU : 0U) << 8U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
-	= ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
-	   | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	        ? 0xfU : 0U) << 0xcU));
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
-    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 1U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
-    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid 
 	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
 	   | (1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
@@ -847,26 +840,6 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
 	        : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
 	       (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 		      >> 6U))]));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual 
-	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
-	    ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update)
-	    : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index));
     // ALWAYS at ../rtl/shared_memory/VX_priority_encoder_sm.v:88
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced = 0U;
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced 
@@ -884,37 +857,37 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
 	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) 
 	   | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
 				    >> 6U))));
+    __Vtemp17[0U] = 0U;
+    __Vtemp17[1U] = 0U;
+    __Vtemp17[2U] = 0U;
+    __Vtemp17[3U] = 0U;
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U] 
+	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
+	    ? __Vtemp17[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))]
+	    : 0U);
+    __Vtemp18[0U] = 0U;
+    __Vtemp18[1U] = 0U;
+    __Vtemp18[2U] = 0U;
+    __Vtemp18[3U] = 0U;
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U] 
+	= ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
+	    ? __Vtemp18[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
+			       >> 2U))] : 0U);
     __Vtemp19[0U] = 0U;
     __Vtemp19[1U] = 0U;
     __Vtemp19[2U] = 0U;
     __Vtemp19[3U] = 0U;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U] 
-	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
-	    ? __Vtemp19[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))]
-	    : 0U);
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U] 
+	= ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
+	    ? __Vtemp19[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
+			       >> 4U))] : 0U);
     __Vtemp20[0U] = 0U;
     __Vtemp20[1U] = 0U;
     __Vtemp20[2U] = 0U;
     __Vtemp20[3U] = 0U;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U] 
-	= ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
-	    ? __Vtemp20[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
-			       >> 2U))] : 0U);
-    __Vtemp21[0U] = 0U;
-    __Vtemp21[1U] = 0U;
-    __Vtemp21[2U] = 0U;
-    __Vtemp21[3U] = 0U;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U] 
-	= ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
-	    ? __Vtemp21[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
-			       >> 4U))] : 0U);
-    __Vtemp22[0U] = 0U;
-    __Vtemp22[1U] = 0U;
-    __Vtemp22[2U] = 0U;
-    __Vtemp22[3U] = 0U;
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U] 
 	= ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
-	    ? __Vtemp22[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
+	    ? __Vtemp20[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
 			       >> 6U))] : 0U);
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
 	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
@@ -951,114 +924,6 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
 	= ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) 
 	   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) 
 	      >> 3U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way 
-	= ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) 
-	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) 
-	      & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
-	= ((0xffff0000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) 
-	   | (0xffffU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)
-			  ? 0U : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way 
-	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) 
-	   | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) 
-	       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)) 
-	      << 1U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
-	= ((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) 
-	   | (0xffff0000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)
-			       ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)
-			       : 0U) << 0x10U)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual 
-	= (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) 
-	    | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))
-	    ? (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-				 << 7U))) ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-						  ((IData)(1U) 
-						   + 
-						   (4U 
-						    & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						       << 2U)))] 
-						  << 
-						  ((IData)(0x20U) 
-						   - 
-						   (0x1fU 
-						    & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						       << 7U))))) 
-	       | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-		  (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-			 << 2U))] >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					       << 7U))))
-	    : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-	        ? ((((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-				      << 7U))) ? 0U
-		      : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-			 ((IData)(1U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					       << 2U)))] 
-			 << ((IData)(0x20U) - (0x1fU 
-					       & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						  << 7U))))) 
-		    | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-		       (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-			      << 2U))] >> (0x1fU & 
-					   ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					    << 7U)))) 
-		   >> 8U) : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-			      ? ((((0U == (0x1fU & 
-					   ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					    << 7U)))
-				    ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-					    ((IData)(1U) 
-					     + (4U 
-						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						   << 2U)))] 
-					    << ((IData)(0x20U) 
-						- (0x1fU 
-						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						      << 7U))))) 
-				  | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-				     (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					    << 2U))] 
-				     >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						  << 7U)))) 
-				 >> 0x10U) : ((((0U 
-						 == 
-						 (0x1fU 
-						  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						     << 7U)))
-						 ? 0U
-						 : 
-						(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-						 ((IData)(1U) 
-						  + 
-						  (4U 
-						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						      << 2U)))] 
-						 << 
-						 ((IData)(0x20U) 
-						  - 
-						  (0x1fU 
-						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						      << 7U))))) 
-					       | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-						  (4U 
-						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						      << 2U))] 
-						  >> 
-						  (0x1fU 
-						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						      << 7U)))) 
-					      >> 0x18U))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
-	= (0x7fffffU & ((0x2dU >= (0x3fU & ((IData)(0x17U) 
-					    * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))
-			 ? (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
-				    >> (0x3fU & ((IData)(0x17U) 
-						 * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))))
-			 : 0U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use 
-	= (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
-		 >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual 
 	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) 
 	   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced));
@@ -1138,21 +1003,6 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
 	    ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 	   [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 		      >> 0x15U))][3U]);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) 
-		 | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
-					      >> 0x10U)))) 
-		 | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
-		    >> 1U)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank 
-	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) 
-	    & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
-	       == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-				>> 9U)))) & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests 
 	= ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
 	    ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) 
@@ -1557,73 +1407,166 @@ void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) {
 	    }
 	}
     }
-    // ALWAYS at ../rtl/cache/VX_d_cache.v:183
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = 0U;
-    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read 
-	    = (((~ ((IData)(0xffffffffU) << (0x1fU 
-					     & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) 
-						<< 5U)))) 
-		& vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read) 
-	       | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)
-		    ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-		        ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			    ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			    : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
-		        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-			    ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			        ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			        : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
-			    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-			        ? (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-				    ? (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				    : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))
-		    : 0U) << (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) 
-				       << 5U))));
-    }
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
-	   & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank;
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 0U;
-    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 1U;
-    }
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state 
-	= (0xfU & (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-		    & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss))
-		    ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
-			     ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-				      & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))
-				      ? 2U : 0U))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank 
-	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)
-	     ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index))
-	     : 0U) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask
-	   [0U]);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict 
-	= ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-	   & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)
-	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read
-	    : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid) 
-	   & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)));
-    vlTOPp->out_icache_stall = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) 
-				| (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)));
 }
 
 VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_settle__TOP__3\n"); );
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb 
+	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb)) 
+	   | (1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+		    >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[0U] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[1U] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[2U] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[3U] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank[0U] 
+	= ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
+	    << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank 
+	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)) 
+	   | (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) 
+	       & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
+		  == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+				   >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[0U] 
+	= ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
+	    ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+	        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+		    ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+		    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
+	        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+		    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+		        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+		        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
+		    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+		        ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+		        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+			    ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+			    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))
+	    : 0U);
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb 
+	= ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb)) 
+	   | (2U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+		     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) 
+		    << 1U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[4U] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[5U] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[6U] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[7U] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank[1U] 
+	= ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
+	    << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank 
+	= ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)) 
+	   | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) 
+		& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
+		   == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+				    >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)) 
+	      << 1U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[1U] 
+	= ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
+	    ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+	        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+		    ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+		    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
+	        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+		    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+		        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+		        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
+		    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+		        ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+		        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+			    ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+			    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))
+	    : 0U);
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb 
+	= ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb)) 
+	   | (4U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+		     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) 
+		    << 2U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[8U] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[9U] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[0xaU] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[0xbU] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank[2U] 
+	= ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
+	    << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank 
+	= ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)) 
+	   | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) 
+		& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
+		   == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+				    >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)) 
+	      << 2U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[2U] 
+	= ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
+	    ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+	        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+		    ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+		    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
+	        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+		    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+		        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+		        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
+		    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+		        ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+		        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+			    ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+			    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))
+	    : 0U);
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb 
+	= ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb)) 
+	   | (8U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+		     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) 
+		    << 3U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[0xcU] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[0xdU] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[0xeU] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata[0xfU] 
+	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank[3U] 
+	= ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
+	    << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank 
+	= ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)) 
+	   | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) 
+		& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
+		   == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+				    >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)) 
+	      << 3U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[3U] 
+	= ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
+	    ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+	        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+		    ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+		    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
+	        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+		    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+		        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+		        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
+		    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+		        ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+		        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+			    ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+			    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))
+	    : 0U);
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb 
 	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) 
 	   | (1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
@@ -1637,8 +1580,8 @@ VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vl
     vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[3U] 
 	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[0U] 
-	= (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
-	   << 0xbU);
+	= ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
+	    << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank 
 	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) 
 	   | (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) 
@@ -1675,8 +1618,8 @@ VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vl
     vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[7U] 
 	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[1U] 
-	= (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
-	   << 0xbU);
+	= ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
+	    << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank 
 	= ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) 
 	   | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) 
@@ -1714,8 +1657,8 @@ VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vl
     vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xbU] 
 	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[2U] 
-	= (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
-	   << 0xbU);
+	= ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
+	    << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank 
 	= ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) 
 	   | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) 
@@ -1753,8 +1696,8 @@ VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vl
     vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xfU] 
 	= vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U];
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[3U] 
-	= (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
-	   << 0xbU);
+	= ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
+	    << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank 
 	= ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) 
 	   | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) 
@@ -1778,6 +1721,38 @@ VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vl
 			    ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 			    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))
 	    : 0U);
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss 
+	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+	   & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0U] 
+	= (1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[1U] 
+	= (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) 
+		 >> 1U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[2U] 
+	= (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) 
+		 >> 2U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[3U] 
+	= (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) 
+		 >> 3U));
+    // ALWAYS at ../rtl/cache/VX_d_cache.v:183
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = 0U;
+    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank))) {
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read 
+	    = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[0U];
+    }
+    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank))) {
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read 
+	    = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[1U];
+    }
+    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank))) {
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read 
+	    = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[2U];
+    }
+    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank))) {
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read 
+	    = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[3U];
+    }
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss 
 	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
 	   & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)));
@@ -1817,6 +1792,44 @@ VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vl
 				       >> 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, 
 			  vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U]);
     }
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state 
+	= (0xfU & (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		    & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss)))
+		    ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+			     ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+				      & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))
+				      ? 2U : 0U))));
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:16
+    vlTOPp->__Vtableidx10 = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss;
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index 
+	= vlTOPp->__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index
+	[vlTOPp->__Vtableidx10];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found 
+	= vlTOPp->__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found
+	[vlTOPp->__Vtableidx10];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i 
+	= vlTOPp->__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i
+	[vlTOPp->__Vtableidx10];
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank 
+	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank) 
+	      & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask
+	      [0U]));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank 
+	= ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)) 
+	   | (0xfffffffeU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank) 
+			     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask
+				[1U] << 1U))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank 
+	= ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)) 
+	   | (0xfffffffcU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank) 
+			     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask
+				[2U] << 2U))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank 
+	= ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)) 
+	   | (0xfffffff8U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank) 
+			     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask
+				[3U] << 3U))));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state 
 	= (0xfU & (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 		    & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss)))
@@ -1855,6 +1868,24 @@ VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vl
 	   | (0xfffff000U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) 
 			     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask
 				[3U] << 0xcU))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict 
+	= ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+	   & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state)));
+    // ALWAYS at ../rtl/cache/VX_d_cache.v:203
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual 
+	= (1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual 
+	= (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual) 
+		 | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank) 
+		    >> 1U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual 
+	= (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual) 
+		 | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank) 
+		    >> 2U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual 
+	= (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual) 
+		 | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank) 
+		    >> 3U)));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__update_global_way_to_evict 
 	= ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 	   & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state)));
@@ -1873,6 +1904,13 @@ VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vl
 	= (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual) 
 		   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank) 
 		      >> 0xcU)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual 
+	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual)
+	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read
+	    : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read);
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid 
+	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid) 
+	   & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual)));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U] 
 	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual))
 	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[0U]
@@ -1892,6 +1930,8 @@ VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vl
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid 
 	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) 
 	   & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual)));
+    vlTOPp->out_icache_stall = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) 
+				| (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)));
     vlTOPp->out_dcache_stall = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
 				| ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
 				   | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))));
@@ -1905,161 +1945,15 @@ VL_INLINE_OPT void Vcache_simX::_sequent__TOP__4(Vcache_simX__Syms* __restrict v
     VL_SIG8(__Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict,0,0);
     VL_SIG8(__Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__state,3,0);
     VL_SIG8(__Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict,0,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0,0,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32,0,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32,0,0);
-    VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,6,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,7,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,0,0);
-    VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,6,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,7,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,0,0);
-    VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,6,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,7,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,0,0);
-    VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,6,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,7,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,0,0);
-    VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,6,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,7,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,0,0);
-    VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,6,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,7,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,0,0);
-    VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,6,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,7,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,0,0);
-    VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,6,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,7,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,0,0);
-    VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,6,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,7,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,0,0);
-    VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,6,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,7,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,0,0);
-    VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,6,0);
-    VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,7,0);
-    VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,0,0);
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-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0U;
-    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 0U;
     __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict 
 	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict;
+    __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state 
+	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state;
     // ALWAYS at ../rtl/shared_memory/VX_shared_memory_block.v:36
     if (vlTOPp->reset) {
 	vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind = 0U;
@@ -2257,8 +2151,6 @@ VL_INLINE_OPT void Vcache_simX::_sequent__TOP__4(Vcache_simX__Syms* __restrict v
 	vlTOPp->cache_simX__DOT__dcache_i_m_ready = 
 	    (1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state));
     }
-    __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state;
     // ALWAYS at ../rtl/shared_memory/VX_priority_encoder_sm.v:105
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests 
 	= ((IData)(vlTOPp->reset) ? 0U : ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))
@@ -2281,300 +2173,13 @@ VL_INLINE_OPT void Vcache_simX::_sequent__TOP__4(Vcache_simX__Syms* __restrict v
 	if ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))) {
 	    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr 
 		= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found)
-		    ? (vlTOPp->in_icache_pc_addr >> 
-		       (0x1fU & (((0U >= (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index)) 
-				  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) 
-				     >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index))) 
-				 << 5U))) : 0U);
+		    ? vlTOPp->in_icache_pc_addr : 0U);
 	}
 	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read 
 	    = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual;
 	__Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__state 
 	    = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state;
     }
-    // ALWAYS at ../rtl/cache/VX_cache_data.v:79
-    if (vlTOPp->reset) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = 0x20U;
-	__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 1U;
-    } else {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U;
-	if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 
-		= (1U & ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
-			  ? 0U : (0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
-	}
-	if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 
-		= (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-				>> 9U));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U;
-	}
-	if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) {
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U;
-	}
-	if ((1U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 
-		= (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U]);
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U;
-	}
-	if ((2U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
-			     << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] 
-					  >> 8U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 8U;
-	}
-	if ((4U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
-			     << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] 
-					  >> 0x10U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
-	}
-	if ((8U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
-			     << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] 
-				       >> 0x18U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
-	}
-	if ((0x10U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 
-		= (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U]);
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
-	}
-	if ((0x20U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
-			     << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
-					  >> 8U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
-	}
-	if ((0x40U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
-			     << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
-					  >> 0x10U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
-	}
-	if ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
-			     << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
-				       >> 0x18U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
-	}
-	if ((0x100U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 
-		= (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U]);
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
-	}
-	if ((0x200U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
-			     << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
-					  >> 8U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
-	}
-	if ((0x400U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
-			     << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
-					  >> 0x10U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
-	}
-	if ((0x800U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
-			     << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
-				       >> 0x18U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0x58U;
-	}
-	if ((0x1000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 
-		= (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U]);
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0x60U;
-	}
-	if ((0x2000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
-			     << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
-					  >> 8U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0x68U;
-	}
-	if ((0x4000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
-			     << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
-					  >> 0x10U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0x70U;
-	}
-	if ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
-			     << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
-				       >> 0x18U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0x78U;
-	}
-    }
-    // ALWAYS at ../rtl/cache/VX_cache_data.v:79
-    if (vlTOPp->reset) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = 0x20U;
-	__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U;
-    } else {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U;
-	if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 
-		= (1U & ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
-			  ? 0U : (0U != (0xffffU & 
-					 (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
-					  >> 0x10U)))));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
-	}
-	if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 
-		= (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-				>> 9U));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U;
-	}
-	if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) {
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U;
-	}
-	if ((0x10000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 
-		= (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U]);
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U;
-	}
-	if ((0x20000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
-			     << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
-					  >> 8U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U;
-	}
-	if ((0x40000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
-			     << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
-					  >> 0x10U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
-	}
-	if ((0x80000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
-			     << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
-				       >> 0x18U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
-	}
-	if ((0x100000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 
-		= (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U]);
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
-	}
-	if ((0x200000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
-			     << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
-					  >> 8U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
-	}
-	if ((0x400000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
-			     << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
-					  >> 0x10U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
-	}
-	if ((0x800000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
-			     << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
-				       >> 0x18U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
-	}
-	if ((0x1000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 
-		= (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U]);
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
-	}
-	if ((0x2000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
-			     << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
-					  >> 8U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
-	}
-	if ((0x4000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
-			     << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
-					  >> 0x10U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
-	}
-	if ((0x8000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 
-		= (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
-			     << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
-				       >> 0x18U)));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0x58U;
-	}
-	if ((0x10000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 
-		= (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U]);
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0x60U;
-	}
-	if ((0x20000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 
-		= (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
-			    >> 8U));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0x68U;
-	}
-	if ((0x40000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 
-		= (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
-			    >> 0x10U));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0x70U;
-	}
-	if ((0x80000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) {
-	    __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 
-		= (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
-			    >> 0x18U));
-	    __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 1U;
-	    __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0x78U;
-	}
-    }
     // ALWAYS at ../rtl/cache/VX_d_cache.v:251
     if (vlTOPp->reset) {
 	vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[0U] = 0U;
@@ -2615,736 +2220,20 @@ VL_INLINE_OPT void Vcache_simX::_sequent__TOP__4(Vcache_simX__Syms* __restrict v
 	= __Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict;
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state 
 	= __Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__state;
-    // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[4U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[5U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[6U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[7U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[8U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[9U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U;
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-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] 
-	    = __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32;
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-    // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
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-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xfU][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xfU][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xfU][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xfU][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x10U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x10U][1U] = 0U;
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-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38) {
-	VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38), 
-			  vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38);
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39) {
-	VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39), 
-			  vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39);
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40) {
-	VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40), 
-			  vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40);
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41) {
-	VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41), 
-			  vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41);
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) {
-	VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), 
-			  vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42);
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) {
-	VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), 
-			  vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43);
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) {
-	VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), 
-			  vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44);
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) {
-	VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), 
-			  vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45);
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) {
-	VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), 
-			  vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46);
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) {
-	VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), 
-			  vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47);
-    }
-    // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[4U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[5U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[6U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[7U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[8U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[9U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xaU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xbU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xcU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xdU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xeU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xfU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x10U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x11U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x12U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x13U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x14U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x15U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x16U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x17U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x18U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x19U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U;
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] 
-	    = __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32;
-    }
-    // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[4U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[5U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[6U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[7U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[8U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[9U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xaU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xbU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xcU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xdU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xeU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xfU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x10U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x11U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x12U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x13U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x14U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x15U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x16U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x17U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x18U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x19U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1aU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1bU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U;
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 1U;
-    }
-    // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[4U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[5U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[6U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[7U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[8U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[9U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U;
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] 
-	    = __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32;
-    }
-    // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][1U] = 0U;
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-    }
-    // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[4U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[5U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[6U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[7U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[8U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[9U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xaU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xbU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xcU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xdU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xeU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xfU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x10U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x11U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x12U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x13U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x14U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x15U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x16U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x17U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x18U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x19U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U;
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] 
-	    = __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32;
-    }
-    // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[1U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[2U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[3U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[4U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[5U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[6U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[7U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[8U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[9U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xaU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xbU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xcU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xdU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xeU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xfU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x10U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x11U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x12U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x13U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x14U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x15U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x16U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x17U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x18U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x19U] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1aU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1bU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U;
-    }
-    if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 1U;
-    }
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict 
 	= __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict;
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state 
 	= __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way 
-	= ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) 
-	   | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-	   [0U]);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[0U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[1U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[2U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[3U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x3fffff800000) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) 
-	   | (IData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			     [0U])));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way 
-	= ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) 
-	   | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-	   [0U]);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way 
-	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) 
-	   | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-	      [0U] << 1U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[4U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[5U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[6U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[7U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x7fffff) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) 
-	   | ((QData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
-			      [0U])) << 0x17U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way 
-	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) 
-	   | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
-	      [0U] << 1U));
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 0U;
-    if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
-		  >> 1U)))) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 1U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U;
-    }
-    if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U;
-    }
 }
 
 VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    Vcache_simX::_combo__TOP__5\n"); );
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
-    VL_SIGW(__Vtemp128,127,0,4);
-    VL_SIGW(__Vtemp129,127,0,4);
-    VL_SIGW(__Vtemp130,127,0,4);
-    VL_SIGW(__Vtemp131,127,0,4);
+    VL_SIGW(__Vtemp63,127,0,4);
+    VL_SIGW(__Vtemp64,127,0,4);
+    VL_SIGW(__Vtemp65,127,0,4);
+    VL_SIGW(__Vtemp66,127,0,4);
     // Body
     vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
 	= vlTOPp->in_dcache_in_address[0U];
@@ -3372,11 +2261,13 @@ VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlS
 					      << 8U) 
 					     | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
 						>> 0x18U)))))));
-    // ALWAYS at ../rtl/cache/VX_cache_bank_valid.v:24
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid;
+    // ALWAYS at ../rtl/cache/VX_cache_bank_valid.v:18
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks = 0U;
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1;
+	= (((~ ((IData)(1U) << (3U & (vlTOPp->in_icache_pc_addr 
+				      >> 2U)))) & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid) 
+	      << (3U & (vlTOPp->in_icache_pc_addr >> 2U))));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))
 	    ? (IData)(vlTOPp->in_dcache_mem_read) : 7U);
@@ -3410,10 +2301,31 @@ VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlS
 	    : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid));
     // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:17
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index = 0U;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 0U;
-    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) {
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found = 0U;
+    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks))) {
 	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 1U;
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found = 1U;
+    }
+    // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:17
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index = 0U;
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found = 0U;
+    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks))) {
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index = 0U;
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found = 1U;
+    }
+    // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:17
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index = 0U;
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found = 0U;
+    if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks))) {
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index = 0U;
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found = 1U;
+    }
+    // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:17
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index = 0U;
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found = 0U;
+    if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks))) {
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index = 0U;
+	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found = 1U;
     }
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
@@ -3450,21 +2362,56 @@ VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlS
 		     >> 3U)) << (0xfU & ((IData)(3U) 
 					 + (0xcU & 
 					    vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U])))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in 
-	= (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-	    & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
-	   | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-		  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
-	      & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-		 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-	= ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
-	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
-	    : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
-	        ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
-	        : (vlTOPp->in_icache_pc_addr >> (0x1fU 
-						 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) 
-						    << 5U)))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank 
+	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank)) 
+	   | (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)
+		     ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index))
+		     : 0U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank 
+	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)) 
+	   | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank 
+	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank)) 
+	   | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank 
+	= ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank)) 
+	   | (2U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)
+		      ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index))
+		      : 0U) << 1U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank 
+	= ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found) 
+	      << 1U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank 
+	= ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index) 
+	      << 1U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank 
+	= ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank)) 
+	   | (4U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)
+		      ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index))
+		      : 0U) << 2U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank 
+	= ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found) 
+	      << 2U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank 
+	= ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index) 
+	      << 2U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank 
+	= ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank)) 
+	   | (8U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)
+		      ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index))
+		      : 0U) << 3U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank 
+	= ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found) 
+	      << 3U));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank 
+	= ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank)) 
+	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index) 
+	      << 3U));
     // ALWAYS at ../rtl/shared_memory/VX_bank_valids.v:22
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids 
 	= ((0xfffeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) 
@@ -3637,28 +2584,61 @@ VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlS
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i 
 	= vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i
 	[vlTOPp->__Vtableidx9];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access 
-	= ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-	   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem 
-	= ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-	   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way 
-	= ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) 
-	   | (1U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
-		     & ((0x7fffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way)) 
-			== (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-					 >> 9U)))) ? 1U
-		     : 0U)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way 
-	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) 
-	   | (2U & (((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
-		       >> 1U) & ((0x7fffffU & (IData)(
-						      (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
-						       >> 0x17U))) 
-				 == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-						  >> 9U))))
-		      ? 1U : 0U) << 1U)));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in 
+	= (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+	    & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
+	   | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
+	      & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in 
+	= (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+	    & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
+	   | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
+	      & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+		    >> 1U))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in 
+	= (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+	    & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
+	   | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
+	      & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+		    >> 2U))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in 
+	= (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+	    & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) 
+	   | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		  & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) 
+	      & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+		 & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+		    >> 3U))));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+	= ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	    : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	        ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	        : vlTOPp->in_icache_pc_addr));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+	= ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	    : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	        ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	        : vlTOPp->in_icache_pc_addr));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+	= ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	    : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	        ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	        : vlTOPp->in_icache_pc_addr));
+    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+	= ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	    : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
+	        ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr
+	        : vlTOPp->in_icache_pc_addr));
     // ALWAYS at ../rtl/VX_countones.v:14
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids = 0U;
     if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) {
@@ -3828,49 +2808,6 @@ VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlS
 	= ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) 
 	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index) 
 	      << 6U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U] 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0U]
-	    : 0U);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U] 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[1U]
-	    : 0U);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U] 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[2U]
-	    : 0U);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U] 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[3U]
-	    : 0U);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
-	= ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
-	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	       ? 0xfU : 0U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
-	= ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
-	   | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	        ? 0xfU : 0U) << 4U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
-	= ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
-	   | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	        ? 0xfU : 0U) << 8U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we 
-	= ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) 
-	   | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)
-	        ? 0xfU : 0U) << 0xcU));
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
-    if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 1U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
-    if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid 
 	= ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
 	   | (1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids)));
@@ -3978,26 +2915,6 @@ VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlS
 	        : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
 	       (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 		      >> 6U))]));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U];
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual 
-	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
-	    ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update)
-	    : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index));
     // ALWAYS at ../rtl/shared_memory/VX_priority_encoder_sm.v:88
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced = 0U;
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced 
@@ -4015,38 +2932,38 @@ VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlS
 	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) 
 	   | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
 				    >> 6U))));
-    __Vtemp128[0U] = 0U;
-    __Vtemp128[1U] = 0U;
-    __Vtemp128[2U] = 0U;
-    __Vtemp128[3U] = 0U;
+    __Vtemp63[0U] = 0U;
+    __Vtemp63[1U] = 0U;
+    __Vtemp63[2U] = 0U;
+    __Vtemp63[3U] = 0U;
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U] 
 	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
-	    ? __Vtemp128[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))]
+	    ? __Vtemp63[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))]
 	    : 0U);
-    __Vtemp129[0U] = 0U;
-    __Vtemp129[1U] = 0U;
-    __Vtemp129[2U] = 0U;
-    __Vtemp129[3U] = 0U;
+    __Vtemp64[0U] = 0U;
+    __Vtemp64[1U] = 0U;
+    __Vtemp64[2U] = 0U;
+    __Vtemp64[3U] = 0U;
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U] 
 	= ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
-	    ? __Vtemp129[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
-				>> 2U))] : 0U);
-    __Vtemp130[0U] = 0U;
-    __Vtemp130[1U] = 0U;
-    __Vtemp130[2U] = 0U;
-    __Vtemp130[3U] = 0U;
+	    ? __Vtemp64[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
+			       >> 2U))] : 0U);
+    __Vtemp65[0U] = 0U;
+    __Vtemp65[1U] = 0U;
+    __Vtemp65[2U] = 0U;
+    __Vtemp65[3U] = 0U;
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U] 
 	= ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
-	    ? __Vtemp130[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
-				>> 4U))] : 0U);
-    __Vtemp131[0U] = 0U;
-    __Vtemp131[1U] = 0U;
-    __Vtemp131[2U] = 0U;
-    __Vtemp131[3U] = 0U;
+	    ? __Vtemp65[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
+			       >> 4U))] : 0U);
+    __Vtemp66[0U] = 0U;
+    __Vtemp66[1U] = 0U;
+    __Vtemp66[2U] = 0U;
+    __Vtemp66[3U] = 0U;
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U] 
 	= ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
-	    ? __Vtemp131[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
-				>> 6U))] : 0U);
+	    ? __Vtemp66[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) 
+			       >> 6U))] : 0U);
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] 
 	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))
 	    ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[
@@ -4082,114 +2999,6 @@ VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlS
 	= ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) 
 	   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) 
 	      >> 3U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way 
-	= ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) 
-	   | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) 
-	      & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
-	= ((0xffff0000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) 
-	   | (0xffffU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)
-			  ? 0U : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way 
-	= ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) 
-	   | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) 
-	       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)) 
-	      << 1U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
-	= ((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) 
-	   | (0xffff0000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)
-			       ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)
-			       : 0U) << 0x10U)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual 
-	= (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) 
-	    | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))
-	    ? (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-				 << 7U))) ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-						  ((IData)(1U) 
-						   + 
-						   (4U 
-						    & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						       << 2U)))] 
-						  << 
-						  ((IData)(0x20U) 
-						   - 
-						   (0x1fU 
-						    & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						       << 7U))))) 
-	       | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-		  (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-			 << 2U))] >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					       << 7U))))
-	    : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-	        ? ((((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-				      << 7U))) ? 0U
-		      : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-			 ((IData)(1U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					       << 2U)))] 
-			 << ((IData)(0x20U) - (0x1fU 
-					       & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						  << 7U))))) 
-		    | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-		       (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-			      << 2U))] >> (0x1fU & 
-					   ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					    << 7U)))) 
-		   >> 8U) : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-			      ? ((((0U == (0x1fU & 
-					   ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					    << 7U)))
-				    ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-					    ((IData)(1U) 
-					     + (4U 
-						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						   << 2U)))] 
-					    << ((IData)(0x20U) 
-						- (0x1fU 
-						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						      << 7U))))) 
-				  | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-				     (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					    << 2U))] 
-				     >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						  << 7U)))) 
-				 >> 0x10U) : ((((0U 
-						 == 
-						 (0x1fU 
-						  & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						     << 7U)))
-						 ? 0U
-						 : 
-						(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-						 ((IData)(1U) 
-						  + 
-						  (4U 
-						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						      << 2U)))] 
-						 << 
-						 ((IData)(0x20U) 
-						  - 
-						  (0x1fU 
-						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						      << 7U))))) 
-					       | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-						  (4U 
-						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						      << 2U))] 
-						  >> 
-						  (0x1fU 
-						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-						      << 7U)))) 
-					      >> 0x18U))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
-	= (0x7fffffU & ((0x2dU >= (0x3fU & ((IData)(0x17U) 
-					    * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))
-			 ? (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way 
-				    >> (0x3fU & ((IData)(0x17U) 
-						 * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))))
-			 : 0U));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use 
-	= (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) 
-		 >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual 
 	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) 
 	   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced));
@@ -4269,21 +3078,6 @@ VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlS
 	    ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 	   [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 		      >> 0x15U))][3U]);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) 
-		 | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
-					      >> 0x10U)))) 
-		 | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
-		    >> 1U)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank 
-	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) 
-	    & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
-	       == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-				>> 9U)))) & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use));
     vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests 
 	= ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
 	    ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) 
@@ -4688,67 +3482,6 @@ VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlS
 	    }
 	}
     }
-    // ALWAYS at ../rtl/cache/VX_d_cache.v:183
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = 0U;
-    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read 
-	    = (((~ ((IData)(0xffffffffU) << (0x1fU 
-					     & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) 
-						<< 5U)))) 
-		& vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read) 
-	       | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)
-		    ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-		        ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			    ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			    : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
-		        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-			    ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			        ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			        : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
-			    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-			        ? (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-				    ? (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				    : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))
-		    : 0U) << (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) 
-				       << 5U))));
-    }
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
-	   & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0U] 
-	= vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank;
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U;
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 0U;
-    if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) {
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U;
-	vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 1U;
-    }
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state 
-	= (0xfU & (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-		    & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss))
-		    ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))
-			     ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-				      & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))
-				      ? 2U : 0U))));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank 
-	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)
-	     ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index))
-	     : 0U) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask
-	   [0U]);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict 
-	= ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
-	   & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state)));
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)
-	    ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read
-	    : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read);
-    vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid 
-	= ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid) 
-	   & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)));
-    vlTOPp->out_icache_stall = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) 
-				| (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)));
 }
 
 void Vcache_simX::_eval(Vcache_simX__Syms* __restrict vlSymsp) {
@@ -4761,12 +3494,20 @@ void Vcache_simX::_eval(Vcache_simX__Syms* __restrict vlSymsp) {
 	 | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) {
 	vlTOPp->_sequent__TOP__4(vlSymsp);
 	vlTOPp->__Vm_traceActivity = (4U | vlTOPp->__Vm_traceActivity);
+	vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(vlSymsp);
+	vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(vlSymsp);
+	vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(vlSymsp);
+	vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(vlSymsp);
 	vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(vlSymsp);
 	vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(vlSymsp);
 	vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(vlSymsp);
 	vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(vlSymsp);
     }
     vlTOPp->_combo__TOP__5(vlSymsp);
+    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(vlSymsp);
+    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(vlSymsp);
+    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(vlSymsp);
+    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(vlSymsp);
     vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(vlSymsp);
     vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(vlSymsp);
     vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(vlSymsp);
@@ -4795,6 +3536,10 @@ void Vcache_simX::_eval_settle(Vcache_simX__Syms* __restrict vlSymsp) {
     // Body
     vlTOPp->_settle__TOP__2(vlSymsp);
     vlTOPp->__Vm_traceActivity = (1U | vlTOPp->__Vm_traceActivity);
+    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(vlSymsp);
+    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(vlSymsp);
+    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(vlSymsp);
+    vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(vlSymsp);
     vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(vlSymsp);
     vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(vlSymsp);
     vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(vlSymsp);
@@ -4861,6 +3606,7 @@ void Vcache_simX::_ctor_var_reset() {
     cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write = VL_RAND_RESET_I(3);
     cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read = VL_RAND_RESET_I(3);
     VL_RAND_RESET_W(512,cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata);
+    VL_RAND_RESET_W(512,cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata);
     cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid = VL_RAND_RESET_I(4);
     VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data);
     cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = VL_RAND_RESET_I(28);
@@ -4971,80 +3717,48 @@ void Vcache_simX::_ctor_var_reset() {
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = VL_RAND_RESET_I(32);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual = VL_RAND_RESET_I(32);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old = VL_RAND_RESET_I(1);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank = VL_RAND_RESET_I(4);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank = VL_RAND_RESET_I(4);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = VL_RAND_RESET_I(4);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank = VL_RAND_RESET_I(4);
+    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank = VL_RAND_RESET_I(4);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb = VL_RAND_RESET_I(4);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old = VL_RAND_RESET_I(4);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__state = VL_RAND_RESET_I(4);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state = VL_RAND_RESET_I(4);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid = VL_RAND_RESET_I(1);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid = VL_RAND_RESET_I(1);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid = VL_RAND_RESET_I(1);
+    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr = VL_RAND_RESET_I(32);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks = VL_RAND_RESET_I(1);
-    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks = VL_RAND_RESET_I(4);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual = VL_RAND_RESET_I(1);
+    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
 	    cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = VL_RAND_RESET_I(1);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss = VL_RAND_RESET_I(4);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = VL_RAND_RESET_I(2);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = VL_RAND_RESET_I(1);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict = VL_RAND_RESET_I(1);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b = VL_RAND_RESET_I(32);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found = VL_RAND_RESET_I(1);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index = VL_RAND_RESET_I(1);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found = VL_RAND_RESET_I(1);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index = VL_RAND_RESET_I(1);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found = VL_RAND_RESET_I(1);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index = VL_RAND_RESET_I(1);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found = VL_RAND_RESET_I(1);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index = VL_RAND_RESET_I(1);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr = VL_RAND_RESET_I(32);
     cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use = VL_RAND_RESET_I(23);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual = VL_RAND_RESET_I(32);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we = VL_RAND_RESET_I(16);
-    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way = VL_RAND_RESET_Q(46);
-    VL_RAND_RESET_W(256,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way = VL_RAND_RESET_I(2);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way = VL_RAND_RESET_I(2);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way = VL_RAND_RESET_I(2);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way = VL_RAND_RESET_I(32);
-    VL_RAND_RESET_W(256,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way = VL_RAND_RESET_I(2);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = VL_RAND_RESET_I(1);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty = VL_RAND_RESET_I(1);
-    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[__Vi0]);
-    }}
-    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(23);
-    }}
-    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
-    }}
-    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1);
-    }}
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty = VL_RAND_RESET_I(1);
-    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[__Vi0]);
-    }}
-    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(23);
-    }}
-    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
-    }}
-    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1);
-    }}
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32);
-    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr = VL_RAND_RESET_I(32);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in = VL_RAND_RESET_I(1);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr = VL_RAND_RESET_I(32);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in = VL_RAND_RESET_I(1);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr = VL_RAND_RESET_I(32);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in = VL_RAND_RESET_I(1);
+    cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i = VL_RAND_RESET_I(32);
     __Vtableidx1 = VL_RAND_RESET_I(4);
     __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[0] = 0U;
     __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[1] = 0U;
@@ -5486,6 +4200,55 @@ void Vcache_simX::_ctor_var_reset() {
     __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[13] = 4U;
     __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[14] = 4U;
     __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[15] = 4U;
+    __Vtableidx10 = VL_RAND_RESET_I(4);
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[0] = 0U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[1] = 0U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[2] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[3] = 0U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[4] = 2U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[5] = 0U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[6] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[7] = 0U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[8] = 3U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[9] = 0U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[10] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[11] = 0U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[12] = 2U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[13] = 0U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[14] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[15] = 0U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[0] = 0U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[1] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[2] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[3] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[4] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[5] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[6] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[7] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[8] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[9] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[10] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[11] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[12] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[13] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[14] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[15] = 1U;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[0] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[1] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[2] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[3] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[4] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[5] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[6] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[7] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[8] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[9] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[10] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[11] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[12] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[13] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[14] = 0xffffffffU;
+    __Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[15] = 0xffffffffU;
     __Vclklast__TOP__clk = VL_RAND_RESET_I(1);
     __Vclklast__TOP__reset = VL_RAND_RESET_I(1);
     __Vchglast__TOP__cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = VL_RAND_RESET_I(28);
diff --git a/simX/obj_dir/Vcache_simX.h b/simX/obj_dir/Vcache_simX.h
index ce960e15..9793b9cf 100644
--- a/simX/obj_dir/Vcache_simX.h
+++ b/simX/obj_dir/Vcache_simX.h
@@ -11,10 +11,10 @@
 #include "verilated.h"
 
 class Vcache_simX__Syms;
-class Vcache_simX_VX_dram_req_rsp_inter__N1_NB4;
-class Vcache_simX_VX_dcache_request_inter;
 class Vcache_simX_VX_dram_req_rsp_inter__N4_NB4;
+class Vcache_simX_VX_dcache_request_inter;
 class Vcache_simX_VX_Cache_Bank__pi8;
+class Vcache_simX_VX_Cache_Bank__pi9;
 class VerilatedVcd;
 
 //----------
@@ -24,13 +24,17 @@ VL_MODULE(Vcache_simX) {
     // CELLS
     // Public to allow access to /*verilator_public*/ items;
     // otherwise the application code can consider these internals.
-    Vcache_simX_VX_dram_req_rsp_inter__N1_NB4*	__PVT__cache_simX__DOT__VX_dram_req_rsp_icache;
+    Vcache_simX_VX_dram_req_rsp_inter__N4_NB4*	__PVT__cache_simX__DOT__VX_dram_req_rsp_icache;
     Vcache_simX_VX_dcache_request_inter*	__PVT__cache_simX__DOT__VX_dcache_req;
     Vcache_simX_VX_dram_req_rsp_inter__N4_NB4*	__PVT__cache_simX__DOT__VX_dram_req_rsp;
     Vcache_simX_VX_Cache_Bank__pi8*	__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
     Vcache_simX_VX_Cache_Bank__pi8*	__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
     Vcache_simX_VX_Cache_Bank__pi8*	__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
     Vcache_simX_VX_Cache_Bank__pi8*	__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
+    Vcache_simX_VX_Cache_Bank__pi9*	__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
+    Vcache_simX_VX_Cache_Bank__pi9*	__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
+    Vcache_simX_VX_Cache_Bank__pi9*	__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
+    Vcache_simX_VX_Cache_Bank__pi9*	__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
     
     // PORTS
     // The application code writes and reads these signals to
@@ -101,37 +105,27 @@ VL_MODULE(Vcache_simX) {
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in,0,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in,0,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank,3,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank,3,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank,3,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank,3,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank,3,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb,3,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old,3,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__state,3,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state,3,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid,0,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid,0,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss,3,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index,1,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found,0,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict,0,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update,0,0);
-    VL_SIG16(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we,15,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way,1,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way,1,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way,1,0);
-    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way,31,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way,1,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in,0,0);
     VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data,127,0,4);
     VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata,511,0,16);
     VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata,511,0,16);
@@ -162,33 +156,21 @@ VL_MODULE(Vcache_simX) {
     VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read,31,0);
     VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read,31,0);
     VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual,31,0);
+    VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank,127,0,4);
+    VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank,127,0,4);
     VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr,31,0);
     VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b,31,0);
     VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr,31,0);
-    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use,22,0);
-    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual,31,0);
-    VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write,127,0,4);
-    VL_SIG64(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way,45,0);
-    VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way,255,0,8);
-    VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way,255,0,8);
-    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f,31,0);
-    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind,31,0);
-    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f,31,0);
-    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind,31,0);
+    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr,31,0);
+    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr,31,0);
+    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr,31,0);
+    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i,31,0);
     VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
     VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
     VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
     VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[4],3,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[1],0,0);
-    VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[32],127,0,4);
-    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[32],22,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[32],0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[32],0,0);
-    VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[32],127,0,4);
-    VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[32],22,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[32],0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32],0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[4],0,0);
     
     // LOCAL VARIABLES
     // Internals; generally not touched by application code
@@ -219,6 +201,9 @@ VL_MODULE(Vcache_simX) {
     static VL_ST_SIG8(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[16],1,0);
     static VL_ST_SIG8(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[16],0,0);
     static VL_ST_SIG(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[16],31,0);
+    static VL_ST_SIG8(__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[16],1,0);
+    static VL_ST_SIG8(__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[16],0,0);
+    static VL_ST_SIG(__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[16],31,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1,6,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2,6,0);
     VL_SIG16(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids,15,0);
@@ -239,9 +224,15 @@ VL_MODULE(Vcache_simX) {
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index,1,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found,0,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index,1,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks,3,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found,0,0);
     VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index,0,0);
-    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found,0,0);
+    VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index,0,0);
     VL_SIG8(__Vtableidx1,3,0);
     VL_SIG8(__Vtableidx2,3,0);
     VL_SIG8(__Vtableidx3,3,0);
@@ -251,10 +242,12 @@ VL_MODULE(Vcache_simX) {
     VL_SIG8(__Vtableidx7,3,0);
     VL_SIG8(__Vtableidx8,3,0);
     VL_SIG8(__Vtableidx9,3,0);
+    VL_SIG8(__Vtableidx10,3,0);
     VL_SIG8(__Vclklast__TOP__clk,0,0);
     VL_SIG8(__Vclklast__TOP__reset,0,0);
     VL_SIG(__Vchglast__TOP__cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr,27,0);
     VL_SIGW(cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata,511,0,16);
+    VL_SIGW(cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata,511,0,16);
     VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data,127,0,4);
     VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address,127,0,4);
     VL_SIG(__Vm_traceActivity,31,0);
diff --git a/simX/obj_dir/Vcache_simX.mk b/simX/obj_dir/Vcache_simX.mk
index 7a99697e..c4af4761 100644
--- a/simX/obj_dir/Vcache_simX.mk
+++ b/simX/obj_dir/Vcache_simX.mk
@@ -12,9 +12,9 @@ PERL = perl
 # Path to Verilator kit (from $VERILATOR_ROOT)
 VERILATOR_ROOT = /usr/share/verilator
 # SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
-SYSTEMC_INCLUDE ?= 
+SYSTEMC_INCLUDE ?= /opt/systemc/include
 # SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
-SYSTEMC_LIBDIR ?= 
+SYSTEMC_LIBDIR ?= /opt/systemc/lib
 
 ### Switches...
 # SystemC output mode?  0/1 (from --sc)
@@ -33,7 +33,7 @@ VM_PREFIX = Vcache_simX
 VM_MODPREFIX = Vcache_simX
 # User CFLAGS (from -CFLAGS on Verilator command line)
 VM_USER_CFLAGS = \
-	-std=c++11 -fPIC -O3 \
+	-std=c++11 -fPIC -O3 -Wall -Wextra -pedantic \
 
 # User LDLIBS (from -LDFLAGS on Verilator command line)
 VM_USER_LDLIBS = \
diff --git a/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp b/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp
index e8076781..d2b036c7 100644
--- a/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp
+++ b/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp
@@ -33,74 +33,35 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
     VL_DEBUG_IF(VL_DBG_MSGF("+            Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1\n"); );
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
+    VL_SIGW(__Vtemp1,127,0,4);
+    VL_SIGW(__Vtemp2,127,0,4);
     VL_SIGW(__Vtemp3,127,0,4);
     VL_SIGW(__Vtemp4,127,0,4);
     VL_SIGW(__Vtemp5,127,0,4);
     VL_SIGW(__Vtemp6,127,0,4);
     VL_SIGW(__Vtemp7,127,0,4);
-    VL_SIGW(__Vtemp8,127,0,4);
-    VL_SIGW(__Vtemp9,127,0,4);
     // Body
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-	   [0U]);
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][3U];
     this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict;
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-	   [0U]);
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			     [0U])));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
-			      [0U])) << 0x15U));
     this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 				   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
     this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 			   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
-    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-				      ? 2U : ((2U == 
-					       (3U 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-					       ? 4U
-					       : 8U)));
+    this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))];
+    this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))];
+    __Vtemp1[0U] = 0U;
+    __Vtemp1[1U] = 0U;
+    __Vtemp1[2U] = 0U;
+    __Vtemp1[3U] = 0U;
+    __Vtemp2[0U] = 0U;
+    __Vtemp2[1U] = 0U;
+    __Vtemp2[2U] = 0U;
+    __Vtemp2[3U] = 0U;
     __Vtemp3[0U] = 0U;
     __Vtemp3[1U] = 0U;
     __Vtemp3[2U] = 0U;
@@ -121,24 +82,16 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
     __Vtemp7[1U] = 0U;
     __Vtemp7[2U] = 0U;
     __Vtemp7[3U] = 0U;
-    __Vtemp8[0U] = 0U;
-    __Vtemp8[1U] = 0U;
-    __Vtemp8[2U] = 0U;
-    __Vtemp8[3U] = 0U;
-    __Vtemp9[0U] = 0U;
-    __Vtemp9[1U] = 0U;
-    __Vtemp9[2U] = 0U;
-    __Vtemp9[3U] = 0U;
     this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))
 				    ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 				        ? (0xff00U 
-					   & (__Vtemp3[
+					   & (__Vtemp1[
 					      (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 					      << 8U))
 				        : ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 					    ? (0xff0000U 
-					       & (__Vtemp4[
+					       & (__Vtemp2[
 						  (3U 
 						   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 						  << 0x10U))
@@ -147,25 +100,104 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 						(3U 
 						 & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 					        ? (0xff000000U 
-						   & (__Vtemp5[
+						   & (__Vtemp3[
 						      (3U 
 						       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 						      << 0x18U))
-					        : __Vtemp6[
+					        : __Vtemp4[
 					       (3U 
 						& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])))
 				    : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))
 				        ? ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 					    ? (0xffff0000U 
-					       & (__Vtemp7[
+					       & (__Vtemp5[
 						  (3U 
 						   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 						  << 0x10U))
-					    : __Vtemp8[
+					    : __Vtemp6[
 					   (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])
-				        : __Vtemp9[
+				        : __Vtemp7[
 				       (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]));
+    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+				      ? 2U : ((2U == 
+					       (3U 
+						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+					       ? 4U
+					       : 8U)));
+    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+	   [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		      >> 6U))]);
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+	      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			 >> 6U))] << 1U));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			     [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					>> 6U))])));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					 >> 6U))])) 
+	      << 0x15U));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | ((IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use) 
+	      << 1U));
+    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U]
+				    : this->__PVT__use_write_data);
     // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
     this->__PVT__data_structures__DOT__invalid_index = 0U;
     this->__PVT__data_structures__DOT__invalid_found = 0U;
@@ -194,38 +226,6 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 				 == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
 						  >> 0xbU))))
 		      ? 1U : 0U) << 1U)));
-    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 4U));
-    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 8U));
-    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 0xcU));
-    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U]
-				    : this->__PVT__use_write_data);
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__way_index = 0U;
-    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
-    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 1U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
-    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 0U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
     this->__PVT__data_structures__DOT__data_write_per_way[0U] 
 	= this->__PVT__data_write[0U];
     this->__PVT__data_structures__DOT__data_write_per_way[1U] 
@@ -242,6 +242,17 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 	= this->__PVT__data_write[2U];
     this->__PVT__data_structures__DOT__data_write_per_way[7U] 
 	= this->__PVT__data_write[3U];
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__way_index = 0U;
+    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
+    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 1U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
+    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 0U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
     this->__PVT__data_structures__DOT__way_use_Qual 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
 	    ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index));
@@ -336,29 +347,69 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 					  : 0U));
     this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) 
 				 | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))
-				 ? this->__Vcellout__data_structures__data_use[0U]
-				 : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-				     ? (this->__Vcellout__data_structures__data_use[0U] 
-					>> 8U) : ((2U 
-						   == 
-						   (3U 
-						    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-						   ? 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x10U)
-						   : 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x18U))));
+				 ? this->__Vcellout__data_structures__data_use[
+				(3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+				       >> 4U))] : (
+						   (1U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+						    ? 
+						   (this->__Vcellout__data_structures__data_use[
+						    (3U 
+						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+							>> 4U))] 
+						    >> 8U)
+						    : 
+						   ((2U 
+						     == 
+						     (3U 
+						      & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+						     ? 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x10U)
+						     : 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x18U))));
+    this->__PVT__miss = (((this->__PVT__tag_use != 
+			   (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					 >> 0xbU))) 
+			  & (IData)(this->__PVT__valid_use)) 
+			 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
     this->__PVT__genblk1__BRA__0__KET____DOT__normal_write 
 	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
-	    & (IData)(this->__PVT__access)) & (~ ((
-						   (this->__PVT__tag_use 
-						    != 
-						    (0x1fffffU 
-						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-							>> 0xbU))) 
-						   & (IData)(this->__PVT__valid_use)) 
-						  & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in))));
+	    & ((IData)(this->__PVT__access) & (0U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__1__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (1U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__2__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (2U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__3__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (3U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
     this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) 
 		       | ((IData)(this->__PVT__write_from_mem)
 			   ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) 
@@ -379,6 +430,69 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 						   ? 3U
 						   : 0xcU)
 						  : 0U)))));
+    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 4U));
+    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 8U));
+    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 0xcU));
     this->__PVT__data_structures__DOT__we_per_way = 
 	((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) 
 	 | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
@@ -388,16 +502,6 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 	 | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
 			     ? (IData)(this->__PVT__we)
 			     : 0U) << 0x10U)));
-    this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
-		 | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)));
-    this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
-					      >> 0x10U)))) 
-		 | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
-		    >> 1U)));
 }
 
 VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(Vcache_simX__Syms* __restrict vlSymsp) {
@@ -451,26 +555,40 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 1U;
     } else {
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U;
-	if (this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty) {
+	if ((1U & (((~ (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+		    & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
+		   | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 
 		= (1U & ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))
 			  ? 0U : (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 
 		= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
 				>> 0xbU));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[0U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 
@@ -479,6 +597,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 8U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((4U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 
@@ -487,6 +608,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((8U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 
@@ -495,12 +619,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[1U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 
@@ -509,6 +639,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 
@@ -517,6 +650,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 
@@ -525,12 +661,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x100U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[2U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x200U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 
@@ -539,6 +681,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x400U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 
@@ -547,6 +692,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x800U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 
@@ -555,12 +703,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0x58U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x1000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[3U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0x60U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x2000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 
@@ -569,6 +723,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0x68U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x4000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 
@@ -577,6 +734,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0x70U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x8000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 
@@ -585,6 +745,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0x78U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
     }
     // ALWAYS at ../rtl/cache/VX_cache_data.v:79
@@ -593,28 +756,44 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U;
     } else {
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U;
-	if (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty) {
+	if ((1U & (((~ (IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+		    & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
+					 >> 0x10U)))) 
+		   | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
+		      >> 1U)))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 
 		= (1U & ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))
 			  ? 0U : (0U != (0xffffU & 
 					 (this->__PVT__data_structures__DOT__we_per_way 
 					  >> 0x10U)))));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 
 		= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
 				>> 0xbU));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[4U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 
@@ -623,6 +802,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 
@@ -631,6 +813,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 
@@ -639,12 +824,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x100000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[5U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x200000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 
@@ -653,6 +844,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x400000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 
@@ -661,6 +855,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x800000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 
@@ -669,12 +866,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x1000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[6U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x2000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 
@@ -683,6 +886,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x4000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 
@@ -691,6 +897,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x8000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 
@@ -699,12 +908,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0x58U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[7U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0x60U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 
@@ -712,6 +927,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 8U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0x68U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 
@@ -719,6 +937,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 0x10U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0x70U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 
@@ -726,6 +947,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 0x18U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0x78U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			    >> 6U));
 	}
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85
@@ -764,7 +988,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82
@@ -901,82 +1125,82 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36);
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     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37);
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     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38);
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     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39);
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     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40) {
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 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40);
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     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41);
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     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42);
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     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43);
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     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47);
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
@@ -1014,7 +1238,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 1U;
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32] = 1U;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
@@ -1052,7 +1276,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85
@@ -1091,7 +1315,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82
@@ -1228,82 +1452,82 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33);
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     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47);
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
@@ -1341,7 +1565,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 1U;
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32] = 1U;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
@@ -1379,94 +1603,43 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32;
     }
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-	   [0U]);
-    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-	   [0U]);
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			     [0U])));
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
-			      [0U])) << 0x15U));
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__invalid_index = 0U;
-    this->__PVT__data_structures__DOT__invalid_found = 0U;
-    if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
-		  >> 1U)))) {
-	this->__PVT__data_structures__DOT__invalid_index = 1U;
-	this->__PVT__data_structures__DOT__invalid_found = 1U;
-    }
-    if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) {
-	this->__PVT__data_structures__DOT__invalid_index = 0U;
-	this->__PVT__data_structures__DOT__invalid_found = 1U;
-    }
 }
 
 VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(Vcache_simX__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+            Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9\n"); );
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
+    VL_SIGW(__Vtemp75,127,0,4);
+    VL_SIGW(__Vtemp76,127,0,4);
     VL_SIGW(__Vtemp77,127,0,4);
     VL_SIGW(__Vtemp78,127,0,4);
     VL_SIGW(__Vtemp79,127,0,4);
     VL_SIGW(__Vtemp80,127,0,4);
     VL_SIGW(__Vtemp81,127,0,4);
-    VL_SIGW(__Vtemp82,127,0,4);
-    VL_SIGW(__Vtemp83,127,0,4);
     // Body
     this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 				   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
     this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 			   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
-    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-				      ? 2U : ((2U == 
-					       (3U 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-					       ? 4U
-					       : 8U)));
+    this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))];
+    this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))];
+    __Vtemp75[0U] = 0U;
+    __Vtemp75[1U] = 0U;
+    __Vtemp75[2U] = 0U;
+    __Vtemp75[3U] = 0U;
+    __Vtemp76[0U] = 0U;
+    __Vtemp76[1U] = 0U;
+    __Vtemp76[2U] = 0U;
+    __Vtemp76[3U] = 0U;
     __Vtemp77[0U] = 0U;
     __Vtemp77[1U] = 0U;
     __Vtemp77[2U] = 0U;
@@ -1487,24 +1660,16 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
     __Vtemp81[1U] = 0U;
     __Vtemp81[2U] = 0U;
     __Vtemp81[3U] = 0U;
-    __Vtemp82[0U] = 0U;
-    __Vtemp82[1U] = 0U;
-    __Vtemp82[2U] = 0U;
-    __Vtemp82[3U] = 0U;
-    __Vtemp83[0U] = 0U;
-    __Vtemp83[1U] = 0U;
-    __Vtemp83[2U] = 0U;
-    __Vtemp83[3U] = 0U;
     this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))
 				    ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 				        ? (0xff00U 
-					   & (__Vtemp77[
+					   & (__Vtemp75[
 					      (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 					      << 8U))
 				        : ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 					    ? (0xff0000U 
-					       & (__Vtemp78[
+					       & (__Vtemp76[
 						  (3U 
 						   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 						  << 0x10U))
@@ -1513,25 +1678,116 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 						(3U 
 						 & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 					        ? (0xff000000U 
-						   & (__Vtemp79[
+						   & (__Vtemp77[
 						      (3U 
 						       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 						      << 0x18U))
-					        : __Vtemp80[
+					        : __Vtemp78[
 					       (3U 
 						& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])))
 				    : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))
 				        ? ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 					    ? (0xffff0000U 
-					       & (__Vtemp81[
+					       & (__Vtemp79[
 						  (3U 
 						   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 						  << 0x10U))
-					    : __Vtemp82[
+					    : __Vtemp80[
 					   (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])
-				        : __Vtemp83[
+				        : __Vtemp81[
 				       (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]));
+    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+				      ? 2U : ((2U == 
+					       (3U 
+						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+					       ? 4U
+					       : 8U)));
+    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+	   [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		      >> 6U))]);
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+	      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+			 >> 6U))] << 1U));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			     [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					>> 6U))])));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					 >> 6U))])) 
+	      << 0x15U));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | ((IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use) 
+	      << 1U));
+    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U]
+				    : this->__PVT__use_write_data);
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__invalid_index = 0U;
+    this->__PVT__data_structures__DOT__invalid_found = 0U;
+    if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
+		  >> 1U)))) {
+	this->__PVT__data_structures__DOT__invalid_index = 1U;
+	this->__PVT__data_structures__DOT__invalid_found = 1U;
+    }
+    if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) {
+	this->__PVT__data_structures__DOT__invalid_index = 0U;
+	this->__PVT__data_structures__DOT__invalid_found = 1U;
+    }
     this->__PVT__data_structures__DOT__hit_per_way 
 	= ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) 
 	   | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
@@ -1548,38 +1804,6 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 				 == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
 						  >> 0xbU))))
 		      ? 1U : 0U) << 1U)));
-    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 4U));
-    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 8U));
-    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 0xcU));
-    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U]
-				    : this->__PVT__use_write_data);
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__way_index = 0U;
-    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
-    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 1U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
-    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 0U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
     this->__PVT__data_structures__DOT__data_write_per_way[0U] 
 	= this->__PVT__data_write[0U];
     this->__PVT__data_structures__DOT__data_write_per_way[1U] 
@@ -1596,6 +1820,17 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 	= this->__PVT__data_write[2U];
     this->__PVT__data_structures__DOT__data_write_per_way[7U] 
 	= this->__PVT__data_write[3U];
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__way_index = 0U;
+    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
+    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 1U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
+    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 0U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
     this->__PVT__data_structures__DOT__way_use_Qual 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
 	    ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index));
@@ -1690,29 +1925,69 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 					  : 0U));
     this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) 
 				 | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))
-				 ? this->__Vcellout__data_structures__data_use[0U]
-				 : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-				     ? (this->__Vcellout__data_structures__data_use[0U] 
-					>> 8U) : ((2U 
-						   == 
-						   (3U 
-						    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-						   ? 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x10U)
-						   : 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x18U))));
+				 ? this->__Vcellout__data_structures__data_use[
+				(3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+				       >> 4U))] : (
+						   (1U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+						    ? 
+						   (this->__Vcellout__data_structures__data_use[
+						    (3U 
+						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+							>> 4U))] 
+						    >> 8U)
+						    : 
+						   ((2U 
+						     == 
+						     (3U 
+						      & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+						     ? 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x10U)
+						     : 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x18U))));
+    this->__PVT__miss = (((this->__PVT__tag_use != 
+			   (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					 >> 0xbU))) 
+			  & (IData)(this->__PVT__valid_use)) 
+			 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
     this->__PVT__genblk1__BRA__0__KET____DOT__normal_write 
 	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
-	    & (IData)(this->__PVT__access)) & (~ ((
-						   (this->__PVT__tag_use 
-						    != 
-						    (0x1fffffU 
-						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-							>> 0xbU))) 
-						   & (IData)(this->__PVT__valid_use)) 
-						  & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in))));
+	    & ((IData)(this->__PVT__access) & (0U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__1__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (1U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__2__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (2U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__3__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (3U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
     this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) 
 		       | ((IData)(this->__PVT__write_from_mem)
 			   ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) 
@@ -1733,6 +2008,69 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 						   ? 3U
 						   : 0xcU)
 						  : 0U)))));
+    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 4U));
+    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 8U));
+    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 0xcU));
     this->__PVT__data_structures__DOT__we_per_way = 
 	((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) 
 	 | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
@@ -1742,90 +2080,41 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 	 | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
 			     ? (IData)(this->__PVT__we)
 			     : 0U) << 0x10U)));
-    this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
-		 | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)));
-    this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
-					      >> 0x10U)))) 
-		 | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
-		    >> 1U)));
 }
 
 void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(Vcache_simX__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+            Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2\n"); );
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
+    VL_SIGW(__Vtemp85,127,0,4);
+    VL_SIGW(__Vtemp86,127,0,4);
     VL_SIGW(__Vtemp87,127,0,4);
     VL_SIGW(__Vtemp88,127,0,4);
     VL_SIGW(__Vtemp89,127,0,4);
     VL_SIGW(__Vtemp90,127,0,4);
     VL_SIGW(__Vtemp91,127,0,4);
-    VL_SIGW(__Vtemp92,127,0,4);
-    VL_SIGW(__Vtemp93,127,0,4);
     // Body
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-	   [0U]);
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][3U];
     this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict;
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-	   [0U]);
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			     [0U])));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
-			      [0U])) << 0x15U));
     this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 				   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
     this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 			   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
-    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-				      ? 2U : ((2U == 
-					       (3U 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-					       ? 4U
-					       : 8U)));
+    this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))];
+    this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))];
+    __Vtemp85[0U] = 0U;
+    __Vtemp85[1U] = 0U;
+    __Vtemp85[2U] = 0U;
+    __Vtemp85[3U] = 0U;
+    __Vtemp86[0U] = 0U;
+    __Vtemp86[1U] = 0U;
+    __Vtemp86[2U] = 0U;
+    __Vtemp86[3U] = 0U;
     __Vtemp87[0U] = 0U;
     __Vtemp87[1U] = 0U;
     __Vtemp87[2U] = 0U;
@@ -1846,18 +2135,10 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
     __Vtemp91[1U] = 0U;
     __Vtemp91[2U] = 0U;
     __Vtemp91[3U] = 0U;
-    __Vtemp92[0U] = 0U;
-    __Vtemp92[1U] = 0U;
-    __Vtemp92[2U] = 0U;
-    __Vtemp92[3U] = 0U;
-    __Vtemp93[0U] = 0U;
-    __Vtemp93[1U] = 0U;
-    __Vtemp93[2U] = 0U;
-    __Vtemp93[3U] = 0U;
     this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))
 				    ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 				        ? (0xff00U 
-					   & (__Vtemp87[
+					   & (__Vtemp85[
 					      (3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 2U))] 
@@ -1865,7 +2146,7 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 				        : ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 					    ? (0xff0000U 
-					       & (__Vtemp88[
+					       & (__Vtemp86[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 2U))] 
@@ -1875,12 +2156,12 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 						(3U 
 						 & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 					        ? (0xff000000U 
-						   & (__Vtemp89[
+						   & (__Vtemp87[
 						      (3U 
 						       & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 							  >> 2U))] 
 						      << 0x18U))
-					        : __Vtemp90[
+					        : __Vtemp88[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 2U))])))
@@ -1888,17 +2169,96 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 				        ? ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 					    ? (0xffff0000U 
-					       & (__Vtemp91[
+					       & (__Vtemp89[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 2U))] 
 						  << 0x10U))
-					    : __Vtemp92[
+					    : __Vtemp90[
 					   (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						  >> 2U))])
-				        : __Vtemp93[
+				        : __Vtemp91[
 				       (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					      >> 2U))]));
+    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+				      ? 2U : ((2U == 
+					       (3U 
+						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+					       ? 4U
+					       : 8U)));
+    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+	   [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		      >> 6U))]);
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+	      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			 >> 6U))] << 1U));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			     [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					>> 6U))])));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					 >> 6U))])) 
+	      << 0x15U));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | ((IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use) 
+	      << 1U));
+    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U]
+				    : this->__PVT__use_write_data);
     // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
     this->__PVT__data_structures__DOT__invalid_index = 0U;
     this->__PVT__data_structures__DOT__invalid_found = 0U;
@@ -1927,38 +2287,6 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 				 == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
 						  >> 0xbU))))
 		      ? 1U : 0U) << 1U)));
-    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 4U));
-    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 8U));
-    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 0xcU));
-    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U]
-				    : this->__PVT__use_write_data);
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__way_index = 0U;
-    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
-    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 1U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
-    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 0U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
     this->__PVT__data_structures__DOT__data_write_per_way[0U] 
 	= this->__PVT__data_write[0U];
     this->__PVT__data_structures__DOT__data_write_per_way[1U] 
@@ -1975,6 +2303,17 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 	= this->__PVT__data_write[2U];
     this->__PVT__data_structures__DOT__data_write_per_way[7U] 
 	= this->__PVT__data_write[3U];
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__way_index = 0U;
+    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
+    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 1U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
+    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 0U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
     this->__PVT__data_structures__DOT__way_use_Qual 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
 	    ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index));
@@ -2069,29 +2408,69 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 					  : 0U));
     this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) 
 				 | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))
-				 ? this->__Vcellout__data_structures__data_use[0U]
-				 : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-				     ? (this->__Vcellout__data_structures__data_use[0U] 
-					>> 8U) : ((2U 
-						   == 
-						   (3U 
-						    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-						   ? 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x10U)
-						   : 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x18U))));
+				 ? this->__Vcellout__data_structures__data_use[
+				(3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+				       >> 4U))] : (
+						   (1U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+						    ? 
+						   (this->__Vcellout__data_structures__data_use[
+						    (3U 
+						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+							>> 4U))] 
+						    >> 8U)
+						    : 
+						   ((2U 
+						     == 
+						     (3U 
+						      & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+						     ? 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x10U)
+						     : 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x18U))));
+    this->__PVT__miss = (((this->__PVT__tag_use != 
+			   (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					 >> 0xbU))) 
+			  & (IData)(this->__PVT__valid_use)) 
+			 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
     this->__PVT__genblk1__BRA__0__KET____DOT__normal_write 
 	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
-	    & (IData)(this->__PVT__access)) & (~ ((
-						   (this->__PVT__tag_use 
-						    != 
-						    (0x1fffffU 
-						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
-							>> 0xbU))) 
-						   & (IData)(this->__PVT__valid_use)) 
-						  & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in))));
+	    & ((IData)(this->__PVT__access) & (0U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__1__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (1U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__2__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (2U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__3__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (3U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
     this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) 
 		       | ((IData)(this->__PVT__write_from_mem)
 			   ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) 
@@ -2112,6 +2491,69 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 						   ? 3U
 						   : 0xcU)
 						  : 0U)))));
+    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 4U));
+    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 8U));
+    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 0xcU));
     this->__PVT__data_structures__DOT__we_per_way = 
 	((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) 
 	 | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
@@ -2121,16 +2563,6 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 	 | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
 			     ? (IData)(this->__PVT__we)
 			     : 0U) << 0x10U)));
-    this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
-		 | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)));
-    this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
-					      >> 0x10U)))) 
-		 | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
-		    >> 1U)));
 }
 
 VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(Vcache_simX__Syms* __restrict vlSymsp) {
@@ -2184,26 +2616,40 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 1U;
     } else {
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U;
-	if (this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty) {
+	if ((1U & (((~ (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+		    & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
+		   | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 
 		= (1U & ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))
 			  ? 0U : (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 
 		= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
 				>> 0xbU));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[0U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 
@@ -2212,6 +2658,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 8U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((4U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 
@@ -2220,6 +2669,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((8U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 
@@ -2228,12 +2680,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[1U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 
@@ -2242,6 +2700,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 
@@ -2250,6 +2711,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 
@@ -2258,12 +2722,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x100U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[2U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x200U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 
@@ -2272,6 +2742,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x400U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 
@@ -2280,6 +2753,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x800U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 
@@ -2288,12 +2764,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0x58U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x1000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[3U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0x60U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x2000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 
@@ -2302,6 +2784,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0x68U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x4000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 
@@ -2310,6 +2795,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0x70U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x8000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 
@@ -2318,6 +2806,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0x78U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
     }
     // ALWAYS at ../rtl/cache/VX_cache_data.v:79
@@ -2326,28 +2817,44 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U;
     } else {
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U;
-	if (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty) {
+	if ((1U & (((~ (IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+		    & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
+					 >> 0x10U)))) 
+		   | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
+		      >> 1U)))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 
 		= (1U & ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))
 			  ? 0U : (0U != (0xffffU & 
 					 (this->__PVT__data_structures__DOT__we_per_way 
 					  >> 0x10U)))));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 
 		= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
 				>> 0xbU));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[4U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 
@@ -2356,6 +2863,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 
@@ -2364,6 +2874,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 
@@ -2372,12 +2885,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x100000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[5U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x200000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 
@@ -2386,6 +2905,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x400000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 
@@ -2394,6 +2916,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x800000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 
@@ -2402,12 +2927,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x1000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[6U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x2000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 
@@ -2416,6 +2947,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x4000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 
@@ -2424,6 +2958,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x8000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 
@@ -2432,12 +2969,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0x58U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[7U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0x60U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 
@@ -2445,6 +2988,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 8U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0x68U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 
@@ -2452,6 +2998,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 0x10U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0x70U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 
@@ -2459,6 +3008,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 0x18U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0x78U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			    >> 6U));
 	}
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85
@@ -2497,7 +3049,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82
@@ -2634,82 +3186,82 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47);
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
@@ -2747,7 +3299,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 1U;
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32] = 1U;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
@@ -2785,7 +3337,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85
@@ -2824,7 +3376,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82
@@ -2961,82 +3513,82 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47);
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
@@ -3074,7 +3626,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 1U;
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32] = 1U;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
@@ -3112,94 +3664,43 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32;
     }
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-	   [0U]);
-    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-	   [0U]);
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			     [0U])));
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
-			      [0U])) << 0x15U));
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__invalid_index = 0U;
-    this->__PVT__data_structures__DOT__invalid_found = 0U;
-    if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
-		  >> 1U)))) {
-	this->__PVT__data_structures__DOT__invalid_index = 1U;
-	this->__PVT__data_structures__DOT__invalid_found = 1U;
-    }
-    if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) {
-	this->__PVT__data_structures__DOT__invalid_index = 0U;
-	this->__PVT__data_structures__DOT__invalid_found = 1U;
-    }
 }
 
 VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(Vcache_simX__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+            Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10\n"); );
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
+    VL_SIGW(__Vtemp159,127,0,4);
+    VL_SIGW(__Vtemp160,127,0,4);
     VL_SIGW(__Vtemp161,127,0,4);
     VL_SIGW(__Vtemp162,127,0,4);
     VL_SIGW(__Vtemp163,127,0,4);
     VL_SIGW(__Vtemp164,127,0,4);
     VL_SIGW(__Vtemp165,127,0,4);
-    VL_SIGW(__Vtemp166,127,0,4);
-    VL_SIGW(__Vtemp167,127,0,4);
     // Body
     this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 				   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
     this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 			   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
-    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-				      ? 2U : ((2U == 
-					       (3U 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-					       ? 4U
-					       : 8U)));
+    this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))];
+    this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))];
+    __Vtemp159[0U] = 0U;
+    __Vtemp159[1U] = 0U;
+    __Vtemp159[2U] = 0U;
+    __Vtemp159[3U] = 0U;
+    __Vtemp160[0U] = 0U;
+    __Vtemp160[1U] = 0U;
+    __Vtemp160[2U] = 0U;
+    __Vtemp160[3U] = 0U;
     __Vtemp161[0U] = 0U;
     __Vtemp161[1U] = 0U;
     __Vtemp161[2U] = 0U;
@@ -3220,18 +3721,10 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
     __Vtemp165[1U] = 0U;
     __Vtemp165[2U] = 0U;
     __Vtemp165[3U] = 0U;
-    __Vtemp166[0U] = 0U;
-    __Vtemp166[1U] = 0U;
-    __Vtemp166[2U] = 0U;
-    __Vtemp166[3U] = 0U;
-    __Vtemp167[0U] = 0U;
-    __Vtemp167[1U] = 0U;
-    __Vtemp167[2U] = 0U;
-    __Vtemp167[3U] = 0U;
     this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))
 				    ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 				        ? (0xff00U 
-					   & (__Vtemp161[
+					   & (__Vtemp159[
 					      (3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 2U))] 
@@ -3239,7 +3732,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 				        : ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 					    ? (0xff0000U 
-					       & (__Vtemp162[
+					       & (__Vtemp160[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 2U))] 
@@ -3249,12 +3742,12 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 						(3U 
 						 & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 					        ? (0xff000000U 
-						   & (__Vtemp163[
+						   & (__Vtemp161[
 						      (3U 
 						       & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 							  >> 2U))] 
 						      << 0x18U))
-					        : __Vtemp164[
+					        : __Vtemp162[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 2U))])))
@@ -3262,17 +3755,108 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 				        ? ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 					    ? (0xffff0000U 
-					       & (__Vtemp165[
+					       & (__Vtemp163[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 2U))] 
 						  << 0x10U))
-					    : __Vtemp166[
+					    : __Vtemp164[
 					   (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						  >> 2U))])
-				        : __Vtemp167[
+				        : __Vtemp165[
 				       (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					      >> 2U))]));
+    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+				      ? 2U : ((2U == 
+					       (3U 
+						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+					       ? 4U
+					       : 8U)));
+    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+	   [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		      >> 6U))]);
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+	      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+			 >> 6U))] << 1U));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			     [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					>> 6U))])));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					 >> 6U))])) 
+	      << 0x15U));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | ((IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use) 
+	      << 1U));
+    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U]
+				    : this->__PVT__use_write_data);
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__invalid_index = 0U;
+    this->__PVT__data_structures__DOT__invalid_found = 0U;
+    if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
+		  >> 1U)))) {
+	this->__PVT__data_structures__DOT__invalid_index = 1U;
+	this->__PVT__data_structures__DOT__invalid_found = 1U;
+    }
+    if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) {
+	this->__PVT__data_structures__DOT__invalid_index = 0U;
+	this->__PVT__data_structures__DOT__invalid_found = 1U;
+    }
     this->__PVT__data_structures__DOT__hit_per_way 
 	= ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) 
 	   | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
@@ -3289,38 +3873,6 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 				 == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
 						  >> 0xbU))))
 		      ? 1U : 0U) << 1U)));
-    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 4U));
-    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 8U));
-    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 0xcU));
-    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U]
-				    : this->__PVT__use_write_data);
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__way_index = 0U;
-    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
-    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 1U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
-    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 0U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
     this->__PVT__data_structures__DOT__data_write_per_way[0U] 
 	= this->__PVT__data_write[0U];
     this->__PVT__data_structures__DOT__data_write_per_way[1U] 
@@ -3337,6 +3889,17 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 	= this->__PVT__data_write[2U];
     this->__PVT__data_structures__DOT__data_write_per_way[7U] 
 	= this->__PVT__data_write[3U];
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__way_index = 0U;
+    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
+    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 1U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
+    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 0U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
     this->__PVT__data_structures__DOT__way_use_Qual 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
 	    ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index));
@@ -3431,29 +3994,69 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 					  : 0U));
     this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) 
 				 | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))
-				 ? this->__Vcellout__data_structures__data_use[0U]
-				 : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-				     ? (this->__Vcellout__data_structures__data_use[0U] 
-					>> 8U) : ((2U 
-						   == 
-						   (3U 
-						    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-						   ? 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x10U)
-						   : 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x18U))));
+				 ? this->__Vcellout__data_structures__data_use[
+				(3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+				       >> 4U))] : (
+						   (1U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+						    ? 
+						   (this->__Vcellout__data_structures__data_use[
+						    (3U 
+						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+							>> 4U))] 
+						    >> 8U)
+						    : 
+						   ((2U 
+						     == 
+						     (3U 
+						      & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+						     ? 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x10U)
+						     : 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x18U))));
+    this->__PVT__miss = (((this->__PVT__tag_use != 
+			   (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					 >> 0xbU))) 
+			  & (IData)(this->__PVT__valid_use)) 
+			 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
     this->__PVT__genblk1__BRA__0__KET____DOT__normal_write 
 	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
-	    & (IData)(this->__PVT__access)) & (~ ((
-						   (this->__PVT__tag_use 
-						    != 
-						    (0x1fffffU 
-						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
-							>> 0xbU))) 
-						   & (IData)(this->__PVT__valid_use)) 
-						  & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in))));
+	    & ((IData)(this->__PVT__access) & (0U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__1__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (1U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__2__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (2U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__3__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (3U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
     this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) 
 		       | ((IData)(this->__PVT__write_from_mem)
 			   ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) 
@@ -3474,6 +4077,69 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 						   ? 3U
 						   : 0xcU)
 						  : 0U)))));
+    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 4U));
+    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 8U));
+    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 0xcU));
     this->__PVT__data_structures__DOT__we_per_way = 
 	((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) 
 	 | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
@@ -3483,90 +4149,41 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 	 | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
 			     ? (IData)(this->__PVT__we)
 			     : 0U) << 0x10U)));
-    this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
-		 | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)));
-    this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
-					      >> 0x10U)))) 
-		 | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
-		    >> 1U)));
 }
 
 void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(Vcache_simX__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+            Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3\n"); );
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
+    VL_SIGW(__Vtemp169,127,0,4);
+    VL_SIGW(__Vtemp170,127,0,4);
     VL_SIGW(__Vtemp171,127,0,4);
     VL_SIGW(__Vtemp172,127,0,4);
     VL_SIGW(__Vtemp173,127,0,4);
     VL_SIGW(__Vtemp174,127,0,4);
     VL_SIGW(__Vtemp175,127,0,4);
-    VL_SIGW(__Vtemp176,127,0,4);
-    VL_SIGW(__Vtemp177,127,0,4);
     // Body
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-	   [0U]);
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][3U];
     this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict;
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-	   [0U]);
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			     [0U])));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
-			      [0U])) << 0x15U));
     this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 				   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
     this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 			   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
-    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-				      ? 2U : ((2U == 
-					       (3U 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-					       ? 4U
-					       : 8U)));
+    this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))];
+    this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))];
+    __Vtemp169[0U] = 0U;
+    __Vtemp169[1U] = 0U;
+    __Vtemp169[2U] = 0U;
+    __Vtemp169[3U] = 0U;
+    __Vtemp170[0U] = 0U;
+    __Vtemp170[1U] = 0U;
+    __Vtemp170[2U] = 0U;
+    __Vtemp170[3U] = 0U;
     __Vtemp171[0U] = 0U;
     __Vtemp171[1U] = 0U;
     __Vtemp171[2U] = 0U;
@@ -3587,18 +4204,10 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
     __Vtemp175[1U] = 0U;
     __Vtemp175[2U] = 0U;
     __Vtemp175[3U] = 0U;
-    __Vtemp176[0U] = 0U;
-    __Vtemp176[1U] = 0U;
-    __Vtemp176[2U] = 0U;
-    __Vtemp176[3U] = 0U;
-    __Vtemp177[0U] = 0U;
-    __Vtemp177[1U] = 0U;
-    __Vtemp177[2U] = 0U;
-    __Vtemp177[3U] = 0U;
     this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))
 				    ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 				        ? (0xff00U 
-					   & (__Vtemp171[
+					   & (__Vtemp169[
 					      (3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 4U))] 
@@ -3606,7 +4215,7 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 				        : ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 					    ? (0xff0000U 
-					       & (__Vtemp172[
+					       & (__Vtemp170[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 4U))] 
@@ -3616,12 +4225,12 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 						(3U 
 						 & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 					        ? (0xff000000U 
-						   & (__Vtemp173[
+						   & (__Vtemp171[
 						      (3U 
 						       & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 							  >> 4U))] 
 						      << 0x18U))
-					        : __Vtemp174[
+					        : __Vtemp172[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 4U))])))
@@ -3629,17 +4238,96 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 				        ? ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 					    ? (0xffff0000U 
-					       & (__Vtemp175[
+					       & (__Vtemp173[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 4U))] 
 						  << 0x10U))
-					    : __Vtemp176[
+					    : __Vtemp174[
 					   (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						  >> 4U))])
-				        : __Vtemp177[
+				        : __Vtemp175[
 				       (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					      >> 4U))]));
+    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+				      ? 2U : ((2U == 
+					       (3U 
+						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+					       ? 4U
+					       : 8U)));
+    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+	   [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		      >> 6U))]);
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+	      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			 >> 6U))] << 1U));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			     [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					>> 6U))])));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					 >> 6U))])) 
+	      << 0x15U));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | ((IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use) 
+	      << 1U));
+    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU]
+				    : this->__PVT__use_write_data);
     // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
     this->__PVT__data_structures__DOT__invalid_index = 0U;
     this->__PVT__data_structures__DOT__invalid_found = 0U;
@@ -3668,38 +4356,6 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 				 == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
 						  >> 0xbU))))
 		      ? 1U : 0U) << 1U)));
-    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 4U));
-    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 8U));
-    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 0xcU));
-    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU]
-				    : this->__PVT__use_write_data);
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__way_index = 0U;
-    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
-    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 1U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
-    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 0U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
     this->__PVT__data_structures__DOT__data_write_per_way[0U] 
 	= this->__PVT__data_write[0U];
     this->__PVT__data_structures__DOT__data_write_per_way[1U] 
@@ -3716,6 +4372,17 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 	= this->__PVT__data_write[2U];
     this->__PVT__data_structures__DOT__data_write_per_way[7U] 
 	= this->__PVT__data_write[3U];
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__way_index = 0U;
+    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
+    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 1U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
+    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 0U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
     this->__PVT__data_structures__DOT__way_use_Qual 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
 	    ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index));
@@ -3810,29 +4477,69 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 					  : 0U));
     this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) 
 				 | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))
-				 ? this->__Vcellout__data_structures__data_use[0U]
-				 : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-				     ? (this->__Vcellout__data_structures__data_use[0U] 
-					>> 8U) : ((2U 
-						   == 
-						   (3U 
-						    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-						   ? 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x10U)
-						   : 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x18U))));
+				 ? this->__Vcellout__data_structures__data_use[
+				(3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+				       >> 4U))] : (
+						   (1U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+						    ? 
+						   (this->__Vcellout__data_structures__data_use[
+						    (3U 
+						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+							>> 4U))] 
+						    >> 8U)
+						    : 
+						   ((2U 
+						     == 
+						     (3U 
+						      & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+						     ? 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x10U)
+						     : 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x18U))));
+    this->__PVT__miss = (((this->__PVT__tag_use != 
+			   (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					 >> 0xbU))) 
+			  & (IData)(this->__PVT__valid_use)) 
+			 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
     this->__PVT__genblk1__BRA__0__KET____DOT__normal_write 
 	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
-	    & (IData)(this->__PVT__access)) & (~ ((
-						   (this->__PVT__tag_use 
-						    != 
-						    (0x1fffffU 
-						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
-							>> 0xbU))) 
-						   & (IData)(this->__PVT__valid_use)) 
-						  & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in))));
+	    & ((IData)(this->__PVT__access) & (0U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__1__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (1U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__2__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (2U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__3__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (3U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
     this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) 
 		       | ((IData)(this->__PVT__write_from_mem)
 			   ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) 
@@ -3853,6 +4560,69 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 						   ? 3U
 						   : 0xcU)
 						  : 0U)))));
+    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 4U));
+    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 8U));
+    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 0xcU));
     this->__PVT__data_structures__DOT__we_per_way = 
 	((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) 
 	 | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
@@ -3862,16 +4632,6 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 	 | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
 			     ? (IData)(this->__PVT__we)
 			     : 0U) << 0x10U)));
-    this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
-		 | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)));
-    this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
-					      >> 0x10U)))) 
-		 | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
-		    >> 1U)));
 }
 
 VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(Vcache_simX__Syms* __restrict vlSymsp) {
@@ -3925,26 +4685,40 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 1U;
     } else {
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U;
-	if (this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty) {
+	if ((1U & (((~ (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+		    & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
+		   | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 
 		= (1U & ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))
 			  ? 0U : (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 
 		= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
 				>> 0xbU));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[0U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 
@@ -3953,6 +4727,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 8U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((4U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 
@@ -3961,6 +4738,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((8U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 
@@ -3969,12 +4749,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[1U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 
@@ -3983,6 +4769,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 
@@ -3991,6 +4780,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 
@@ -3999,12 +4791,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x100U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[2U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x200U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 
@@ -4013,6 +4811,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x400U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 
@@ -4021,6 +4822,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x800U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 
@@ -4029,12 +4833,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0x58U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x1000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[3U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0x60U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x2000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 
@@ -4043,6 +4853,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0x68U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x4000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 
@@ -4051,6 +4864,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0x70U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x8000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 
@@ -4059,6 +4875,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0x78U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
     }
     // ALWAYS at ../rtl/cache/VX_cache_data.v:79
@@ -4067,28 +4886,44 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U;
     } else {
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U;
-	if (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty) {
+	if ((1U & (((~ (IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+		    & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
+					 >> 0x10U)))) 
+		   | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
+		      >> 1U)))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 
 		= (1U & ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))
 			  ? 0U : (0U != (0xffffU & 
 					 (this->__PVT__data_structures__DOT__we_per_way 
 					  >> 0x10U)))));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 
 		= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
 				>> 0xbU));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[4U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 
@@ -4097,6 +4932,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 
@@ -4105,6 +4943,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 
@@ -4113,12 +4954,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x100000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[5U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x200000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 
@@ -4127,6 +4974,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x400000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 
@@ -4135,6 +4985,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x800000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 
@@ -4143,12 +4996,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x1000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[6U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x2000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 
@@ -4157,6 +5016,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x4000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 
@@ -4165,6 +5027,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x8000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 
@@ -4173,12 +5038,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0x58U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[7U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0x60U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 
@@ -4186,6 +5057,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 8U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0x68U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 
@@ -4193,6 +5067,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 0x10U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0x70U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 
@@ -4200,6 +5077,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 0x18U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0x78U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			    >> 6U));
 	}
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85
@@ -4238,7 +5118,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82
@@ -4375,82 +5255,82 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47);
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
@@ -4488,7 +5368,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 1U;
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32] = 1U;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
@@ -4526,7 +5406,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85
@@ -4565,7 +5445,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82
@@ -4702,82 +5582,82 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47);
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
@@ -4815,7 +5695,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 1U;
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32] = 1U;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
@@ -4853,94 +5733,43 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32;
     }
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-	   [0U]);
-    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-	   [0U]);
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			     [0U])));
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
-			      [0U])) << 0x15U));
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__invalid_index = 0U;
-    this->__PVT__data_structures__DOT__invalid_found = 0U;
-    if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
-		  >> 1U)))) {
-	this->__PVT__data_structures__DOT__invalid_index = 1U;
-	this->__PVT__data_structures__DOT__invalid_found = 1U;
-    }
-    if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) {
-	this->__PVT__data_structures__DOT__invalid_index = 0U;
-	this->__PVT__data_structures__DOT__invalid_found = 1U;
-    }
 }
 
 VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(Vcache_simX__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+            Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11\n"); );
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
+    VL_SIGW(__Vtemp243,127,0,4);
+    VL_SIGW(__Vtemp244,127,0,4);
     VL_SIGW(__Vtemp245,127,0,4);
     VL_SIGW(__Vtemp246,127,0,4);
     VL_SIGW(__Vtemp247,127,0,4);
     VL_SIGW(__Vtemp248,127,0,4);
     VL_SIGW(__Vtemp249,127,0,4);
-    VL_SIGW(__Vtemp250,127,0,4);
-    VL_SIGW(__Vtemp251,127,0,4);
     // Body
     this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 				   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
     this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 			   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
-    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-				      ? 2U : ((2U == 
-					       (3U 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-					       ? 4U
-					       : 8U)));
+    this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))];
+    this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))];
+    __Vtemp243[0U] = 0U;
+    __Vtemp243[1U] = 0U;
+    __Vtemp243[2U] = 0U;
+    __Vtemp243[3U] = 0U;
+    __Vtemp244[0U] = 0U;
+    __Vtemp244[1U] = 0U;
+    __Vtemp244[2U] = 0U;
+    __Vtemp244[3U] = 0U;
     __Vtemp245[0U] = 0U;
     __Vtemp245[1U] = 0U;
     __Vtemp245[2U] = 0U;
@@ -4961,18 +5790,10 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
     __Vtemp249[1U] = 0U;
     __Vtemp249[2U] = 0U;
     __Vtemp249[3U] = 0U;
-    __Vtemp250[0U] = 0U;
-    __Vtemp250[1U] = 0U;
-    __Vtemp250[2U] = 0U;
-    __Vtemp250[3U] = 0U;
-    __Vtemp251[0U] = 0U;
-    __Vtemp251[1U] = 0U;
-    __Vtemp251[2U] = 0U;
-    __Vtemp251[3U] = 0U;
     this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))
 				    ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 				        ? (0xff00U 
-					   & (__Vtemp245[
+					   & (__Vtemp243[
 					      (3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 4U))] 
@@ -4980,7 +5801,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 				        : ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 					    ? (0xff0000U 
-					       & (__Vtemp246[
+					       & (__Vtemp244[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 4U))] 
@@ -4990,12 +5811,12 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 						(3U 
 						 & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 					        ? (0xff000000U 
-						   & (__Vtemp247[
+						   & (__Vtemp245[
 						      (3U 
 						       & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 							  >> 4U))] 
 						      << 0x18U))
-					        : __Vtemp248[
+					        : __Vtemp246[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 4U))])))
@@ -5003,17 +5824,108 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 				        ? ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 					    ? (0xffff0000U 
-					       & (__Vtemp249[
+					       & (__Vtemp247[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 4U))] 
 						  << 0x10U))
-					    : __Vtemp250[
+					    : __Vtemp248[
 					   (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						  >> 4U))])
-				        : __Vtemp251[
+				        : __Vtemp249[
 				       (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					      >> 4U))]));
+    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+				      ? 2U : ((2U == 
+					       (3U 
+						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+					       ? 4U
+					       : 8U)));
+    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+	   [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		      >> 6U))]);
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+	      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+			 >> 6U))] << 1U));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			     [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					>> 6U))])));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					 >> 6U))])) 
+	      << 0x15U));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | ((IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use) 
+	      << 1U));
+    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU]
+				    : this->__PVT__use_write_data);
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__invalid_index = 0U;
+    this->__PVT__data_structures__DOT__invalid_found = 0U;
+    if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
+		  >> 1U)))) {
+	this->__PVT__data_structures__DOT__invalid_index = 1U;
+	this->__PVT__data_structures__DOT__invalid_found = 1U;
+    }
+    if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) {
+	this->__PVT__data_structures__DOT__invalid_index = 0U;
+	this->__PVT__data_structures__DOT__invalid_found = 1U;
+    }
     this->__PVT__data_structures__DOT__hit_per_way 
 	= ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) 
 	   | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
@@ -5030,38 +5942,6 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 				 == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
 						  >> 0xbU))))
 		      ? 1U : 0U) << 1U)));
-    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 4U));
-    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 8U));
-    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 0xcU));
-    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU]
-				    : this->__PVT__use_write_data);
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__way_index = 0U;
-    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
-    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 1U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
-    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 0U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
     this->__PVT__data_structures__DOT__data_write_per_way[0U] 
 	= this->__PVT__data_write[0U];
     this->__PVT__data_structures__DOT__data_write_per_way[1U] 
@@ -5078,6 +5958,17 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 	= this->__PVT__data_write[2U];
     this->__PVT__data_structures__DOT__data_write_per_way[7U] 
 	= this->__PVT__data_write[3U];
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__way_index = 0U;
+    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
+    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 1U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
+    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 0U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
     this->__PVT__data_structures__DOT__way_use_Qual 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
 	    ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index));
@@ -5172,29 +6063,69 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 					  : 0U));
     this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) 
 				 | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))
-				 ? this->__Vcellout__data_structures__data_use[0U]
-				 : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-				     ? (this->__Vcellout__data_structures__data_use[0U] 
-					>> 8U) : ((2U 
-						   == 
-						   (3U 
-						    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-						   ? 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x10U)
-						   : 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x18U))));
+				 ? this->__Vcellout__data_structures__data_use[
+				(3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+				       >> 4U))] : (
+						   (1U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+						    ? 
+						   (this->__Vcellout__data_structures__data_use[
+						    (3U 
+						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+							>> 4U))] 
+						    >> 8U)
+						    : 
+						   ((2U 
+						     == 
+						     (3U 
+						      & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+						     ? 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x10U)
+						     : 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x18U))));
+    this->__PVT__miss = (((this->__PVT__tag_use != 
+			   (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					 >> 0xbU))) 
+			  & (IData)(this->__PVT__valid_use)) 
+			 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
     this->__PVT__genblk1__BRA__0__KET____DOT__normal_write 
 	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
-	    & (IData)(this->__PVT__access)) & (~ ((
-						   (this->__PVT__tag_use 
-						    != 
-						    (0x1fffffU 
-						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
-							>> 0xbU))) 
-						   & (IData)(this->__PVT__valid_use)) 
-						  & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in))));
+	    & ((IData)(this->__PVT__access) & (0U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__1__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (1U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__2__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (2U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__3__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (3U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
     this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) 
 		       | ((IData)(this->__PVT__write_from_mem)
 			   ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) 
@@ -5215,6 +6146,69 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 						   ? 3U
 						   : 0xcU)
 						  : 0U)))));
+    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 4U));
+    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 8U));
+    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 0xcU));
     this->__PVT__data_structures__DOT__we_per_way = 
 	((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) 
 	 | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
@@ -5224,90 +6218,41 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 	 | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
 			     ? (IData)(this->__PVT__we)
 			     : 0U) << 0x10U)));
-    this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
-		 | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)));
-    this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
-					      >> 0x10U)))) 
-		 | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
-		    >> 1U)));
 }
 
 void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(Vcache_simX__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+            Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4\n"); );
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
+    VL_SIGW(__Vtemp253,127,0,4);
+    VL_SIGW(__Vtemp254,127,0,4);
     VL_SIGW(__Vtemp255,127,0,4);
     VL_SIGW(__Vtemp256,127,0,4);
     VL_SIGW(__Vtemp257,127,0,4);
     VL_SIGW(__Vtemp258,127,0,4);
     VL_SIGW(__Vtemp259,127,0,4);
-    VL_SIGW(__Vtemp260,127,0,4);
-    VL_SIGW(__Vtemp261,127,0,4);
     // Body
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-	   [0U]);
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][3U];
     this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict;
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-	   [0U]);
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			     [0U])));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
-			      [0U])) << 0x15U));
     this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 				   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
     this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 			   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
-    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-				      ? 2U : ((2U == 
-					       (3U 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-					       ? 4U
-					       : 8U)));
+    this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))];
+    this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))];
+    __Vtemp253[0U] = 0U;
+    __Vtemp253[1U] = 0U;
+    __Vtemp253[2U] = 0U;
+    __Vtemp253[3U] = 0U;
+    __Vtemp254[0U] = 0U;
+    __Vtemp254[1U] = 0U;
+    __Vtemp254[2U] = 0U;
+    __Vtemp254[3U] = 0U;
     __Vtemp255[0U] = 0U;
     __Vtemp255[1U] = 0U;
     __Vtemp255[2U] = 0U;
@@ -5328,18 +6273,10 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
     __Vtemp259[1U] = 0U;
     __Vtemp259[2U] = 0U;
     __Vtemp259[3U] = 0U;
-    __Vtemp260[0U] = 0U;
-    __Vtemp260[1U] = 0U;
-    __Vtemp260[2U] = 0U;
-    __Vtemp260[3U] = 0U;
-    __Vtemp261[0U] = 0U;
-    __Vtemp261[1U] = 0U;
-    __Vtemp261[2U] = 0U;
-    __Vtemp261[3U] = 0U;
     this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))
 				    ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 				        ? (0xff00U 
-					   & (__Vtemp255[
+					   & (__Vtemp253[
 					      (3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 6U))] 
@@ -5347,7 +6284,7 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 				        : ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 					    ? (0xff0000U 
-					       & (__Vtemp256[
+					       & (__Vtemp254[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 6U))] 
@@ -5357,12 +6294,12 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 						(3U 
 						 & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 					        ? (0xff000000U 
-						   & (__Vtemp257[
+						   & (__Vtemp255[
 						      (3U 
 						       & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 							  >> 6U))] 
 						      << 0x18U))
-					        : __Vtemp258[
+					        : __Vtemp256[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 6U))])))
@@ -5370,17 +6307,96 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 				        ? ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 					    ? (0xffff0000U 
-					       & (__Vtemp259[
+					       & (__Vtemp257[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 6U))] 
 						  << 0x10U))
-					    : __Vtemp260[
+					    : __Vtemp258[
 					   (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						  >> 6U))])
-				        : __Vtemp261[
+				        : __Vtemp259[
 				       (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					      >> 6U))]));
+    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+				      ? 2U : ((2U == 
+					       (3U 
+						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+					       ? 4U
+					       : 8U)));
+    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+	   [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		      >> 6U))]);
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+	      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			 >> 6U))] << 1U));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			     [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					>> 6U))])));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					 >> 6U))])) 
+	      << 0x15U));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | ((IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use) 
+	      << 1U));
+    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU]
+				    : this->__PVT__use_write_data);
     // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
     this->__PVT__data_structures__DOT__invalid_index = 0U;
     this->__PVT__data_structures__DOT__invalid_found = 0U;
@@ -5409,38 +6425,6 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 				 == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
 						  >> 0xbU))))
 		      ? 1U : 0U) << 1U)));
-    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 4U));
-    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 8U));
-    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 0xcU));
-    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU]
-				    : this->__PVT__use_write_data);
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__way_index = 0U;
-    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
-    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 1U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
-    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 0U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
     this->__PVT__data_structures__DOT__data_write_per_way[0U] 
 	= this->__PVT__data_write[0U];
     this->__PVT__data_structures__DOT__data_write_per_way[1U] 
@@ -5457,6 +6441,17 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 	= this->__PVT__data_write[2U];
     this->__PVT__data_structures__DOT__data_write_per_way[7U] 
 	= this->__PVT__data_write[3U];
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__way_index = 0U;
+    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
+    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 1U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
+    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 0U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
     this->__PVT__data_structures__DOT__way_use_Qual 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
 	    ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index));
@@ -5551,29 +6546,69 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 					  : 0U));
     this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) 
 				 | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))
-				 ? this->__Vcellout__data_structures__data_use[0U]
-				 : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-				     ? (this->__Vcellout__data_structures__data_use[0U] 
-					>> 8U) : ((2U 
-						   == 
-						   (3U 
-						    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-						   ? 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x10U)
-						   : 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x18U))));
+				 ? this->__Vcellout__data_structures__data_use[
+				(3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+				       >> 4U))] : (
+						   (1U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+						    ? 
+						   (this->__Vcellout__data_structures__data_use[
+						    (3U 
+						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+							>> 4U))] 
+						    >> 8U)
+						    : 
+						   ((2U 
+						     == 
+						     (3U 
+						      & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+						     ? 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x10U)
+						     : 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x18U))));
+    this->__PVT__miss = (((this->__PVT__tag_use != 
+			   (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					 >> 0xbU))) 
+			  & (IData)(this->__PVT__valid_use)) 
+			 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
     this->__PVT__genblk1__BRA__0__KET____DOT__normal_write 
 	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
-	    & (IData)(this->__PVT__access)) & (~ ((
-						   (this->__PVT__tag_use 
-						    != 
-						    (0x1fffffU 
-						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
-							>> 0xbU))) 
-						   & (IData)(this->__PVT__valid_use)) 
-						  & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in))));
+	    & ((IData)(this->__PVT__access) & (0U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__1__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (1U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__2__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (2U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__3__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (3U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
     this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) 
 		       | ((IData)(this->__PVT__write_from_mem)
 			   ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) 
@@ -5594,6 +6629,69 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 						   ? 3U
 						   : 0xcU)
 						  : 0U)))));
+    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 4U));
+    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 8U));
+    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 0xcU));
     this->__PVT__data_structures__DOT__we_per_way = 
 	((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) 
 	 | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
@@ -5603,16 +6701,6 @@ void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_control
 	 | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
 			     ? (IData)(this->__PVT__we)
 			     : 0U) << 0x10U)));
-    this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
-		 | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)));
-    this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
-					      >> 0x10U)))) 
-		 | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
-		    >> 1U)));
 }
 
 VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(Vcache_simX__Syms* __restrict vlSymsp) {
@@ -5666,26 +6754,40 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 1U;
     } else {
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U;
-	if (this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty) {
+	if ((1U & (((~ (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+		    & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
+		   | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 
 		= (1U & ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))
 			  ? 0U : (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 
 		= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
 				>> 0xbU));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((1U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[0U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 
@@ -5694,6 +6796,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 8U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((4U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 
@@ -5702,6 +6807,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((8U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 
@@ -5710,12 +6818,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[1U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 
@@ -5724,6 +6838,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 
@@ -5732,6 +6849,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 
@@ -5740,12 +6860,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x100U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[2U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x200U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 
@@ -5754,6 +6880,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x400U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 
@@ -5762,6 +6891,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x800U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 
@@ -5770,12 +6902,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0x58U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x1000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[3U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0x60U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x2000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 
@@ -5784,6 +6922,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0x68U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x4000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 
@@ -5792,6 +6933,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0x70U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x8000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 
@@ -5800,6 +6944,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0x78U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
     }
     // ALWAYS at ../rtl/cache/VX_cache_data.v:79
@@ -5808,28 +6955,44 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U;
     } else {
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U;
-	if (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty) {
+	if ((1U & (((~ (IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+		    & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
+					 >> 0x10U)))) 
+		   | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
+		      >> 1U)))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 
 		= (1U & ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))
 			  ? 0U : (0U != (0xffffU & 
 					 (this->__PVT__data_structures__DOT__we_per_way 
 					  >> 0x10U)))));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 
 		= (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
 				>> 0xbU));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) {
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[4U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 
@@ -5838,6 +7001,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 
@@ -5846,6 +7012,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 
@@ -5854,12 +7023,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x100000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[5U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0x20U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x200000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 
@@ -5868,6 +7043,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0x28U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x400000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 
@@ -5876,6 +7054,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0x30U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x800000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 
@@ -5884,12 +7065,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0x38U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x1000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[6U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0x40U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x2000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 
@@ -5898,6 +7085,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 8U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0x48U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x4000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 
@@ -5906,6 +7096,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 					  >> 0x10U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0x50U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x8000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 
@@ -5914,12 +7107,18 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 				       >> 0x18U)));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0x58U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x10000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 
 		= (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[7U]);
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0x60U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x20000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 
@@ -5927,6 +7126,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 8U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0x68U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x40000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 
@@ -5934,6 +7136,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 0x10U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0x70U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
 	if ((0x80000000U & this->__PVT__data_structures__DOT__we_per_way)) {
 	    this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 
@@ -5941,6 +7146,9 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 			    >> 0x18U));
 	    this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 1U;
 	    this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0x78U;
+	    this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 
+		= (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			    >> 6U));
 	}
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85
@@ -5979,7 +7187,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82
@@ -6116,82 +7324,82 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47);
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
@@ -6229,7 +7437,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 1U;
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32] = 1U;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) {
@@ -6267,7 +7475,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85
@@ -6306,7 +7514,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82
@@ -6443,82 +7651,82 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46);
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47) {
 	VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47), 
 			  this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-			  [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47);
+			  [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47);
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
@@ -6556,7 +7764,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 1U;
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32] = 1U;
     }
     // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) {
@@ -6594,94 +7802,43 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DO
 	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U;
     }
     if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32) {
-	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] 
+	this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32] 
 	    = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32;
     }
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-	   [0U]);
-    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-	   [0U]);
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			     [0U])));
-    this->__PVT__data_structures__DOT__dirty_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][0U];
-    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][1U];
-    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][2U];
-    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
-	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
-	[0U][3U];
-    this->__PVT__data_structures__DOT__valid_use_per_way 
-	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
-	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
-	      [0U] << 1U));
-    this->__PVT__data_structures__DOT__tag_use_per_way 
-	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
-	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
-			      [0U])) << 0x15U));
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__invalid_index = 0U;
-    this->__PVT__data_structures__DOT__invalid_found = 0U;
-    if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
-		  >> 1U)))) {
-	this->__PVT__data_structures__DOT__invalid_index = 1U;
-	this->__PVT__data_structures__DOT__invalid_found = 1U;
-    }
-    if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) {
-	this->__PVT__data_structures__DOT__invalid_index = 0U;
-	this->__PVT__data_structures__DOT__invalid_found = 1U;
-    }
 }
 
 VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(Vcache_simX__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+            Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12\n"); );
     Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
+    VL_SIGW(__Vtemp327,127,0,4);
+    VL_SIGW(__Vtemp328,127,0,4);
     VL_SIGW(__Vtemp329,127,0,4);
     VL_SIGW(__Vtemp330,127,0,4);
     VL_SIGW(__Vtemp331,127,0,4);
     VL_SIGW(__Vtemp332,127,0,4);
     VL_SIGW(__Vtemp333,127,0,4);
-    VL_SIGW(__Vtemp334,127,0,4);
-    VL_SIGW(__Vtemp335,127,0,4);
     // Body
     this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 				   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
     this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
 			   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
-    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-				      ? 2U : ((2U == 
-					       (3U 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-					       ? 4U
-					       : 8U)));
+    this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))];
+    this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))];
+    __Vtemp327[0U] = 0U;
+    __Vtemp327[1U] = 0U;
+    __Vtemp327[2U] = 0U;
+    __Vtemp327[3U] = 0U;
+    __Vtemp328[0U] = 0U;
+    __Vtemp328[1U] = 0U;
+    __Vtemp328[2U] = 0U;
+    __Vtemp328[3U] = 0U;
     __Vtemp329[0U] = 0U;
     __Vtemp329[1U] = 0U;
     __Vtemp329[2U] = 0U;
@@ -6702,18 +7859,10 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
     __Vtemp333[1U] = 0U;
     __Vtemp333[2U] = 0U;
     __Vtemp333[3U] = 0U;
-    __Vtemp334[0U] = 0U;
-    __Vtemp334[1U] = 0U;
-    __Vtemp334[2U] = 0U;
-    __Vtemp334[3U] = 0U;
-    __Vtemp335[0U] = 0U;
-    __Vtemp335[1U] = 0U;
-    __Vtemp335[2U] = 0U;
-    __Vtemp335[3U] = 0U;
     this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))
 				    ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 				        ? (0xff00U 
-					   & (__Vtemp329[
+					   & (__Vtemp327[
 					      (3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 6U))] 
@@ -6721,7 +7870,7 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 				        : ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 					    ? (0xff0000U 
-					       & (__Vtemp330[
+					       & (__Vtemp328[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 6U))] 
@@ -6731,12 +7880,12 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 						(3U 
 						 & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 					        ? (0xff000000U 
-						   & (__Vtemp331[
+						   & (__Vtemp329[
 						      (3U 
 						       & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 							  >> 6U))] 
 						      << 0x18U))
-					        : __Vtemp332[
+					        : __Vtemp330[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 6U))])))
@@ -6744,17 +7893,108 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 				        ? ((2U == (3U 
 						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 					    ? (0xffff0000U 
-					       & (__Vtemp333[
+					       & (__Vtemp331[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 6U))] 
 						  << 0x10U))
-					    : __Vtemp334[
+					    : __Vtemp332[
 					   (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						  >> 6U))])
-				        : __Vtemp335[
+				        : __Vtemp333[
 				       (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					      >> 6U))]));
+    this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+			     ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+				      ? 2U : ((2U == 
+					       (3U 
+						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+					       ? 4U
+					       : 8U)));
+    this->__PVT__data_structures__DOT__data_use_per_way[0U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[1U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[2U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[3U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__data_use_per_way[4U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][0U];
+    this->__PVT__data_structures__DOT__data_use_per_way[5U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][1U];
+    this->__PVT__data_structures__DOT__data_use_per_way[6U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][2U];
+    this->__PVT__data_structures__DOT__data_use_per_way[7U] 
+	= this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		   >> 6U))][3U];
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+	   [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		      >> 6U))]);
+    this->__PVT__data_structures__DOT__valid_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) 
+	   | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+	      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+			 >> 6U))] << 1U));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			     [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					>> 6U))])));
+    this->__PVT__data_structures__DOT__tag_use_per_way 
+	= ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) 
+	   | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			      [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					 >> 6U))])) 
+	      << 0x15U));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | (IData)(this->data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+    this->__PVT__data_structures__DOT__dirty_use_per_way 
+	= ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) 
+	   | ((IData)(this->data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use) 
+	      << 1U));
+    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU]
+				    : this->__PVT__use_write_data);
+    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
+				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU]
+				    : this->__PVT__use_write_data);
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__invalid_index = 0U;
+    this->__PVT__data_structures__DOT__invalid_found = 0U;
+    if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
+		  >> 1U)))) {
+	this->__PVT__data_structures__DOT__invalid_index = 1U;
+	this->__PVT__data_structures__DOT__invalid_found = 1U;
+    }
+    if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) {
+	this->__PVT__data_structures__DOT__invalid_index = 0U;
+	this->__PVT__data_structures__DOT__invalid_found = 1U;
+    }
     this->__PVT__data_structures__DOT__hit_per_way 
 	= ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) 
 	   | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) 
@@ -6771,38 +8011,6 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 				 == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
 						  >> 0xbU))))
 		      ? 1U : 0U) << 1U)));
-    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 4U));
-    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 8U));
-    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
-		       | (((IData)(this->__PVT__write_from_mem)
-			    ? 0xfU : 0U) << 0xcU));
-    this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU]
-				    : this->__PVT__use_write_data);
-    this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem)
-				    ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU]
-				    : this->__PVT__use_write_data);
-    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
-    this->__PVT__data_structures__DOT__way_index = 0U;
-    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
-    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 1U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
-    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
-	this->__PVT__data_structures__DOT__way_index = 0U;
-	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
-    }
     this->__PVT__data_structures__DOT__data_write_per_way[0U] 
 	= this->__PVT__data_write[0U];
     this->__PVT__data_structures__DOT__data_write_per_way[1U] 
@@ -6819,6 +8027,17 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 	= this->__PVT__data_write[2U];
     this->__PVT__data_structures__DOT__data_write_per_way[7U] 
 	= this->__PVT__data_write[3U];
+    // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17
+    this->__PVT__data_structures__DOT__way_index = 0U;
+    this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U;
+    if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 1U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
+    if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) {
+	this->__PVT__data_structures__DOT__way_index = 0U;
+	this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U;
+    }
     this->__PVT__data_structures__DOT__way_use_Qual 
 	= ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))
 	    ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index));
@@ -6913,29 +8132,69 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 					  : 0U));
     this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) 
 				 | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))
-				 ? this->__Vcellout__data_structures__data_use[0U]
-				 : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-				     ? (this->__Vcellout__data_structures__data_use[0U] 
-					>> 8U) : ((2U 
-						   == 
-						   (3U 
-						    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-						   ? 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x10U)
-						   : 
-						  (this->__Vcellout__data_structures__data_use[0U] 
-						   >> 0x18U))));
+				 ? this->__Vcellout__data_structures__data_use[
+				(3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+				       >> 4U))] : (
+						   (1U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+						    ? 
+						   (this->__Vcellout__data_structures__data_use[
+						    (3U 
+						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+							>> 4U))] 
+						    >> 8U)
+						    : 
+						   ((2U 
+						     == 
+						     (3U 
+						      & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+						     ? 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x10U)
+						     : 
+						    (this->__Vcellout__data_structures__data_use[
+						     (3U 
+						      & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+							 >> 4U))] 
+						     >> 0x18U))));
+    this->__PVT__miss = (((this->__PVT__tag_use != 
+			   (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					 >> 0xbU))) 
+			  & (IData)(this->__PVT__valid_use)) 
+			 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
     this->__PVT__genblk1__BRA__0__KET____DOT__normal_write 
 	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
-	    & (IData)(this->__PVT__access)) & (~ ((
-						   (this->__PVT__tag_use 
-						    != 
-						    (0x1fffffU 
-						     & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
-							>> 0xbU))) 
-						   & (IData)(this->__PVT__valid_use)) 
-						  & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in))));
+	    & ((IData)(this->__PVT__access) & (0U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__1__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (1U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__2__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (2U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
+    this->__PVT__genblk1__BRA__3__KET____DOT__normal_write 
+	= (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) 
+	    & ((IData)(this->__PVT__access) & (3U == 
+					       (3U 
+						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+						   >> 4U))))) 
+	   & (~ (IData)(this->__PVT__miss)));
     this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) 
 		       | ((IData)(this->__PVT__write_from_mem)
 			   ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) 
@@ -6956,6 +8215,69 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 						   ? 3U
 						   : 0xcU)
 						  : 0U)))));
+    this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 4U));
+    this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 8U));
+    this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) 
+		       | (((IData)(this->__PVT__write_from_mem)
+			    ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+				       & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+				       ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						  & (0U 
+						     == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						  ? (IData)(this->__PVT__sb_mask)
+						  : 
+						 (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) 
+						   & (1U 
+						      == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))
+						   ? 
+						  ((0U 
+						    == 
+						    (3U 
+						     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+						    ? 3U
+						    : 0xcU)
+						   : 0U)))) 
+			  << 0xcU));
     this->__PVT__data_structures__DOT__we_per_way = 
 	((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) 
 	 | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
@@ -6965,16 +8287,6 @@ VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT_
 	 | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual)
 			     ? (IData)(this->__PVT__we)
 			     : 0U) << 0x10U)));
-    this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) 
-		 | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)));
-    this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty 
-	= (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-		   [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way 
-					      >> 0x10U)))) 
-		 | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) 
-		    >> 1U)));
 }
 
 void Vcache_simX_VX_Cache_Bank__pi8::_ctor_var_reset() {
@@ -7003,6 +8315,7 @@ void Vcache_simX_VX_Cache_Bank__pi8::_ctor_var_reset() {
     __PVT__valid_use = VL_RAND_RESET_I(1);
     __PVT__access = VL_RAND_RESET_I(1);
     __PVT__write_from_mem = VL_RAND_RESET_I(1);
+    __PVT__miss = VL_RAND_RESET_I(1);
     __PVT__way_to_update = VL_RAND_RESET_I(1);
     __PVT__data_unQual = VL_RAND_RESET_I(32);
     __PVT__use_write_data = VL_RAND_RESET_I(32);
@@ -7011,6 +8324,9 @@ void Vcache_simX_VX_Cache_Bank__pi8::_ctor_var_reset() {
     VL_RAND_RESET_W(128,__PVT__data_write);
     VL_RAND_RESET_W(128,__Vcellout__data_structures__data_use);
     __PVT__genblk1__BRA__0__KET____DOT__normal_write = VL_RAND_RESET_I(1);
+    __PVT__genblk1__BRA__1__KET____DOT__normal_write = VL_RAND_RESET_I(1);
+    __PVT__genblk1__BRA__2__KET____DOT__normal_write = VL_RAND_RESET_I(1);
+    __PVT__genblk1__BRA__3__KET____DOT__normal_write = VL_RAND_RESET_I(1);
     __PVT__data_structures__DOT__tag_use_per_way = VL_RAND_RESET_Q(42);
     VL_RAND_RESET_W(256,__PVT__data_structures__DOT__data_use_per_way);
     __PVT__data_structures__DOT__valid_use_per_way = VL_RAND_RESET_I(2);
@@ -7023,8 +8339,9 @@ void Vcache_simX_VX_Cache_Bank__pi8::_ctor_var_reset() {
     __PVT__data_structures__DOT__way_index = VL_RAND_RESET_I(1);
     __PVT__data_structures__DOT__invalid_index = VL_RAND_RESET_I(1);
     __PVT__data_structures__DOT__way_use_Qual = VL_RAND_RESET_I(1);
+    data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use = VL_RAND_RESET_I(1);
+    data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use = VL_RAND_RESET_I(1);
     __PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = VL_RAND_RESET_I(1);
-    __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty = VL_RAND_RESET_I(1);
     { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
 	    VL_RAND_RESET_W(128,__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[__Vi0]);
     }}
@@ -7039,7 +8356,6 @@ void Vcache_simX_VX_Cache_Bank__pi8::_ctor_var_reset() {
     }}
     __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32);
     __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32);
-    __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty = VL_RAND_RESET_I(1);
     { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
 	    VL_RAND_RESET_W(128,__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[__Vi0]);
     }}
@@ -7055,110 +8371,148 @@ void Vcache_simX_VX_Cache_Bank__pi8::_ctor_var_reset() {
     __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32);
     __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = VL_RAND_RESET_I(5);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = VL_RAND_RESET_I(1);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = VL_RAND_RESET_I(5);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = VL_RAND_RESET_I(21);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = VL_RAND_RESET_I(5);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(1);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = VL_RAND_RESET_I(5);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = VL_RAND_RESET_I(1);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = VL_RAND_RESET_I(5);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = VL_RAND_RESET_I(21);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = VL_RAND_RESET_I(5);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(1);
+    __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(5);
     __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(7);
     __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(8);
     __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(1);
diff --git a/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h b/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h
index adbb3427..19399811 100644
--- a/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h
+++ b/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h
@@ -40,10 +40,14 @@ VL_MODULE(Vcache_simX_VX_Cache_Bank__pi8) {
     VL_SIG8(__PVT__valid_use,0,0);
     VL_SIG8(__PVT__access,0,0);
     VL_SIG8(__PVT__write_from_mem,0,0);
+    VL_SIG8(__PVT__miss,0,0);
     VL_SIG8(__PVT__way_to_update,0,0);
     VL_SIG8(__PVT__sb_mask,3,0);
     VL_SIG16(__PVT__we,15,0);
     VL_SIG8(__PVT__genblk1__BRA__0__KET____DOT__normal_write,0,0);
+    VL_SIG8(__PVT__genblk1__BRA__1__KET____DOT__normal_write,0,0);
+    VL_SIG8(__PVT__genblk1__BRA__2__KET____DOT__normal_write,0,0);
+    VL_SIG8(__PVT__genblk1__BRA__3__KET____DOT__normal_write,0,0);
     VL_SIG8(__PVT__data_structures__DOT__valid_use_per_way,1,0);
     VL_SIG8(__PVT__data_structures__DOT__dirty_use_per_way,1,0);
     VL_SIG8(__PVT__data_structures__DOT__hit_per_way,1,0);
@@ -54,8 +58,6 @@ VL_MODULE(Vcache_simX_VX_Cache_Bank__pi8) {
     VL_SIG8(__PVT__data_structures__DOT__invalid_index,0,0);
     VL_SIG8(__PVT__data_structures__DOT__way_use_Qual,0,0);
     VL_SIG8(__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found,0,0);
-    VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty,0,0);
-    VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty,0,0);
     VL_SIG(__PVT__tag_use,20,0);
     VL_SIG(__PVT__data_unQual,31,0);
     VL_SIG(__PVT__use_write_data,31,0);
@@ -77,109 +79,149 @@ VL_MODULE(Vcache_simX_VX_Cache_Bank__pi8) {
     VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32],0,0);
     
     // LOCAL VARIABLES
+    VL_SIG8(data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use,0,0);
+    VL_SIG8(data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use,0,0);
     VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0,0,0);
+    VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,4,0);
     VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0);
     VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0);
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diff --git a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp
deleted file mode 100644
index b9911c9b..00000000
--- a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp
+++ /dev/null
@@ -1,36 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Design implementation internals
-// See Vcache_simX.h for the primary calling header
-
-#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" // For This
-#include "Vcache_simX__Syms.h"
-
-
-//--------------------
-// STATIC VARIABLES
-
-
-//--------------------
-
-VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
-    // Reset internal values
-    // Reset structure values
-    _ctor_var_reset();
-}
-
-void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
-    if (0 && first) {}  // Prevent unused
-    this->__VlSymsp = vlSymsp;
-}
-
-Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4() {
-}
-
-//--------------------
-// Internal Methods
-
-void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+          Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset\n"); );
-    // Body
-    VL_RAND_RESET_W(128,i_m_readdata);
-}
diff --git a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h
deleted file mode 100644
index 5af0a97d..00000000
--- a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h
+++ /dev/null
@@ -1,53 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Design internal header
-// See Vcache_simX.h for the primary calling header
-
-#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
-#define _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
-
-#include "verilated.h"
-
-class Vcache_simX__Syms;
-class VerilatedVcd;
-
-//----------
-
-VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
-  public:
-    
-    // PORTS
-    
-    // LOCAL SIGNALS
-    VL_SIGW(i_m_readdata,127,0,4);
-    
-    // LOCAL VARIABLES
-    
-    // INTERNAL VARIABLES
-  private:
-    Vcache_simX__Syms* __VlSymsp;  // Symbol table
-  public:
-    
-    // PARAMETERS
-    
-    // CONSTRUCTORS
-  private:
-    Vcache_simX_VX_dram_req_rsp_inter__N1_NB4& operator= (const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&);  ///< Copying not allowed
-    Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&);  ///< Copying not allowed
-  public:
-    Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const char* name="TOP");
-    ~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4();
-    void trace (VerilatedVcdC* tfp, int levels, int options=0);
-    
-    // API METHODS
-    
-    // INTERNAL METHODS
-    void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
-  private:
-    void _ctor_var_reset();
-  public:
-    static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
-    static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
-    static void traceChg  (VerilatedVcd* vcdp, void* userthis, uint32_t code);
-} VL_ATTR_ALIGNED(128);
-
-#endif // guard
diff --git a/simX/obj_dir/Vcache_simX__ALL.a b/simX/obj_dir/Vcache_simX__ALL.a
index efd7f2e4..402660eb 100644
Binary files a/simX/obj_dir/Vcache_simX__ALL.a and b/simX/obj_dir/Vcache_simX__ALL.a differ
diff --git a/simX/obj_dir/Vcache_simX__ALLcls.cpp b/simX/obj_dir/Vcache_simX__ALLcls.cpp
index ac39543f..3985b101 100644
--- a/simX/obj_dir/Vcache_simX__ALLcls.cpp
+++ b/simX/obj_dir/Vcache_simX__ALLcls.cpp
@@ -2,6 +2,6 @@
 #define VL_INCLUDE_OPT include
 #include "Vcache_simX.cpp"
 #include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
-#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
 #include "Vcache_simX_VX_dcache_request_inter.cpp"
+#include "Vcache_simX_VX_Cache_Bank__pi9.cpp"
 #include "Vcache_simX_VX_Cache_Bank__pi8.cpp"
diff --git a/simX/obj_dir/Vcache_simX__ALLcls.d b/simX/obj_dir/Vcache_simX__ALLcls.d
index 0768f6c1..ce7a2bca 100644
--- a/simX/obj_dir/Vcache_simX__ALLcls.d
+++ b/simX/obj_dir/Vcache_simX__ALLcls.d
@@ -3,9 +3,8 @@ Vcache_simX__ALLcls.o: Vcache_simX__ALLcls.cpp Vcache_simX.cpp \
  /usr/share/verilator/include/verilated_config.h \
  /usr/share/verilator/include/verilatedos.h Vcache_simX__Syms.h \
  Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
- Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
- Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi8.h \
+ Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi9.h \
+ Vcache_simX_VX_Cache_Bank__pi8.h \
  Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp \
- Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp \
  Vcache_simX_VX_dcache_request_inter.cpp \
- Vcache_simX_VX_Cache_Bank__pi8.cpp
+ Vcache_simX_VX_Cache_Bank__pi9.cpp Vcache_simX_VX_Cache_Bank__pi8.cpp
diff --git a/simX/obj_dir/Vcache_simX__ALLcls.o b/simX/obj_dir/Vcache_simX__ALLcls.o
index f7a0f234..59610cbc 100644
Binary files a/simX/obj_dir/Vcache_simX__ALLcls.o and b/simX/obj_dir/Vcache_simX__ALLcls.o differ
diff --git a/simX/obj_dir/Vcache_simX__ALLsup.d b/simX/obj_dir/Vcache_simX__ALLsup.d
index e8cbf34b..8e1dd87c 100644
--- a/simX/obj_dir/Vcache_simX__ALLsup.d
+++ b/simX/obj_dir/Vcache_simX__ALLsup.d
@@ -5,6 +5,6 @@ Vcache_simX__ALLsup.o: Vcache_simX__ALLsup.cpp Vcache_simX__Trace.cpp \
  /usr/share/verilator/include/verilated_config.h Vcache_simX__Syms.h \
  /usr/share/verilator/include/verilated.h Vcache_simX.h \
  Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
- Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
- Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi8.h \
- Vcache_simX__Syms.cpp Vcache_simX__Trace__Slow.cpp
+ Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi9.h \
+ Vcache_simX_VX_Cache_Bank__pi8.h Vcache_simX__Syms.cpp \
+ Vcache_simX__Trace__Slow.cpp
diff --git a/simX/obj_dir/Vcache_simX__ALLsup.o b/simX/obj_dir/Vcache_simX__ALLsup.o
index 5a665d64..362a2a48 100644
Binary files a/simX/obj_dir/Vcache_simX__ALLsup.o and b/simX/obj_dir/Vcache_simX__ALLsup.o differ
diff --git a/simX/obj_dir/Vcache_simX__Syms.cpp b/simX/obj_dir/Vcache_simX__Syms.cpp
index 4d621b00..3dfcb615 100644
--- a/simX/obj_dir/Vcache_simX__Syms.cpp
+++ b/simX/obj_dir/Vcache_simX__Syms.cpp
@@ -4,8 +4,8 @@
 #include "Vcache_simX__Syms.h"
 #include "Vcache_simX.h"
 #include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
-#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
 #include "Vcache_simX_VX_dcache_request_inter.h"
+#include "Vcache_simX_VX_Cache_Bank__pi9.h"
 #include "Vcache_simX_VX_Cache_Bank__pi8.h"
 
 // FUNCTIONS
@@ -22,6 +22,10 @@ Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
 	, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[1].bank_structure"))
 	, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[2].bank_structure"))
 	, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[3].bank_structure"))
+	, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[0].bank_structure"))
+	, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[1].bank_structure"))
+	, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[2].bank_structure"))
+	, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[3].bank_structure"))
 {
     // Pointer to top level
     TOPp = topp;
@@ -33,13 +37,21 @@ Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
     TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure  = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
     TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure  = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
     TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure  = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
+    TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure  = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
+    TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure  = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
+    TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure  = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
+    TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure  = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
     // Setup each module's pointer back to symbol table (for public functions)
     TOPp->__Vconfigure(this, true);
     TOP__cache_simX__DOT__VX_dcache_req.__Vconfigure(this, true);
     TOP__cache_simX__DOT__VX_dram_req_rsp.__Vconfigure(this, true);
-    TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, true);
+    TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, false);
     TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true);
     TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false);
     TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false);
     TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false);
+    TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true);
+    TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false);
+    TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false);
+    TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false);
 }
diff --git a/simX/obj_dir/Vcache_simX__Syms.h b/simX/obj_dir/Vcache_simX__Syms.h
index 50667b34..24328972 100644
--- a/simX/obj_dir/Vcache_simX__Syms.h
+++ b/simX/obj_dir/Vcache_simX__Syms.h
@@ -11,8 +11,8 @@
 // INCLUDE MODULE CLASSES
 #include "Vcache_simX.h"
 #include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
-#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
 #include "Vcache_simX_VX_dcache_request_inter.h"
+#include "Vcache_simX_VX_Cache_Bank__pi9.h"
 #include "Vcache_simX_VX_Cache_Bank__pi8.h"
 
 // SYMS CLASS
@@ -28,11 +28,15 @@ class Vcache_simX__Syms : public VerilatedSyms {
     Vcache_simX*                   TOPp;
     Vcache_simX_VX_dcache_request_inter TOP__cache_simX__DOT__VX_dcache_req;
     Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp;
-    Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
+    Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
     Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
     Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
     Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
     Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
+    Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
+    Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
+    Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
+    Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
     
     // CREATORS
     Vcache_simX__Syms(Vcache_simX* topp, const char* namep);
diff --git a/simX/obj_dir/Vcache_simX__Trace.cpp b/simX/obj_dir/Vcache_simX__Trace.cpp
index 21903a7c..8b3a96f3 100644
--- a/simX/obj_dir/Vcache_simX__Trace.cpp
+++ b/simX/obj_dir/Vcache_simX__Trace.cpp
@@ -54,50 +54,56 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
     int c=code;
     if (0 && vcdp && c) {}  // Prevent unused
     // Variables
-    VL_SIGW(__Vtemp544,127,0,4);
-    VL_SIGW(__Vtemp545,127,0,4);
-    VL_SIGW(__Vtemp546,127,0,4);
-    VL_SIGW(__Vtemp547,127,0,4);
-    VL_SIGW(__Vtemp548,127,0,4);
-    VL_SIGW(__Vtemp549,127,0,4);
-    VL_SIGW(__Vtemp550,127,0,4);
-    VL_SIGW(__Vtemp555,127,0,4);
-    VL_SIGW(__Vtemp556,127,0,4);
-    VL_SIGW(__Vtemp557,127,0,4);
-    VL_SIGW(__Vtemp558,127,0,4);
-    VL_SIGW(__Vtemp559,127,0,4);
-    VL_SIGW(__Vtemp560,127,0,4);
-    VL_SIGW(__Vtemp561,127,0,4);
-    VL_SIGW(__Vtemp562,127,0,4);
-    VL_SIGW(__Vtemp563,127,0,4);
-    VL_SIGW(__Vtemp564,127,0,4);
-    VL_SIGW(__Vtemp565,127,0,4);
-    VL_SIGW(__Vtemp566,127,0,4);
-    VL_SIGW(__Vtemp567,127,0,4);
-    VL_SIGW(__Vtemp568,127,0,4);
-    VL_SIGW(__Vtemp569,127,0,4);
-    VL_SIGW(__Vtemp570,127,0,4);
-    VL_SIGW(__Vtemp571,127,0,4);
-    VL_SIGW(__Vtemp572,127,0,4);
-    VL_SIGW(__Vtemp573,127,0,4);
-    VL_SIGW(__Vtemp574,127,0,4);
-    VL_SIGW(__Vtemp575,127,0,4);
-    VL_SIGW(__Vtemp576,127,0,4);
-    VL_SIGW(__Vtemp577,127,0,4);
-    VL_SIGW(__Vtemp578,127,0,4);
-    VL_SIGW(__Vtemp579,127,0,4);
-    VL_SIGW(__Vtemp580,127,0,4);
-    VL_SIGW(__Vtemp581,127,0,4);
-    VL_SIGW(__Vtemp582,127,0,4);
-    VL_SIGW(__Vtemp583,127,0,4);
-    VL_SIGW(__Vtemp584,127,0,4);
-    VL_SIGW(__Vtemp585,127,0,4);
-    VL_SIGW(__Vtemp586,127,0,4);
-    VL_SIGW(__Vtemp587,127,0,4);
-    VL_SIGW(__Vtemp588,127,0,4);
-    VL_SIGW(__Vtemp589,127,0,4);
-    VL_SIGW(__Vtemp590,127,0,4);
-    VL_SIGW(__Vtemp591,127,0,4);
+    VL_SIGW(__Vtemp686,127,0,4);
+    VL_SIGW(__Vtemp687,127,0,4);
+    VL_SIGW(__Vtemp688,127,0,4);
+    VL_SIGW(__Vtemp689,127,0,4);
+    VL_SIGW(__Vtemp690,127,0,4);
+    VL_SIGW(__Vtemp695,127,0,4);
+    VL_SIGW(__Vtemp696,127,0,4);
+    VL_SIGW(__Vtemp697,127,0,4);
+    VL_SIGW(__Vtemp698,127,0,4);
+    VL_SIGW(__Vtemp699,127,0,4);
+    VL_SIGW(__Vtemp700,127,0,4);
+    VL_SIGW(__Vtemp701,127,0,4);
+    VL_SIGW(__Vtemp702,127,0,4);
+    VL_SIGW(__Vtemp703,127,0,4);
+    VL_SIGW(__Vtemp704,127,0,4);
+    VL_SIGW(__Vtemp705,127,0,4);
+    VL_SIGW(__Vtemp706,127,0,4);
+    VL_SIGW(__Vtemp707,127,0,4);
+    VL_SIGW(__Vtemp708,127,0,4);
+    VL_SIGW(__Vtemp709,127,0,4);
+    VL_SIGW(__Vtemp710,127,0,4);
+    VL_SIGW(__Vtemp711,127,0,4);
+    VL_SIGW(__Vtemp712,127,0,4);
+    VL_SIGW(__Vtemp713,127,0,4);
+    VL_SIGW(__Vtemp714,127,0,4);
+    VL_SIGW(__Vtemp715,127,0,4);
+    VL_SIGW(__Vtemp716,127,0,4);
+    VL_SIGW(__Vtemp717,127,0,4);
+    VL_SIGW(__Vtemp718,127,0,4);
+    VL_SIGW(__Vtemp719,127,0,4);
+    VL_SIGW(__Vtemp720,127,0,4);
+    VL_SIGW(__Vtemp721,127,0,4);
+    VL_SIGW(__Vtemp722,127,0,4);
+    VL_SIGW(__Vtemp723,127,0,4);
+    VL_SIGW(__Vtemp724,127,0,4);
+    VL_SIGW(__Vtemp725,127,0,4);
+    VL_SIGW(__Vtemp726,127,0,4);
+    VL_SIGW(__Vtemp727,127,0,4);
+    VL_SIGW(__Vtemp728,127,0,4);
+    VL_SIGW(__Vtemp729,127,0,4);
+    VL_SIGW(__Vtemp730,127,0,4);
+    VL_SIGW(__Vtemp731,127,0,4);
+    VL_SIGW(__Vtemp732,127,0,4);
+    VL_SIGW(__Vtemp733,127,0,4);
+    VL_SIGW(__Vtemp734,127,0,4);
+    VL_SIGW(__Vtemp735,127,0,4);
+    VL_SIGW(__Vtemp736,127,0,4);
+    VL_SIGW(__Vtemp737,127,0,4);
+    VL_SIGW(__Vtemp738,127,0,4);
+    VL_SIGW(__Vtemp739,127,0,4);
     // Body
     {
 	vcdp->chgBit  (c+1,((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
@@ -113,23 +119,23 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 	vcdp->chgBus  (c+11,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read),3);
 	vcdp->chgBus  (c+12,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write),3);
 	vcdp->chgArray(c+13,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual),128);
-	__Vtemp544[0U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+	__Vtemp686[0U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
 			   & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
 			   ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U]
 			   : 0U);
-	__Vtemp544[1U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+	__Vtemp686[1U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
 			   & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
 			   ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U]
 			   : 0U);
-	__Vtemp544[2U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+	__Vtemp686[2U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
 			   & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
 			   ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U]
 			   : 0U);
-	__Vtemp544[3U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+	__Vtemp686[3U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
 			   & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
 			   ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U]
 			   : 0U);
-	vcdp->chgArray(c+17,(__Vtemp544),128);
+	vcdp->chgArray(c+17,(__Vtemp686),128);
 	vcdp->chgBus  (c+21,((0xfU & (((~ (IData)((0U 
 						   != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
 				       & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
@@ -184,37 +190,37 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 	vcdp->chgBit  (c+103,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found));
 	vcdp->chgBus  (c+104,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i),32);
 	vcdp->chgBus  (c+105,((0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)),7);
-	__Vtemp545[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U];
-	__Vtemp545[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U];
-	__Vtemp545[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U];
-	__Vtemp545[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U];
-	vcdp->chgArray(c+106,(__Vtemp545),128);
+	__Vtemp687[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U];
+	__Vtemp687[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U];
+	__Vtemp687[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U];
+	__Vtemp687[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U];
+	vcdp->chgArray(c+106,(__Vtemp687),128);
 	vcdp->chgBus  (c+110,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we))),2);
 	vcdp->chgBus  (c+111,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 					>> 7U))),7);
-	__Vtemp546[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U];
-	__Vtemp546[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U];
-	__Vtemp546[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U];
-	__Vtemp546[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U];
-	vcdp->chgArray(c+112,(__Vtemp546),128);
+	__Vtemp688[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U];
+	__Vtemp688[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U];
+	__Vtemp688[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U];
+	__Vtemp688[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U];
+	vcdp->chgArray(c+112,(__Vtemp688),128);
 	vcdp->chgBus  (c+116,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
 				     >> 2U))),2);
 	vcdp->chgBus  (c+117,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 					>> 0xeU))),7);
-	__Vtemp547[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U];
-	__Vtemp547[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U];
-	__Vtemp547[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU];
-	__Vtemp547[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU];
-	vcdp->chgArray(c+118,(__Vtemp547),128);
+	__Vtemp689[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U];
+	__Vtemp689[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U];
+	__Vtemp689[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU];
+	__Vtemp689[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU];
+	vcdp->chgArray(c+118,(__Vtemp689),128);
 	vcdp->chgBus  (c+122,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
 				     >> 4U))),2);
 	vcdp->chgBus  (c+123,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 					>> 0x15U))),7);
-	__Vtemp548[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU];
-	__Vtemp548[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU];
-	__Vtemp548[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU];
-	__Vtemp548[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU];
-	vcdp->chgArray(c+124,(__Vtemp548),128);
+	__Vtemp690[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU];
+	__Vtemp690[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU];
+	__Vtemp690[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU];
+	__Vtemp690[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU];
+	vcdp->chgArray(c+124,(__Vtemp690),128);
 	vcdp->chgBus  (c+128,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
 				     >> 6U))),2);
 	vcdp->chgBus  (c+129,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[0U])),32);
@@ -270,207 +276,192 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 	vcdp->chgBus  (c+194,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2);
 	vcdp->chgBus  (c+195,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
 					    >> 0xbU))),21);
-	vcdp->chgBit  (c+196,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank))));
-	vcdp->chgBit  (c+197,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
-	vcdp->chgBus  (c+198,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32);
-	vcdp->chgBus  (c+199,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2);
-	vcdp->chgBus  (c+200,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+	vcdp->chgBus  (c+196,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+				     >> 4U))),2);
+	vcdp->chgBus  (c+197,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					>> 6U))),5);
+	vcdp->chgBit  (c+198,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank))));
+	vcdp->chgBit  (c+199,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
+	vcdp->chgBus  (c+200,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32);
+	vcdp->chgBus  (c+201,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2);
+	vcdp->chgBus  (c+202,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
 					    >> 0xbU))),21);
-	vcdp->chgBit  (c+201,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
+	vcdp->chgBus  (c+203,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+				     >> 4U))),2);
+	vcdp->chgBus  (c+204,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					>> 6U))),5);
+	vcdp->chgBit  (c+205,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
 				     >> 1U))));
-	vcdp->chgBit  (c+202,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
-	vcdp->chgBus  (c+203,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32);
-	vcdp->chgBus  (c+204,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2);
-	vcdp->chgBus  (c+205,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+	vcdp->chgBit  (c+206,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
+	vcdp->chgBus  (c+207,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32);
+	vcdp->chgBus  (c+208,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2);
+	vcdp->chgBus  (c+209,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
 					    >> 0xbU))),21);
-	vcdp->chgBit  (c+206,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
+	vcdp->chgBus  (c+210,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+				     >> 4U))),2);
+	vcdp->chgBus  (c+211,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					>> 6U))),5);
+	vcdp->chgBit  (c+212,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
 				     >> 2U))));
-	vcdp->chgBit  (c+207,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
-	vcdp->chgBus  (c+208,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32);
-	vcdp->chgBus  (c+209,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2);
-	vcdp->chgBus  (c+210,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+	vcdp->chgBit  (c+213,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
+	vcdp->chgBus  (c+214,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32);
+	vcdp->chgBus  (c+215,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2);
+	vcdp->chgBus  (c+216,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
 					    >> 0xbU))),21);
-	vcdp->chgBit  (c+211,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
+	vcdp->chgBus  (c+217,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+				     >> 4U))),2);
+	vcdp->chgBus  (c+218,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					>> 6U))),5);
+	vcdp->chgBit  (c+219,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
 				     >> 3U))));
-	vcdp->chgBit  (c+212,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
-	vcdp->chgBus  (c+213,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i),32);
-	vcdp->chgBus  (c+214,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)
+	vcdp->chgBit  (c+220,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
+	vcdp->chgBus  (c+221,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i),32);
+	vcdp->chgBus  (c+222,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)
 				        ? ((IData)(1U) 
 					   << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index))
 				        : 0U))),4);
-	vcdp->chgBus  (c+215,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),2);
-	vcdp->chgBit  (c+216,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found));
-	vcdp->chgBus  (c+217,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i),32);
-	vcdp->chgBus  (c+218,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)
+	vcdp->chgBus  (c+223,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),2);
+	vcdp->chgBit  (c+224,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->chgBus  (c+225,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i),32);
+	vcdp->chgBus  (c+226,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)
 				        ? ((IData)(1U) 
 					   << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index))
 				        : 0U))),4);
-	vcdp->chgBus  (c+219,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index),2);
-	vcdp->chgBit  (c+220,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found));
-	vcdp->chgBus  (c+221,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i),32);
-	vcdp->chgBus  (c+222,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)
+	vcdp->chgBus  (c+227,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index),2);
+	vcdp->chgBit  (c+228,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->chgBus  (c+229,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i),32);
+	vcdp->chgBus  (c+230,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)
 				        ? ((IData)(1U) 
 					   << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index))
 				        : 0U))),4);
-	vcdp->chgBus  (c+223,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index),2);
-	vcdp->chgBit  (c+224,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found));
-	vcdp->chgBus  (c+225,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i),32);
-	vcdp->chgBus  (c+226,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)
+	vcdp->chgBus  (c+231,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index),2);
+	vcdp->chgBit  (c+232,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->chgBus  (c+233,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i),32);
+	vcdp->chgBus  (c+234,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)
 				        ? ((IData)(1U) 
 					   << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index))
 				        : 0U))),4);
-	vcdp->chgBus  (c+227,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index),2);
-	vcdp->chgBit  (c+228,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found));
-	vcdp->chgBus  (c+229,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i),32);
-	vcdp->chgBus  (c+230,((0xfffffff0U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
-					      << 9U))),32);
-	vcdp->chgBus  (c+231,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read),32);
-	vcdp->chgBus  (c+232,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks),1);
-	vcdp->chgBus  (c+233,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),1);
-	vcdp->chgBus  (c+234,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)
+	vcdp->chgBus  (c+235,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index),2);
+	vcdp->chgBit  (c+236,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->chgBus  (c+237,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i),32);
+	vcdp->chgBus  (c+238,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank[0U])),32);
+	vcdp->chgArray(c+239,(vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata),512);
+	vcdp->chgBus  (c+255,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read),32);
+	vcdp->chgBus  (c+256,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks),4);
+	vcdp->chgBus  (c+257,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank),4);
+	vcdp->chgBus  (c+258,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank),4);
+	vcdp->chgBus  (c+259,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank),4);
+	vcdp->chgBus  (c+260,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank),4);
+	vcdp->chgArray(c+261,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank),128);
+	vcdp->chgBus  (c+265,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank),4);
+	vcdp->chgBus  (c+266,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb),4);
+	vcdp->chgBus  (c+267,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state),4);
+	vcdp->chgBus  (c+268,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid),1);
+	vcdp->chgBus  (c+269,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid),1);
+	vcdp->chgArray(c+270,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank),128);
+	vcdp->chgBus  (c+274,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual),1);
+	vcdp->chgBus  (c+275,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0]),1);
+	vcdp->chgBus  (c+276,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[1]),1);
+	vcdp->chgBus  (c+277,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[2]),1);
+	vcdp->chgBus  (c+278,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[3]),1);
+	vcdp->chgBus  (c+279,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss),4);
+	vcdp->chgBus  (c+280,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index),2);
+	vcdp->chgBit  (c+281,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found));
+	vcdp->chgBus  (c+282,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks))),1);
+	vcdp->chgBus  (c+283,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank))),1);
+	vcdp->chgBit  (c+284,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank))));
+	vcdp->chgBus  (c+285,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[0U]),32);
+	vcdp->chgBus  (c+286,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) 
+				     >> 1U))),1);
+	vcdp->chgBus  (c+287,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank) 
+				     >> 1U))),1);
+	vcdp->chgBit  (c+288,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) 
+				     >> 1U))));
+	vcdp->chgBus  (c+289,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[1U]),32);
+	vcdp->chgBus  (c+290,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) 
+				     >> 2U))),1);
+	vcdp->chgBus  (c+291,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank) 
+				     >> 2U))),1);
+	vcdp->chgBit  (c+292,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) 
+				     >> 2U))));
+	vcdp->chgBus  (c+293,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[2U]),32);
+	vcdp->chgBus  (c+294,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) 
+				     >> 3U))),1);
+	vcdp->chgBus  (c+295,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank) 
+				     >> 3U))),1);
+	vcdp->chgBit  (c+296,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) 
+				     >> 3U))));
+	vcdp->chgBus  (c+297,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[3U]),32);
+	vcdp->chgBus  (c+298,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32);
+	vcdp->chgBus  (c+299,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2);
+	vcdp->chgBus  (c+300,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					    >> 0xbU))),21);
+	vcdp->chgBus  (c+301,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+				     >> 4U))),2);
+	vcdp->chgBus  (c+302,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					>> 6U))),5);
+	vcdp->chgBit  (c+303,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank))));
+	vcdp->chgBit  (c+304,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
+	vcdp->chgBus  (c+305,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32);
+	vcdp->chgBus  (c+306,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2);
+	vcdp->chgBus  (c+307,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					    >> 0xbU))),21);
+	vcdp->chgBus  (c+308,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+				     >> 4U))),2);
+	vcdp->chgBus  (c+309,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					>> 6U))),5);
+	vcdp->chgBit  (c+310,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+				     >> 1U))));
+	vcdp->chgBit  (c+311,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
+	vcdp->chgBus  (c+312,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32);
+	vcdp->chgBus  (c+313,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2);
+	vcdp->chgBus  (c+314,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					    >> 0xbU))),21);
+	vcdp->chgBus  (c+315,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+				     >> 4U))),2);
+	vcdp->chgBus  (c+316,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					>> 6U))),5);
+	vcdp->chgBit  (c+317,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+				     >> 2U))));
+	vcdp->chgBit  (c+318,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
+	vcdp->chgBus  (c+319,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32);
+	vcdp->chgBus  (c+320,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2);
+	vcdp->chgBus  (c+321,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					    >> 0xbU))),21);
+	vcdp->chgBus  (c+322,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+				     >> 4U))),2);
+	vcdp->chgBus  (c+323,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					>> 6U))),5);
+	vcdp->chgBit  (c+324,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+				     >> 3U))));
+	vcdp->chgBit  (c+325,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
+	vcdp->chgBus  (c+326,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i),32);
+	vcdp->chgBus  (c+327,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)
 				      ? ((IData)(1U) 
 					 << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index))
 				      : 0U))),1);
-	vcdp->chgBus  (c+235,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank),1);
-	vcdp->chgBus  (c+236,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank),1);
-	vcdp->chgBus  (c+237,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)
-			        ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-				    ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				        ? (0xffffff00U 
-					   | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				        : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
-				    : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-				        ? ((0x8000U 
-					    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-					    ? (0xffff0000U 
-					       | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-					    : (0xffffU 
-					       & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
-				        : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-					    ? (0xffffU 
-					       & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-					    : ((4U 
-						== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-					        ? (0xffU 
-						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-					        : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))
-			        : 0U)),32);
-	vcdp->chgBus  (c+238,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank),1);
-	vcdp->chgBus  (c+239,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state),4);
-	vcdp->chgBus  (c+240,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid),1);
-	vcdp->chgBus  (c+241,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid),1);
-	vcdp->chgBus  (c+242,((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
-			       << 9U)),32);
-	vcdp->chgBus  (c+243,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank),1);
-	vcdp->chgBus  (c+244,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0]),1);
-	vcdp->chgBus  (c+245,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss),1);
-	vcdp->chgBus  (c+246,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index),1);
-	vcdp->chgBit  (c+247,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found));
-	vcdp->chgBit  (c+248,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank));
-	vcdp->chgBus  (c+249,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32);
-	vcdp->chgBus  (c+250,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2);
-	vcdp->chgBus  (c+251,((0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-					    >> 9U))),23);
-	vcdp->chgBit  (c+252,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank));
-	vcdp->chgBit  (c+253,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
-	vcdp->chgBus  (c+254,(0U),32);
-	vcdp->chgBus  (c+255,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use),23);
-	vcdp->chgBit  (c+256,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use));
-	vcdp->chgBit  (c+257,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access));
-	vcdp->chgBit  (c+258,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem));
-	vcdp->chgBit  (c+259,((((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
-				 != (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-						  >> 9U))) 
-				& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)) 
-			       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in))));
-	vcdp->chgBit  (c+260,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
-	vcdp->chgBit  (c+261,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
-	vcdp->chgBit  (c+262,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
-	vcdp->chgBit  (c+263,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
-	vcdp->chgBit  (c+264,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
-	vcdp->chgBit  (c+265,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+266,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+267,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+268,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->chgBus  (c+269,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual),32);
-	vcdp->chgBus  (c+270,(((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			        ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			        : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32);
-	vcdp->chgBus  (c+271,(((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			        ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-			        : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32);
-	vcdp->chgBus  (c+272,((0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32);
-	vcdp->chgBus  (c+273,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32);
-	vcdp->chgBus  (c+274,(0U),32);
-	vcdp->chgBus  (c+275,(0U),32);
-	vcdp->chgBus  (c+276,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-			        ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				    ? (0xffffff00U 
-				       | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				    : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
-			        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-				    ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				        ? (0xffff0000U 
-					   | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				        : (0xffffU 
-					   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
-				    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-				        ? (0xffffU 
-					   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-					    ? (0xffU 
-					       & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-					    : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))),32);
-	vcdp->chgBus  (c+277,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-			        ? 1U : ((1U == (3U 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-					 ? 2U : ((2U 
-						  == 
-						  (3U 
-						   & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-						  ? 4U
-						  : 8U)))),4);
-	vcdp->chgBus  (c+278,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-			        ? 3U : 0xcU)),4);
-	vcdp->chgBus  (c+279,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we),16);
-	vcdp->chgArray(c+280,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write),128);
-	vcdp->chgBus  (c+284,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way),2);
-	vcdp->chgBus  (c+285,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way),32);
-	vcdp->chgArray(c+286,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way),256);
-	vcdp->chgBus  (c+294,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way),2);
-	vcdp->chgBus  (c+295,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index),1);
-	vcdp->chgBus  (c+296,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual),1);
-	vcdp->chgBit  (c+297,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
-	vcdp->chgBus  (c+298,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)),16);
-	vcdp->chgBit  (c+299,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))));
-	__Vtemp549[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U];
-	__Vtemp549[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U];
-	__Vtemp549[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U];
-	__Vtemp549[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U];
-	vcdp->chgArray(c+300,(__Vtemp549),128);
-	vcdp->chgBit  (c+304,((0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))));
-	vcdp->chgBit  (c+305,((1U & ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
-				      ? 0U : (0U != 
-					      (0xffffU 
-					       & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))))));
-	vcdp->chgBus  (c+306,((0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
-					  >> 0x10U))),16);
-	vcdp->chgBit  (c+307,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
-				     >> 1U))));
-	__Vtemp550[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U];
-	__Vtemp550[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U];
-	__Vtemp550[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U];
-	__Vtemp550[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U];
-	vcdp->chgArray(c+308,(__Vtemp550),128);
-	vcdp->chgBit  (c+312,((0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
-						 >> 0x10U)))));
-	vcdp->chgBit  (c+313,((1U & ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
-				      ? 0U : (0U != 
-					      (0xffffU 
-					       & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
-						  >> 0x10U)))))));
-	vcdp->chgBus  (c+314,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid),4);
-	__Vtemp555[0U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
+	vcdp->chgBus  (c+328,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),1);
+	vcdp->chgBit  (c+329,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->chgBus  (c+330,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)
+				      ? ((IData)(1U) 
+					 << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index))
+				      : 0U))),1);
+	vcdp->chgBus  (c+331,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index),1);
+	vcdp->chgBit  (c+332,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->chgBus  (c+333,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)
+				      ? ((IData)(1U) 
+					 << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index))
+				      : 0U))),1);
+	vcdp->chgBus  (c+334,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index),1);
+	vcdp->chgBit  (c+335,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->chgBus  (c+336,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)
+				      ? ((IData)(1U) 
+					 << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index))
+				      : 0U))),1);
+	vcdp->chgBus  (c+337,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index),1);
+	vcdp->chgBit  (c+338,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->chgBus  (c+339,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid),4);
+	__Vtemp695[0U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
 					       << 8U) 
 					      | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
 						 >> 0x18U))))
@@ -478,7 +469,7 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 			       & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
 			       ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U]
 			       : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U]);
-	__Vtemp555[1U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
+	__Vtemp695[1U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
 					       << 8U) 
 					      | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
 						 >> 0x18U))))
@@ -486,7 +477,7 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 			       & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
 			       ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U]
 			       : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U]);
-	__Vtemp555[2U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
+	__Vtemp695[2U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
 					       << 8U) 
 					      | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
 						 >> 0x18U))))
@@ -494,7 +485,7 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 			       & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
 			       ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U]
 			       : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U]);
-	__Vtemp555[3U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
+	__Vtemp695[3U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
 					       << 8U) 
 					      | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
 						 >> 0x18U))))
@@ -502,13 +493,562 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 			       & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
 			       ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U]
 			       : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U]);
-	vcdp->chgArray(c+315,(__Vtemp555),128);
-	__Vtemp556[0U] = 0U;
-	__Vtemp556[1U] = 0U;
-	__Vtemp556[2U] = 0U;
-	__Vtemp556[3U] = 0U;
-	vcdp->chgBus  (c+319,(__Vtemp556[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]),32);
-	vcdp->chgBus  (c+320,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
+	vcdp->chgArray(c+340,(__Vtemp695),128);
+	vcdp->chgBus  (c+344,(0U),32);
+	vcdp->chgBus  (c+345,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
+			        ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				    ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				        ? (0xffffff00U 
+					   | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
+				    : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				        ? ((0x8000U 
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+					    ? (0xffff0000U 
+					       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
+				        : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					    ? (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : ((4U 
+						== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					        ? (0xffU 
+						   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+					        : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))
+			        : 0U)),32);
+	vcdp->chgBit  (c+346,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) 
+				& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
+				   == (0x1fffffU & 
+				       (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					>> 0xbU)))) 
+			       & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use))));
+	vcdp->chgBit  (c+347,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->chgBus  (c+348,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
+				<< 0xbU) | (0x7c0U 
+					    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))),32);
+	vcdp->chgArray(c+349,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->chgBus  (c+353,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->chgBit  (c+354,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->chgBit  (c+355,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access));
+	vcdp->chgBit  (c+356,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->chgBit  (c+357,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
+				 != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+						  >> 0xbU))) 
+				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)) 
+			       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in))));
+	vcdp->chgBit  (c+358,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
+	vcdp->chgBit  (c+359,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
+	vcdp->chgBit  (c+360,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
+	vcdp->chgBit  (c+361,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
+	vcdp->chgBit  (c+362,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
+	vcdp->chgBit  (c+363,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+364,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+365,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+366,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->chgBus  (c+367,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->chgBus  (c+368,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+			        ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+			        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->chgBus  (c+369,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+			        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+			        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->chgBus  (c+370,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+371,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+372,(0U),32);
+	vcdp->chgBus  (c+373,(0U),32);
+	vcdp->chgBus  (c+374,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+			        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				    ? (0xffffff00U 
+				       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
+			        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				        ? (0xffff0000U 
+					   | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : (0xffffU 
+					   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
+				    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				        ? (0xffffU 
+					   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					    ? (0xffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
+	vcdp->chgBus  (c+375,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->chgBus  (c+376,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+			        ? 3U : 0xcU)),4);
+	vcdp->chgBus  (c+377,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->chgArray(c+378,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->chgQuad (c+382,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->chgArray(c+384,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->chgBus  (c+392,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->chgBus  (c+393,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->chgBus  (c+394,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->chgBus  (c+395,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->chgArray(c+396,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->chgBus  (c+404,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->chgBit  (c+405,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->chgBus  (c+406,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->chgBus  (c+407,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->chgBus  (c+408,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->chgBus  (c+409,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->chgBit  (c+410,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->chgBus  (c+411,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->chgBit  (c+412,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp696[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp696[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp696[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp696[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->chgArray(c+413,(__Vtemp696),128);
+	vcdp->chgBit  (c+417,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+418,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->chgBit  (c+419,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				     | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->chgBit  (c+420,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				      ? 0U : (0U != 
+					      (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
+	vcdp->chgBus  (c+421,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+					  >> 0x10U))),16);
+	vcdp->chgBit  (c+422,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+				     >> 1U))));
+	__Vtemp697[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp697[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp697[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp697[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->chgArray(c+423,(__Vtemp697),128);
+	vcdp->chgBit  (c+427,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+428,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						 >> 0x10U)))));
+	vcdp->chgBit  (c+429,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))) 
+				     | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					>> 1U)))));
+	vcdp->chgBit  (c+430,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				      ? 0U : (0U != 
+					      (0xffffU 
+					       & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						  >> 0x10U)))))));
+	vcdp->chgBus  (c+431,(0U),32);
+	vcdp->chgBus  (c+432,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
+			        ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				    ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				        ? (0xffffff00U 
+					   | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
+				    : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				        ? ((0x8000U 
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					    ? (0xffff0000U 
+					       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
+				        : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					    ? (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : ((4U 
+						== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					        ? (0xffU 
+						   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					        : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))
+			        : 0U)),32);
+	vcdp->chgBit  (c+433,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) 
+				& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
+				   == (0x1fffffU & 
+				       (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					>> 0xbU)))) 
+			       & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use))));
+	vcdp->chgBit  (c+434,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->chgBus  (c+435,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
+				<< 0xbU) | (0x7c0U 
+					    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))),32);
+	vcdp->chgArray(c+436,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->chgBus  (c+440,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->chgBit  (c+441,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->chgBit  (c+442,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access));
+	vcdp->chgBit  (c+443,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->chgBit  (c+444,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
+				 != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+						  >> 0xbU))) 
+				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)) 
+			       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in))));
+	vcdp->chgBit  (c+445,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+446,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+447,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+448,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->chgBus  (c+449,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->chgBus  (c+450,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+			        ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+			        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->chgBus  (c+451,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+			        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+			        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->chgBus  (c+452,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+453,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+454,(0U),32);
+	vcdp->chgBus  (c+455,(0U),32);
+	vcdp->chgBus  (c+456,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+			        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				    ? (0xffffff00U 
+				       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
+			        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				        ? (0xffff0000U 
+					   | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : (0xffffU 
+					   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
+				    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				        ? (0xffffU 
+					   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					    ? (0xffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
+	vcdp->chgBus  (c+457,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->chgBus  (c+458,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+			        ? 3U : 0xcU)),4);
+	vcdp->chgBus  (c+459,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->chgArray(c+460,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->chgQuad (c+464,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->chgArray(c+466,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->chgBus  (c+474,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->chgBus  (c+475,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->chgBus  (c+476,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->chgBus  (c+477,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->chgArray(c+478,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->chgBus  (c+486,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->chgBit  (c+487,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->chgBus  (c+488,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->chgBus  (c+489,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->chgBus  (c+490,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->chgBus  (c+491,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->chgBit  (c+492,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->chgBus  (c+493,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->chgBit  (c+494,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp698[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp698[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp698[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp698[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->chgArray(c+495,(__Vtemp698),128);
+	vcdp->chgBit  (c+499,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+500,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->chgBit  (c+501,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				     | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->chgBit  (c+502,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				      ? 0U : (0U != 
+					      (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
+	vcdp->chgBus  (c+503,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+					  >> 0x10U))),16);
+	vcdp->chgBit  (c+504,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+				     >> 1U))));
+	__Vtemp699[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp699[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp699[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp699[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->chgArray(c+505,(__Vtemp699),128);
+	vcdp->chgBit  (c+509,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+510,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						 >> 0x10U)))));
+	vcdp->chgBit  (c+511,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))) 
+				     | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					>> 1U)))));
+	vcdp->chgBit  (c+512,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				      ? 0U : (0U != 
+					      (0xffffU 
+					       & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						  >> 0x10U)))))));
+	vcdp->chgBus  (c+513,(0U),32);
+	vcdp->chgBus  (c+514,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
+			        ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				    ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				        ? (0xffffff00U 
+					   | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
+				    : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				        ? ((0x8000U 
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					    ? (0xffff0000U 
+					       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
+				        : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					    ? (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : ((4U 
+						== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					        ? (0xffU 
+						   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					        : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))
+			        : 0U)),32);
+	vcdp->chgBit  (c+515,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) 
+				& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
+				   == (0x1fffffU & 
+				       (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					>> 0xbU)))) 
+			       & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use))));
+	vcdp->chgBit  (c+516,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->chgBus  (c+517,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
+				<< 0xbU) | (0x7c0U 
+					    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))),32);
+	vcdp->chgArray(c+518,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->chgBus  (c+522,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->chgBit  (c+523,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->chgBit  (c+524,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access));
+	vcdp->chgBit  (c+525,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->chgBit  (c+526,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
+				 != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+						  >> 0xbU))) 
+				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)) 
+			       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in))));
+	vcdp->chgBit  (c+527,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+528,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+529,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+530,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->chgBus  (c+531,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->chgBus  (c+532,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+			        ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+			        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->chgBus  (c+533,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+			        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+			        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->chgBus  (c+534,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+535,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+536,(0U),32);
+	vcdp->chgBus  (c+537,(0U),32);
+	vcdp->chgBus  (c+538,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+			        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				    ? (0xffffff00U 
+				       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
+			        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				        ? (0xffff0000U 
+					   | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : (0xffffU 
+					   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
+				    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				        ? (0xffffU 
+					   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					    ? (0xffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
+	vcdp->chgBus  (c+539,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->chgBus  (c+540,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+			        ? 3U : 0xcU)),4);
+	vcdp->chgBus  (c+541,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->chgArray(c+542,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->chgQuad (c+546,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->chgArray(c+548,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->chgBus  (c+556,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->chgBus  (c+557,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->chgBus  (c+558,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->chgBus  (c+559,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->chgArray(c+560,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->chgBus  (c+568,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->chgBit  (c+569,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->chgBus  (c+570,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->chgBus  (c+571,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->chgBus  (c+572,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->chgBus  (c+573,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->chgBit  (c+574,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->chgBus  (c+575,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->chgBit  (c+576,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp700[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp700[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp700[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp700[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->chgArray(c+577,(__Vtemp700),128);
+	vcdp->chgBit  (c+581,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+582,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->chgBit  (c+583,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				     | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->chgBit  (c+584,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				      ? 0U : (0U != 
+					      (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
+	vcdp->chgBus  (c+585,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+					  >> 0x10U))),16);
+	vcdp->chgBit  (c+586,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+				     >> 1U))));
+	__Vtemp701[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp701[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp701[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp701[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->chgArray(c+587,(__Vtemp701),128);
+	vcdp->chgBit  (c+591,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+592,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						 >> 0x10U)))));
+	vcdp->chgBit  (c+593,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))) 
+				     | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					>> 1U)))));
+	vcdp->chgBit  (c+594,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				      ? 0U : (0U != 
+					      (0xffffU 
+					       & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						  >> 0x10U)))))));
+	vcdp->chgBus  (c+595,(0U),32);
+	vcdp->chgBus  (c+596,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
+			        ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				    ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				        ? (0xffffff00U 
+					   | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
+				    : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				        ? ((0x8000U 
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					    ? (0xffff0000U 
+					       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
+				        : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					    ? (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : ((4U 
+						== (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					        ? (0xffU 
+						   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					        : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))
+			        : 0U)),32);
+	vcdp->chgBit  (c+597,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) 
+				& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
+				   == (0x1fffffU & 
+				       (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					>> 0xbU)))) 
+			       & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use))));
+	vcdp->chgBit  (c+598,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->chgBus  (c+599,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
+				<< 0xbU) | (0x7c0U 
+					    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))),32);
+	vcdp->chgArray(c+600,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->chgBus  (c+604,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->chgBit  (c+605,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->chgBit  (c+606,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access));
+	vcdp->chgBit  (c+607,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->chgBit  (c+608,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
+				 != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+						  >> 0xbU))) 
+				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)) 
+			       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in))));
+	vcdp->chgBit  (c+609,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+610,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+611,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+612,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->chgBus  (c+613,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->chgBus  (c+614,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+			        ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+			        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->chgBus  (c+615,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+			        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+			        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->chgBus  (c+616,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+617,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+618,(0U),32);
+	vcdp->chgBus  (c+619,(0U),32);
+	vcdp->chgBus  (c+620,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+			        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				    ? (0xffffff00U 
+				       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				    : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
+			        : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				    ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				        ? (0xffff0000U 
+					   | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : (0xffffU 
+					   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
+				    : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				        ? (0xffffU 
+					   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				        : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					    ? (0xffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
+	vcdp->chgBus  (c+621,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->chgBus  (c+622,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+			        ? 3U : 0xcU)),4);
+	vcdp->chgBus  (c+623,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->chgArray(c+624,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->chgQuad (c+628,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->chgArray(c+630,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->chgBus  (c+638,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->chgBus  (c+639,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->chgBus  (c+640,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->chgBus  (c+641,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->chgArray(c+642,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->chgBus  (c+650,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->chgBit  (c+651,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->chgBus  (c+652,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->chgBus  (c+653,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->chgBus  (c+654,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->chgBus  (c+655,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->chgBit  (c+656,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->chgBus  (c+657,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->chgBit  (c+658,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp702[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp702[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp702[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp702[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->chgArray(c+659,(__Vtemp702),128);
+	vcdp->chgBit  (c+663,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+664,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->chgBit  (c+665,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				     | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->chgBit  (c+666,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				      ? 0U : (0U != 
+					      (0xffffU 
+					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
+	vcdp->chgBus  (c+667,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+					  >> 0x10U))),16);
+	vcdp->chgBit  (c+668,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+				     >> 1U))));
+	__Vtemp703[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp703[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp703[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp703[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->chgArray(c+669,(__Vtemp703),128);
+	vcdp->chgBit  (c+673,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+674,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						 >> 0x10U)))));
+	vcdp->chgBit  (c+675,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))) 
+				     | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					>> 1U)))));
+	vcdp->chgBit  (c+676,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				      ? 0U : (0U != 
+					      (0xffffU 
+					       & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						  >> 0x10U)))))));
+	__Vtemp704[0U] = 0U;
+	__Vtemp704[1U] = 0U;
+	__Vtemp704[2U] = 0U;
+	__Vtemp704[3U] = 0U;
+	vcdp->chgBus  (c+677,(__Vtemp704[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]),32);
+	vcdp->chgBus  (c+678,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
 			        ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				    ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 				        ? (0xffffff00U 
@@ -530,93 +1070,92 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 						   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 					        : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))
 			        : 0U)),32);
-	vcdp->chgBit  (c+321,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) 
+	vcdp->chgBit  (c+679,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) 
 				& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
 				   == (0x1fffffU & 
 				       (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
 					>> 0xbU)))) 
 			       & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use))));
-	vcdp->chgBus  (c+322,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
-			       << 0xbU)),32);
-	vcdp->chgArray(c+323,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
-	vcdp->chgBus  (c+327,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21);
-	vcdp->chgBit  (c+328,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use));
-	vcdp->chgBit  (c+329,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access));
-	vcdp->chgBit  (c+330,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem));
-	vcdp->chgBit  (c+331,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
-				 != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-						  >> 0xbU))) 
-				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)) 
-			       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in))));
-	vcdp->chgBit  (c+332,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
-	vcdp->chgBit  (c+333,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
-	vcdp->chgBit  (c+334,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
-	vcdp->chgBit  (c+335,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
-	vcdp->chgBit  (c+336,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
-	vcdp->chgBit  (c+337,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
-	vcdp->chgBit  (c+338,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
-	vcdp->chgBit  (c+339,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
-	vcdp->chgBit  (c+340,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+341,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+342,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+343,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->chgBus  (c+344,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32);
-	vcdp->chgBus  (c+345,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->chgBit  (c+680,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->chgBus  (c+681,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
+				<< 0xbU) | (0x7c0U 
+					    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))),32);
+	vcdp->chgArray(c+682,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->chgBus  (c+686,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->chgBit  (c+687,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->chgBit  (c+688,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access));
+	vcdp->chgBit  (c+689,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->chgBit  (c+690,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__miss));
+	vcdp->chgBit  (c+691,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
+	vcdp->chgBit  (c+692,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
+	vcdp->chgBit  (c+693,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
+	vcdp->chgBit  (c+694,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
+	vcdp->chgBit  (c+695,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
+	vcdp->chgBit  (c+696,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
+	vcdp->chgBit  (c+697,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
+	vcdp->chgBit  (c+698,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
+	vcdp->chgBit  (c+699,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+700,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+701,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+702,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->chgBus  (c+703,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->chgBus  (c+704,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 			        ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 			        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->chgBus  (c+346,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->chgBus  (c+705,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 			        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 			        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->chgBus  (c+347,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	vcdp->chgBus  (c+348,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	__Vtemp557[0U] = 0U;
-	__Vtemp557[1U] = 0U;
-	__Vtemp557[2U] = 0U;
-	__Vtemp557[3U] = 0U;
-	__Vtemp558[0U] = 0U;
-	__Vtemp558[1U] = 0U;
-	__Vtemp558[2U] = 0U;
-	__Vtemp558[3U] = 0U;
-	__Vtemp559[0U] = 0U;
-	__Vtemp559[1U] = 0U;
-	__Vtemp559[2U] = 0U;
-	__Vtemp559[3U] = 0U;
-	__Vtemp560[0U] = 0U;
-	__Vtemp560[1U] = 0U;
-	__Vtemp560[2U] = 0U;
-	__Vtemp560[3U] = 0U;
-	vcdp->chgBus  (c+349,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-			        ? (0xff00U & (__Vtemp557[
+	vcdp->chgBus  (c+706,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+707,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	__Vtemp705[0U] = 0U;
+	__Vtemp705[1U] = 0U;
+	__Vtemp705[2U] = 0U;
+	__Vtemp705[3U] = 0U;
+	__Vtemp706[0U] = 0U;
+	__Vtemp706[1U] = 0U;
+	__Vtemp706[2U] = 0U;
+	__Vtemp706[3U] = 0U;
+	__Vtemp707[0U] = 0U;
+	__Vtemp707[1U] = 0U;
+	__Vtemp707[2U] = 0U;
+	__Vtemp707[3U] = 0U;
+	__Vtemp708[0U] = 0U;
+	__Vtemp708[1U] = 0U;
+	__Vtemp708[2U] = 0U;
+	__Vtemp708[3U] = 0U;
+	vcdp->chgBus  (c+708,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+			        ? (0xff00U & (__Vtemp705[
 					      (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 					      << 8U))
 			        : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 				    ? (0xff0000U & 
-				       (__Vtemp558[
+				       (__Vtemp706[
 					(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 					<< 0x10U)) : 
 				   ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 				     ? (0xff000000U 
-					& (__Vtemp559[
+					& (__Vtemp707[
 					   (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 					   << 0x18U))
-				     : __Vtemp560[(3U 
+				     : __Vtemp708[(3U 
 						   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])))),32);
-	__Vtemp561[0U] = 0U;
-	__Vtemp561[1U] = 0U;
-	__Vtemp561[2U] = 0U;
-	__Vtemp561[3U] = 0U;
-	__Vtemp562[0U] = 0U;
-	__Vtemp562[1U] = 0U;
-	__Vtemp562[2U] = 0U;
-	__Vtemp562[3U] = 0U;
-	vcdp->chgBus  (c+350,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-			        ? (0xffff0000U & (__Vtemp561[
+	__Vtemp709[0U] = 0U;
+	__Vtemp709[1U] = 0U;
+	__Vtemp709[2U] = 0U;
+	__Vtemp709[3U] = 0U;
+	__Vtemp710[0U] = 0U;
+	__Vtemp710[1U] = 0U;
+	__Vtemp710[2U] = 0U;
+	__Vtemp710[3U] = 0U;
+	vcdp->chgBus  (c+709,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+			        ? (0xffff0000U & (__Vtemp709[
 						  (3U 
 						   & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 						  << 0x10U))
-			        : __Vtemp562[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])),32);
-	vcdp->chgBus  (c+351,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__use_write_data),32);
-	vcdp->chgBus  (c+352,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
+			        : __Vtemp710[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])),32);
+	vcdp->chgBus  (c+710,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__use_write_data),32);
+	vcdp->chgBus  (c+711,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 			        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 				    ? (0xffffff00U 
 				       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
@@ -634,54 +1173,76 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 					    ? (0xffU 
 					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 					    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
-	vcdp->chgBus  (c+353,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4);
-	vcdp->chgBus  (c+354,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+	vcdp->chgBus  (c+712,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->chgBus  (c+713,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 			        ? 3U : 0xcU)),4);
-	vcdp->chgBus  (c+355,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16);
-	vcdp->chgArray(c+356,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128);
-	vcdp->chgBit  (c+360,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
-	vcdp->chgBus  (c+361,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
-	vcdp->chgBus  (c+362,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
-	vcdp->chgArray(c+363,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
-	vcdp->chgBus  (c+371,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
-	vcdp->chgBus  (c+372,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
-	vcdp->chgBus  (c+373,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
-	vcdp->chgBit  (c+374,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
-	vcdp->chgBus  (c+375,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
-	vcdp->chgBit  (c+376,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
-	__Vtemp563[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
-	__Vtemp563[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
-	__Vtemp563[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
-	__Vtemp563[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
-	vcdp->chgArray(c+377,(__Vtemp563),128);
-	vcdp->chgBit  (c+381,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
-	vcdp->chgBit  (c+382,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->chgBus  (c+714,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->chgArray(c+715,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->chgBit  (c+719,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
+	vcdp->chgBit  (c+720,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
+	vcdp->chgBit  (c+721,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
+	vcdp->chgBit  (c+722,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
+	vcdp->chgQuad (c+723,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->chgArray(c+725,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->chgBus  (c+733,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->chgBus  (c+734,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->chgBus  (c+735,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->chgBus  (c+736,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->chgArray(c+737,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->chgBus  (c+745,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->chgBit  (c+746,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->chgBus  (c+747,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->chgBus  (c+748,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->chgBus  (c+749,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->chgBus  (c+750,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->chgBit  (c+751,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->chgBus  (c+752,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->chgBit  (c+753,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp711[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp711[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp711[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp711[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->chgArray(c+754,(__Vtemp711),128);
+	vcdp->chgBit  (c+758,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+759,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->chgBit  (c+760,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				     | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->chgBit  (c+761,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				      ? 0U : (0U != 
 					      (0xffffU 
 					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
-	vcdp->chgBus  (c+383,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	vcdp->chgBus  (c+762,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 					  >> 0x10U))),16);
-	vcdp->chgBit  (c+384,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+	vcdp->chgBit  (c+763,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
 				     >> 1U))));
-	__Vtemp564[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
-	__Vtemp564[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
-	__Vtemp564[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
-	__Vtemp564[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
-	vcdp->chgArray(c+385,(__Vtemp564),128);
-	vcdp->chgBit  (c+389,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	__Vtemp712[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp712[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp712[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp712[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->chgArray(c+764,(__Vtemp712),128);
+	vcdp->chgBit  (c+768,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+769,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						 >> 0x10U)))));
-	vcdp->chgBit  (c+390,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->chgBit  (c+770,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))) 
+				     | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					>> 1U)))));
+	vcdp->chgBit  (c+771,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				      ? 0U : (0U != 
 					      (0xffffU 
 					       & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						  >> 0x10U)))))));
-	__Vtemp565[0U] = 0U;
-	__Vtemp565[1U] = 0U;
-	__Vtemp565[2U] = 0U;
-	__Vtemp565[3U] = 0U;
-	vcdp->chgBus  (c+391,(__Vtemp565[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
+	__Vtemp713[0U] = 0U;
+	__Vtemp713[1U] = 0U;
+	__Vtemp713[2U] = 0U;
+	__Vtemp713[3U] = 0U;
+	vcdp->chgBus  (c+772,(__Vtemp713[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 2U))]),32);
-	vcdp->chgBus  (c+392,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
+	vcdp->chgBus  (c+773,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
 			        ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				    ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 				        ? (0xffffff00U 
@@ -703,93 +1264,92 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 						   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 					        : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))
 			        : 0U)),32);
-	vcdp->chgBit  (c+393,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) 
+	vcdp->chgBit  (c+774,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) 
 				& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
 				   == (0x1fffffU & 
 				       (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
 					>> 0xbU)))) 
 			       & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use))));
-	vcdp->chgBus  (c+394,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
-			       << 0xbU)),32);
-	vcdp->chgArray(c+395,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
-	vcdp->chgBus  (c+399,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21);
-	vcdp->chgBit  (c+400,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use));
-	vcdp->chgBit  (c+401,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access));
-	vcdp->chgBit  (c+402,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem));
-	vcdp->chgBit  (c+403,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
-				 != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
-						  >> 0xbU))) 
-				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)) 
-			       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in))));
-	vcdp->chgBit  (c+404,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+405,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+406,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+407,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
-	vcdp->chgBus  (c+408,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32);
-	vcdp->chgBus  (c+409,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->chgBit  (c+775,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->chgBus  (c+776,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
+				<< 0xbU) | (0x7c0U 
+					    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))),32);
+	vcdp->chgArray(c+777,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->chgBus  (c+781,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->chgBit  (c+782,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->chgBit  (c+783,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access));
+	vcdp->chgBit  (c+784,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->chgBit  (c+785,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__miss));
+	vcdp->chgBit  (c+786,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+787,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+788,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+789,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->chgBus  (c+790,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->chgBus  (c+791,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 			        ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 			        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->chgBus  (c+410,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->chgBus  (c+792,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 			        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 			        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->chgBus  (c+411,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	vcdp->chgBus  (c+412,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	__Vtemp566[0U] = 0U;
-	__Vtemp566[1U] = 0U;
-	__Vtemp566[2U] = 0U;
-	__Vtemp566[3U] = 0U;
-	__Vtemp567[0U] = 0U;
-	__Vtemp567[1U] = 0U;
-	__Vtemp567[2U] = 0U;
-	__Vtemp567[3U] = 0U;
-	__Vtemp568[0U] = 0U;
-	__Vtemp568[1U] = 0U;
-	__Vtemp568[2U] = 0U;
-	__Vtemp568[3U] = 0U;
-	__Vtemp569[0U] = 0U;
-	__Vtemp569[1U] = 0U;
-	__Vtemp569[2U] = 0U;
-	__Vtemp569[3U] = 0U;
-	vcdp->chgBus  (c+413,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-			        ? (0xff00U & (__Vtemp566[
+	vcdp->chgBus  (c+793,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+794,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	__Vtemp714[0U] = 0U;
+	__Vtemp714[1U] = 0U;
+	__Vtemp714[2U] = 0U;
+	__Vtemp714[3U] = 0U;
+	__Vtemp715[0U] = 0U;
+	__Vtemp715[1U] = 0U;
+	__Vtemp715[2U] = 0U;
+	__Vtemp715[3U] = 0U;
+	__Vtemp716[0U] = 0U;
+	__Vtemp716[1U] = 0U;
+	__Vtemp716[2U] = 0U;
+	__Vtemp716[3U] = 0U;
+	__Vtemp717[0U] = 0U;
+	__Vtemp717[1U] = 0U;
+	__Vtemp717[2U] = 0U;
+	__Vtemp717[3U] = 0U;
+	vcdp->chgBus  (c+795,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+			        ? (0xff00U & (__Vtemp714[
 					      (3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 2U))] 
 					      << 8U))
 			        : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 				    ? (0xff0000U & 
-				       (__Vtemp567[
+				       (__Vtemp715[
 					(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					       >> 2U))] 
 					<< 0x10U)) : 
 				   ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 				     ? (0xff000000U 
-					& (__Vtemp568[
+					& (__Vtemp716[
 					   (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						  >> 2U))] 
 					   << 0x18U))
-				     : __Vtemp569[(3U 
+				     : __Vtemp717[(3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 2U))])))),32);
-	__Vtemp570[0U] = 0U;
-	__Vtemp570[1U] = 0U;
-	__Vtemp570[2U] = 0U;
-	__Vtemp570[3U] = 0U;
-	__Vtemp571[0U] = 0U;
-	__Vtemp571[1U] = 0U;
-	__Vtemp571[2U] = 0U;
-	__Vtemp571[3U] = 0U;
-	vcdp->chgBus  (c+414,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-			        ? (0xffff0000U & (__Vtemp570[
+	__Vtemp718[0U] = 0U;
+	__Vtemp718[1U] = 0U;
+	__Vtemp718[2U] = 0U;
+	__Vtemp718[3U] = 0U;
+	__Vtemp719[0U] = 0U;
+	__Vtemp719[1U] = 0U;
+	__Vtemp719[2U] = 0U;
+	__Vtemp719[3U] = 0U;
+	vcdp->chgBus  (c+796,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+			        ? (0xffff0000U & (__Vtemp718[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 2U))] 
 						  << 0x10U))
-			        : __Vtemp571[(3U & 
+			        : __Vtemp719[(3U & 
 					      ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					       >> 2U))])),32);
-	vcdp->chgBus  (c+415,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__use_write_data),32);
-	vcdp->chgBus  (c+416,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
+	vcdp->chgBus  (c+797,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__use_write_data),32);
+	vcdp->chgBus  (c+798,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 			        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 				    ? (0xffffff00U 
 				       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
@@ -807,54 +1367,76 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 					    ? (0xffU 
 					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 					    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
-	vcdp->chgBus  (c+417,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4);
-	vcdp->chgBus  (c+418,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+	vcdp->chgBus  (c+799,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->chgBus  (c+800,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 			        ? 3U : 0xcU)),4);
-	vcdp->chgBus  (c+419,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16);
-	vcdp->chgArray(c+420,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128);
-	vcdp->chgBit  (c+424,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
-	vcdp->chgBus  (c+425,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
-	vcdp->chgBus  (c+426,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
-	vcdp->chgArray(c+427,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
-	vcdp->chgBus  (c+435,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
-	vcdp->chgBus  (c+436,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
-	vcdp->chgBus  (c+437,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
-	vcdp->chgBit  (c+438,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
-	vcdp->chgBus  (c+439,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
-	vcdp->chgBit  (c+440,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
-	__Vtemp572[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
-	__Vtemp572[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
-	__Vtemp572[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
-	__Vtemp572[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
-	vcdp->chgArray(c+441,(__Vtemp572),128);
-	vcdp->chgBit  (c+445,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
-	vcdp->chgBit  (c+446,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->chgBus  (c+801,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->chgArray(c+802,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->chgBit  (c+806,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
+	vcdp->chgBit  (c+807,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
+	vcdp->chgBit  (c+808,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
+	vcdp->chgBit  (c+809,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
+	vcdp->chgQuad (c+810,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->chgArray(c+812,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->chgBus  (c+820,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->chgBus  (c+821,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->chgBus  (c+822,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->chgBus  (c+823,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->chgArray(c+824,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->chgBus  (c+832,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->chgBit  (c+833,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->chgBus  (c+834,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->chgBus  (c+835,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->chgBus  (c+836,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->chgBus  (c+837,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->chgBit  (c+838,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->chgBus  (c+839,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->chgBit  (c+840,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp720[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp720[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp720[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp720[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->chgArray(c+841,(__Vtemp720),128);
+	vcdp->chgBit  (c+845,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+846,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->chgBit  (c+847,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				     | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->chgBit  (c+848,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				      ? 0U : (0U != 
 					      (0xffffU 
 					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
-	vcdp->chgBus  (c+447,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	vcdp->chgBus  (c+849,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 					  >> 0x10U))),16);
-	vcdp->chgBit  (c+448,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+	vcdp->chgBit  (c+850,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
 				     >> 1U))));
-	__Vtemp573[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
-	__Vtemp573[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
-	__Vtemp573[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
-	__Vtemp573[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
-	vcdp->chgArray(c+449,(__Vtemp573),128);
-	vcdp->chgBit  (c+453,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	__Vtemp721[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp721[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp721[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp721[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->chgArray(c+851,(__Vtemp721),128);
+	vcdp->chgBit  (c+855,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+856,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						 >> 0x10U)))));
-	vcdp->chgBit  (c+454,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->chgBit  (c+857,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))) 
+				     | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					>> 1U)))));
+	vcdp->chgBit  (c+858,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				      ? 0U : (0U != 
 					      (0xffffU 
 					       & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						  >> 0x10U)))))));
-	__Vtemp574[0U] = 0U;
-	__Vtemp574[1U] = 0U;
-	__Vtemp574[2U] = 0U;
-	__Vtemp574[3U] = 0U;
-	vcdp->chgBus  (c+455,(__Vtemp574[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
+	__Vtemp722[0U] = 0U;
+	__Vtemp722[1U] = 0U;
+	__Vtemp722[2U] = 0U;
+	__Vtemp722[3U] = 0U;
+	vcdp->chgBus  (c+859,(__Vtemp722[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 4U))]),32);
-	vcdp->chgBus  (c+456,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
+	vcdp->chgBus  (c+860,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
 			        ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				    ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 				        ? (0xffffff00U 
@@ -876,93 +1458,92 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 						   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 					        : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))
 			        : 0U)),32);
-	vcdp->chgBit  (c+457,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) 
+	vcdp->chgBit  (c+861,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) 
 				& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
 				   == (0x1fffffU & 
 				       (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
 					>> 0xbU)))) 
 			       & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use))));
-	vcdp->chgBus  (c+458,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
-			       << 0xbU)),32);
-	vcdp->chgArray(c+459,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
-	vcdp->chgBus  (c+463,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21);
-	vcdp->chgBit  (c+464,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use));
-	vcdp->chgBit  (c+465,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access));
-	vcdp->chgBit  (c+466,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem));
-	vcdp->chgBit  (c+467,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
-				 != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
-						  >> 0xbU))) 
-				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)) 
-			       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in))));
-	vcdp->chgBit  (c+468,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+469,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+470,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+471,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
-	vcdp->chgBus  (c+472,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32);
-	vcdp->chgBus  (c+473,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->chgBit  (c+862,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->chgBus  (c+863,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
+				<< 0xbU) | (0x7c0U 
+					    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))),32);
+	vcdp->chgArray(c+864,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->chgBus  (c+868,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->chgBit  (c+869,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->chgBit  (c+870,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access));
+	vcdp->chgBit  (c+871,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->chgBit  (c+872,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__miss));
+	vcdp->chgBit  (c+873,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+874,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+875,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+876,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->chgBus  (c+877,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->chgBus  (c+878,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 			        ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 			        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->chgBus  (c+474,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->chgBus  (c+879,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 			        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 			        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->chgBus  (c+475,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	vcdp->chgBus  (c+476,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	__Vtemp575[0U] = 0U;
-	__Vtemp575[1U] = 0U;
-	__Vtemp575[2U] = 0U;
-	__Vtemp575[3U] = 0U;
-	__Vtemp576[0U] = 0U;
-	__Vtemp576[1U] = 0U;
-	__Vtemp576[2U] = 0U;
-	__Vtemp576[3U] = 0U;
-	__Vtemp577[0U] = 0U;
-	__Vtemp577[1U] = 0U;
-	__Vtemp577[2U] = 0U;
-	__Vtemp577[3U] = 0U;
-	__Vtemp578[0U] = 0U;
-	__Vtemp578[1U] = 0U;
-	__Vtemp578[2U] = 0U;
-	__Vtemp578[3U] = 0U;
-	vcdp->chgBus  (c+477,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-			        ? (0xff00U & (__Vtemp575[
+	vcdp->chgBus  (c+880,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+881,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	__Vtemp723[0U] = 0U;
+	__Vtemp723[1U] = 0U;
+	__Vtemp723[2U] = 0U;
+	__Vtemp723[3U] = 0U;
+	__Vtemp724[0U] = 0U;
+	__Vtemp724[1U] = 0U;
+	__Vtemp724[2U] = 0U;
+	__Vtemp724[3U] = 0U;
+	__Vtemp725[0U] = 0U;
+	__Vtemp725[1U] = 0U;
+	__Vtemp725[2U] = 0U;
+	__Vtemp725[3U] = 0U;
+	__Vtemp726[0U] = 0U;
+	__Vtemp726[1U] = 0U;
+	__Vtemp726[2U] = 0U;
+	__Vtemp726[3U] = 0U;
+	vcdp->chgBus  (c+882,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+			        ? (0xff00U & (__Vtemp723[
 					      (3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 4U))] 
 					      << 8U))
 			        : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 				    ? (0xff0000U & 
-				       (__Vtemp576[
+				       (__Vtemp724[
 					(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					       >> 4U))] 
 					<< 0x10U)) : 
 				   ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 				     ? (0xff000000U 
-					& (__Vtemp577[
+					& (__Vtemp725[
 					   (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						  >> 4U))] 
 					   << 0x18U))
-				     : __Vtemp578[(3U 
+				     : __Vtemp726[(3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 4U))])))),32);
-	__Vtemp579[0U] = 0U;
-	__Vtemp579[1U] = 0U;
-	__Vtemp579[2U] = 0U;
-	__Vtemp579[3U] = 0U;
-	__Vtemp580[0U] = 0U;
-	__Vtemp580[1U] = 0U;
-	__Vtemp580[2U] = 0U;
-	__Vtemp580[3U] = 0U;
-	vcdp->chgBus  (c+478,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-			        ? (0xffff0000U & (__Vtemp579[
+	__Vtemp727[0U] = 0U;
+	__Vtemp727[1U] = 0U;
+	__Vtemp727[2U] = 0U;
+	__Vtemp727[3U] = 0U;
+	__Vtemp728[0U] = 0U;
+	__Vtemp728[1U] = 0U;
+	__Vtemp728[2U] = 0U;
+	__Vtemp728[3U] = 0U;
+	vcdp->chgBus  (c+883,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+			        ? (0xffff0000U & (__Vtemp727[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 4U))] 
 						  << 0x10U))
-			        : __Vtemp580[(3U & 
+			        : __Vtemp728[(3U & 
 					      ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					       >> 4U))])),32);
-	vcdp->chgBus  (c+479,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__use_write_data),32);
-	vcdp->chgBus  (c+480,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
+	vcdp->chgBus  (c+884,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__use_write_data),32);
+	vcdp->chgBus  (c+885,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 			        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 				    ? (0xffffff00U 
 				       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
@@ -980,54 +1561,76 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 					    ? (0xffU 
 					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 					    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
-	vcdp->chgBus  (c+481,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4);
-	vcdp->chgBus  (c+482,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+	vcdp->chgBus  (c+886,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->chgBus  (c+887,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 			        ? 3U : 0xcU)),4);
-	vcdp->chgBus  (c+483,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16);
-	vcdp->chgArray(c+484,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128);
-	vcdp->chgBit  (c+488,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
-	vcdp->chgBus  (c+489,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
-	vcdp->chgBus  (c+490,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
-	vcdp->chgArray(c+491,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
-	vcdp->chgBus  (c+499,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
-	vcdp->chgBus  (c+500,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
-	vcdp->chgBus  (c+501,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
-	vcdp->chgBit  (c+502,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
-	vcdp->chgBus  (c+503,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
-	vcdp->chgBit  (c+504,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
-	__Vtemp581[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
-	__Vtemp581[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
-	__Vtemp581[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
-	__Vtemp581[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
-	vcdp->chgArray(c+505,(__Vtemp581),128);
-	vcdp->chgBit  (c+509,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
-	vcdp->chgBit  (c+510,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->chgBus  (c+888,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->chgArray(c+889,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->chgBit  (c+893,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
+	vcdp->chgBit  (c+894,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
+	vcdp->chgBit  (c+895,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
+	vcdp->chgBit  (c+896,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
+	vcdp->chgQuad (c+897,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->chgArray(c+899,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->chgBus  (c+907,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->chgBus  (c+908,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->chgBus  (c+909,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->chgBus  (c+910,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->chgArray(c+911,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->chgBus  (c+919,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->chgBit  (c+920,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->chgBus  (c+921,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->chgBus  (c+922,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->chgBus  (c+923,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->chgBus  (c+924,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->chgBit  (c+925,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->chgBus  (c+926,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->chgBit  (c+927,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp729[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp729[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp729[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp729[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->chgArray(c+928,(__Vtemp729),128);
+	vcdp->chgBit  (c+932,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+933,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->chgBit  (c+934,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				     | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->chgBit  (c+935,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				      ? 0U : (0U != 
 					      (0xffffU 
 					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
-	vcdp->chgBus  (c+511,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	vcdp->chgBus  (c+936,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 					  >> 0x10U))),16);
-	vcdp->chgBit  (c+512,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+	vcdp->chgBit  (c+937,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
 				     >> 1U))));
-	__Vtemp582[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
-	__Vtemp582[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
-	__Vtemp582[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
-	__Vtemp582[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
-	vcdp->chgArray(c+513,(__Vtemp582),128);
-	vcdp->chgBit  (c+517,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	__Vtemp730[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp730[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp730[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp730[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->chgArray(c+938,(__Vtemp730),128);
+	vcdp->chgBit  (c+942,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+943,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						 >> 0x10U)))));
-	vcdp->chgBit  (c+518,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->chgBit  (c+944,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				      & (0U != (0xffffU 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))) 
+				     | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					>> 1U)))));
+	vcdp->chgBit  (c+945,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				      ? 0U : (0U != 
 					      (0xffffU 
 					       & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						  >> 0x10U)))))));
-	__Vtemp583[0U] = 0U;
-	__Vtemp583[1U] = 0U;
-	__Vtemp583[2U] = 0U;
-	__Vtemp583[3U] = 0U;
-	vcdp->chgBus  (c+519,(__Vtemp583[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
+	__Vtemp731[0U] = 0U;
+	__Vtemp731[1U] = 0U;
+	__Vtemp731[2U] = 0U;
+	__Vtemp731[3U] = 0U;
+	vcdp->chgBus  (c+946,(__Vtemp731[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 6U))]),32);
-	vcdp->chgBus  (c+520,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
+	vcdp->chgBus  (c+947,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
 			        ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				    ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 				        ? (0xffffff00U 
@@ -1049,93 +1652,92 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 						   & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 					        : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))
 			        : 0U)),32);
-	vcdp->chgBit  (c+521,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) 
+	vcdp->chgBit  (c+948,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) 
 				& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
 				   == (0x1fffffU & 
 				       (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
 					>> 0xbU)))) 
 			       & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use))));
-	vcdp->chgBus  (c+522,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
-			       << 0xbU)),32);
-	vcdp->chgArray(c+523,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
-	vcdp->chgBus  (c+527,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21);
-	vcdp->chgBit  (c+528,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use));
-	vcdp->chgBit  (c+529,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access));
-	vcdp->chgBit  (c+530,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem));
-	vcdp->chgBit  (c+531,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
-				 != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
-						  >> 0xbU))) 
-				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)) 
-			       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in))));
-	vcdp->chgBit  (c+532,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+533,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+534,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
-	vcdp->chgBit  (c+535,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
-	vcdp->chgBus  (c+536,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32);
-	vcdp->chgBus  (c+537,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->chgBit  (c+949,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				     >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->chgBus  (c+950,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
+				<< 0xbU) | (0x7c0U 
+					    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))),32);
+	vcdp->chgArray(c+951,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->chgBus  (c+955,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->chgBit  (c+956,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->chgBit  (c+957,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access));
+	vcdp->chgBit  (c+958,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->chgBit  (c+959,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__miss));
+	vcdp->chgBit  (c+960,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+961,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+962,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->chgBit  (c+963,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->chgBus  (c+964,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->chgBus  (c+965,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 			        ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 			        : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->chgBus  (c+538,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->chgBus  (c+966,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 			        ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 			        : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->chgBus  (c+539,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	vcdp->chgBus  (c+540,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	__Vtemp584[0U] = 0U;
-	__Vtemp584[1U] = 0U;
-	__Vtemp584[2U] = 0U;
-	__Vtemp584[3U] = 0U;
-	__Vtemp585[0U] = 0U;
-	__Vtemp585[1U] = 0U;
-	__Vtemp585[2U] = 0U;
-	__Vtemp585[3U] = 0U;
-	__Vtemp586[0U] = 0U;
-	__Vtemp586[1U] = 0U;
-	__Vtemp586[2U] = 0U;
-	__Vtemp586[3U] = 0U;
-	__Vtemp587[0U] = 0U;
-	__Vtemp587[1U] = 0U;
-	__Vtemp587[2U] = 0U;
-	__Vtemp587[3U] = 0U;
-	vcdp->chgBus  (c+541,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-			        ? (0xff00U & (__Vtemp584[
+	vcdp->chgBus  (c+967,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->chgBus  (c+968,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	__Vtemp732[0U] = 0U;
+	__Vtemp732[1U] = 0U;
+	__Vtemp732[2U] = 0U;
+	__Vtemp732[3U] = 0U;
+	__Vtemp733[0U] = 0U;
+	__Vtemp733[1U] = 0U;
+	__Vtemp733[2U] = 0U;
+	__Vtemp733[3U] = 0U;
+	__Vtemp734[0U] = 0U;
+	__Vtemp734[1U] = 0U;
+	__Vtemp734[2U] = 0U;
+	__Vtemp734[3U] = 0U;
+	__Vtemp735[0U] = 0U;
+	__Vtemp735[1U] = 0U;
+	__Vtemp735[2U] = 0U;
+	__Vtemp735[3U] = 0U;
+	vcdp->chgBus  (c+969,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+			        ? (0xff00U & (__Vtemp732[
 					      (3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 6U))] 
 					      << 8U))
 			        : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 				    ? (0xff0000U & 
-				       (__Vtemp585[
+				       (__Vtemp733[
 					(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					       >> 6U))] 
 					<< 0x10U)) : 
 				   ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 				     ? (0xff000000U 
-					& (__Vtemp586[
+					& (__Vtemp734[
 					   (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						  >> 6U))] 
 					   << 0x18U))
-				     : __Vtemp587[(3U 
+				     : __Vtemp735[(3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 6U))])))),32);
-	__Vtemp588[0U] = 0U;
-	__Vtemp588[1U] = 0U;
-	__Vtemp588[2U] = 0U;
-	__Vtemp588[3U] = 0U;
-	__Vtemp589[0U] = 0U;
-	__Vtemp589[1U] = 0U;
-	__Vtemp589[2U] = 0U;
-	__Vtemp589[3U] = 0U;
-	vcdp->chgBus  (c+542,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-			        ? (0xffff0000U & (__Vtemp588[
+	__Vtemp736[0U] = 0U;
+	__Vtemp736[1U] = 0U;
+	__Vtemp736[2U] = 0U;
+	__Vtemp736[3U] = 0U;
+	__Vtemp737[0U] = 0U;
+	__Vtemp737[1U] = 0U;
+	__Vtemp737[2U] = 0U;
+	__Vtemp737[3U] = 0U;
+	vcdp->chgBus  (c+970,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+			        ? (0xffff0000U & (__Vtemp736[
 						  (3U 
 						   & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						      >> 6U))] 
 						  << 0x10U))
-			        : __Vtemp589[(3U & 
+			        : __Vtemp737[(3U & 
 					      ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					       >> 6U))])),32);
-	vcdp->chgBus  (c+543,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__use_write_data),32);
-	vcdp->chgBus  (c+544,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
+	vcdp->chgBus  (c+971,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__use_write_data),32);
+	vcdp->chgBus  (c+972,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 			        ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 				    ? (0xffffff00U 
 				       | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
@@ -1153,47 +1755,69 @@ void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, Verilat
 					    ? (0xffU 
 					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 					    : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
-	vcdp->chgBus  (c+545,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4);
-	vcdp->chgBus  (c+546,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+	vcdp->chgBus  (c+973,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->chgBus  (c+974,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 			        ? 3U : 0xcU)),4);
-	vcdp->chgBus  (c+547,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16);
-	vcdp->chgArray(c+548,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128);
-	vcdp->chgBit  (c+552,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
-	vcdp->chgBus  (c+553,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
-	vcdp->chgBus  (c+554,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
-	vcdp->chgArray(c+555,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
-	vcdp->chgBus  (c+563,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
-	vcdp->chgBus  (c+564,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
-	vcdp->chgBus  (c+565,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
-	vcdp->chgBit  (c+566,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
-	vcdp->chgBus  (c+567,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
-	vcdp->chgBit  (c+568,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
-	__Vtemp590[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
-	__Vtemp590[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
-	__Vtemp590[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
-	__Vtemp590[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
-	vcdp->chgArray(c+569,(__Vtemp590),128);
-	vcdp->chgBit  (c+573,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
-	vcdp->chgBit  (c+574,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
-				      ? 0U : (0U != 
-					      (0xffffU 
-					       & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
-	vcdp->chgBus  (c+575,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
-					  >> 0x10U))),16);
-	vcdp->chgBit  (c+576,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
-				     >> 1U))));
-	__Vtemp591[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
-	__Vtemp591[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
-	__Vtemp591[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
-	__Vtemp591[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
-	vcdp->chgArray(c+577,(__Vtemp591),128);
-	vcdp->chgBit  (c+581,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
-						 >> 0x10U)))));
-	vcdp->chgBit  (c+582,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
-				      ? 0U : (0U != 
-					      (0xffffU 
-					       & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
-						  >> 0x10U)))))));
+	vcdp->chgBus  (c+975,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->chgArray(c+976,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->chgBit  (c+980,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
+	vcdp->chgBit  (c+981,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
+	vcdp->chgBit  (c+982,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
+	vcdp->chgBit  (c+983,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
+	vcdp->chgQuad (c+984,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->chgArray(c+986,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->chgBus  (c+994,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->chgBus  (c+995,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->chgBus  (c+996,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->chgBus  (c+997,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->chgArray(c+998,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->chgBus  (c+1006,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->chgBit  (c+1007,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->chgBus  (c+1008,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->chgBus  (c+1009,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->chgBus  (c+1010,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->chgBus  (c+1011,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->chgBit  (c+1012,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->chgBus  (c+1013,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->chgBit  (c+1014,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp738[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp738[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp738[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp738[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->chgArray(c+1015,(__Vtemp738),128);
+	vcdp->chgBit  (c+1019,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+1020,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->chgBit  (c+1021,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				      | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->chgBit  (c+1022,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				       ? 0U : (0U != 
+					       (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
+	vcdp->chgBus  (c+1023,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+					   >> 0x10U))),16);
+	vcdp->chgBit  (c+1024,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+				      >> 1U))));
+	__Vtemp739[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp739[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp739[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp739[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->chgArray(c+1025,(__Vtemp739),128);
+	vcdp->chgBit  (c+1029,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->chgBit  (c+1030,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						  >> 0x10U)))));
+	vcdp->chgBit  (c+1031,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						    >> 0x10U)))) 
+				      | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					 >> 1U)))));
+	vcdp->chgBit  (c+1032,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				       ? 0U : (0U != 
+					       (0xffffU 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))))));
     }
 }
 
@@ -1202,449 +1826,6 @@ void Vcache_simX::traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, Verilat
     int c=code;
     if (0 && vcdp && c) {}  // Prevent unused
     // Variables
-    VL_SIGW(__Vtemp594,127,0,4);
-    VL_SIGW(__Vtemp597,127,0,4);
-    VL_SIGW(__Vtemp600,127,0,4);
-    VL_SIGW(__Vtemp603,127,0,4);
-    VL_SIGW(__Vtemp604,127,0,4);
-    // Body
-    {
-	vcdp->chgBit  (c+583,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
-			       | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))));
-	vcdp->chgBus  (c+584,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)
-			        ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read
-			        : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read)),32);
-	vcdp->chgBit  (c+585,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) 
-			       | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)))));
-	vcdp->chgBit  (c+586,((1U & ((~ ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
-					 | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))) 
-				     & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)))));
-	vcdp->chgBus  (c+587,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
-			        ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) 
-				   & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))
-			        : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) 
-				   & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))))),4);
-	__Vtemp594[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
-			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
-			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]);
-	__Vtemp594[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
-			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
-			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]);
-	__Vtemp594[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
-			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
-			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]);
-	__Vtemp594[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
-			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
-			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]);
-	vcdp->chgArray(c+588,(__Vtemp594),128);
-	__Vtemp597[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
-			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
-			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
-				     >> 7U))][0U]);
-	__Vtemp597[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
-			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
-			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
-				     >> 7U))][1U]);
-	__Vtemp597[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
-			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
-			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
-				     >> 7U))][2U]);
-	__Vtemp597[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
-			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
-			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
-				     >> 7U))][3U]);
-	vcdp->chgArray(c+592,(__Vtemp597),128);
-	__Vtemp600[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
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-						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
-				     | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
-	vcdp->chgBit  (c+627,((1U & (((~ vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty
-				       [0U]) & (0U 
-						!= 
-						(0xffffU 
-						 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
-						    >> 0x10U)))) 
-				     | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
-					>> 1U)))));
-    }
-}
-
-void Vcache_simX::traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
-    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    int c=code;
-    if (0 && vcdp && c) {}  // Prevent unused
-    // Body
-    {
-	vcdp->chgBus  (c+628,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update),1);
-	vcdp->chgQuad (c+629,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way),46);
-	vcdp->chgArray(c+631,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way),256);
-	vcdp->chgBus  (c+639,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way),2);
-	vcdp->chgBus  (c+640,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way),2);
-	vcdp->chgBit  (c+641,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found));
-	vcdp->chgBus  (c+642,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index),1);
-	vcdp->chgBus  (c+643,((3U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))),2);
-	vcdp->chgBus  (c+644,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__way_to_update),1);
-	vcdp->chgQuad (c+645,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
-	vcdp->chgArray(c+647,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
-	vcdp->chgBus  (c+655,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
-	vcdp->chgBus  (c+656,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
-	vcdp->chgBit  (c+657,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
-	vcdp->chgBus  (c+658,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
-	vcdp->chgBus  (c+659,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
-	vcdp->chgBus  (c+660,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__way_to_update),1);
-	vcdp->chgQuad (c+661,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
-	vcdp->chgArray(c+663,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
-	vcdp->chgBus  (c+671,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
-	vcdp->chgBus  (c+672,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
-	vcdp->chgBit  (c+673,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
-	vcdp->chgBus  (c+674,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
-	vcdp->chgBus  (c+675,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
-	vcdp->chgBus  (c+676,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__way_to_update),1);
-	vcdp->chgQuad (c+677,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
-	vcdp->chgArray(c+679,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
-	vcdp->chgBus  (c+687,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
-	vcdp->chgBus  (c+688,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
-	vcdp->chgBit  (c+689,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
-	vcdp->chgBus  (c+690,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
-	vcdp->chgBus  (c+691,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
-	vcdp->chgBus  (c+692,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__way_to_update),1);
-	vcdp->chgQuad (c+693,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
-	vcdp->chgArray(c+695,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
-	vcdp->chgBus  (c+703,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
-	vcdp->chgBus  (c+704,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
-	vcdp->chgBit  (c+705,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
-	vcdp->chgBus  (c+706,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
-	vcdp->chgBus  (c+707,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
-    }
-}
-
-void Vcache_simX::traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
-    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    int c=code;
-    if (0 && vcdp && c) {}  // Prevent unused
-    // Variables
-    VL_SIGW(__Vtemp605,127,0,4);
-    VL_SIGW(__Vtemp606,127,0,4);
-    VL_SIGW(__Vtemp607,127,0,4);
-    VL_SIGW(__Vtemp608,127,0,4);
-    VL_SIGW(__Vtemp609,127,0,4);
-    VL_SIGW(__Vtemp610,127,0,4);
-    VL_SIGW(__Vtemp611,127,0,4);
-    VL_SIGW(__Vtemp612,127,0,4);
-    VL_SIGW(__Vtemp613,127,0,4);
-    VL_SIGW(__Vtemp614,127,0,4);
-    VL_SIGW(__Vtemp615,127,0,4);
-    VL_SIGW(__Vtemp616,127,0,4);
-    VL_SIGW(__Vtemp617,127,0,4);
-    VL_SIGW(__Vtemp618,127,0,4);
-    VL_SIGW(__Vtemp619,127,0,4);
-    VL_SIGW(__Vtemp620,127,0,4);
-    VL_SIGW(__Vtemp621,127,0,4);
-    VL_SIGW(__Vtemp622,127,0,4);
-    VL_SIGW(__Vtemp623,127,0,4);
-    VL_SIGW(__Vtemp624,127,0,4);
-    VL_SIGW(__Vtemp625,127,0,4);
-    VL_SIGW(__Vtemp626,127,0,4);
-    VL_SIGW(__Vtemp627,127,0,4);
-    VL_SIGW(__Vtemp628,127,0,4);
-    VL_SIGW(__Vtemp629,127,0,4);
-    VL_SIGW(__Vtemp630,127,0,4);
-    VL_SIGW(__Vtemp631,127,0,4);
-    VL_SIGW(__Vtemp632,127,0,4);
-    VL_SIGW(__Vtemp633,127,0,4);
-    VL_SIGW(__Vtemp634,127,0,4);
-    VL_SIGW(__Vtemp635,127,0,4);
-    VL_SIGW(__Vtemp636,127,0,4);
-    VL_SIGW(__Vtemp637,127,0,4);
-    VL_SIGW(__Vtemp638,127,0,4);
-    VL_SIGW(__Vtemp639,127,0,4);
-    VL_SIGW(__Vtemp640,127,0,4);
-    VL_SIGW(__Vtemp641,127,0,4);
-    VL_SIGW(__Vtemp642,127,0,4);
-    VL_SIGW(__Vtemp643,127,0,4);
-    VL_SIGW(__Vtemp644,127,0,4);
-    VL_SIGW(__Vtemp645,127,0,4);
-    VL_SIGW(__Vtemp646,127,0,4);
-    VL_SIGW(__Vtemp647,127,0,4);
-    VL_SIGW(__Vtemp648,127,0,4);
-    VL_SIGW(__Vtemp649,127,0,4);
-    VL_SIGW(__Vtemp650,127,0,4);
-    VL_SIGW(__Vtemp651,127,0,4);
-    VL_SIGW(__Vtemp652,127,0,4);
-    VL_SIGW(__Vtemp653,127,0,4);
-    VL_SIGW(__Vtemp654,127,0,4);
-    VL_SIGW(__Vtemp655,127,0,4);
-    VL_SIGW(__Vtemp656,127,0,4);
-    VL_SIGW(__Vtemp657,127,0,4);
-    VL_SIGW(__Vtemp658,127,0,4);
-    VL_SIGW(__Vtemp659,127,0,4);
-    VL_SIGW(__Vtemp660,127,0,4);
-    VL_SIGW(__Vtemp661,127,0,4);
-    VL_SIGW(__Vtemp662,127,0,4);
-    VL_SIGW(__Vtemp663,127,0,4);
-    VL_SIGW(__Vtemp664,127,0,4);
-    VL_SIGW(__Vtemp665,127,0,4);
-    VL_SIGW(__Vtemp666,127,0,4);
-    VL_SIGW(__Vtemp667,127,0,4);
-    VL_SIGW(__Vtemp668,127,0,4);
-    VL_SIGW(__Vtemp669,127,0,4);
-    VL_SIGW(__Vtemp670,127,0,4);
-    VL_SIGW(__Vtemp671,127,0,4);
-    VL_SIGW(__Vtemp672,127,0,4);
-    VL_SIGW(__Vtemp673,127,0,4);
-    VL_SIGW(__Vtemp674,127,0,4);
-    VL_SIGW(__Vtemp675,127,0,4);
-    VL_SIGW(__Vtemp676,127,0,4);
-    VL_SIGW(__Vtemp677,127,0,4);
-    VL_SIGW(__Vtemp678,127,0,4);
-    VL_SIGW(__Vtemp679,127,0,4);
-    VL_SIGW(__Vtemp680,127,0,4);
-    VL_SIGW(__Vtemp681,127,0,4);
-    VL_SIGW(__Vtemp682,127,0,4);
-    VL_SIGW(__Vtemp683,127,0,4);
-    VL_SIGW(__Vtemp684,127,0,4);
-    VL_SIGW(__Vtemp685,127,0,4);
-    VL_SIGW(__Vtemp686,127,0,4);
-    VL_SIGW(__Vtemp687,127,0,4);
-    VL_SIGW(__Vtemp688,127,0,4);
-    VL_SIGW(__Vtemp689,127,0,4);
-    VL_SIGW(__Vtemp690,127,0,4);
-    VL_SIGW(__Vtemp691,127,0,4);
-    VL_SIGW(__Vtemp692,127,0,4);
-    VL_SIGW(__Vtemp693,127,0,4);
-    VL_SIGW(__Vtemp694,127,0,4);
-    VL_SIGW(__Vtemp695,127,0,4);
-    VL_SIGW(__Vtemp696,127,0,4);
-    VL_SIGW(__Vtemp697,127,0,4);
-    VL_SIGW(__Vtemp698,127,0,4);
-    VL_SIGW(__Vtemp699,127,0,4);
-    VL_SIGW(__Vtemp700,127,0,4);
-    VL_SIGW(__Vtemp701,127,0,4);
-    VL_SIGW(__Vtemp702,127,0,4);
-    VL_SIGW(__Vtemp703,127,0,4);
-    VL_SIGW(__Vtemp704,127,0,4);
-    VL_SIGW(__Vtemp705,127,0,4);
-    VL_SIGW(__Vtemp706,127,0,4);
-    VL_SIGW(__Vtemp707,127,0,4);
-    VL_SIGW(__Vtemp708,127,0,4);
-    VL_SIGW(__Vtemp709,127,0,4);
-    VL_SIGW(__Vtemp710,127,0,4);
-    VL_SIGW(__Vtemp711,127,0,4);
-    VL_SIGW(__Vtemp712,127,0,4);
-    VL_SIGW(__Vtemp713,127,0,4);
-    VL_SIGW(__Vtemp714,127,0,4);
-    VL_SIGW(__Vtemp715,127,0,4);
-    VL_SIGW(__Vtemp716,127,0,4);
-    VL_SIGW(__Vtemp717,127,0,4);
-    VL_SIGW(__Vtemp718,127,0,4);
-    VL_SIGW(__Vtemp719,127,0,4);
-    VL_SIGW(__Vtemp720,127,0,4);
-    VL_SIGW(__Vtemp721,127,0,4);
-    VL_SIGW(__Vtemp722,127,0,4);
-    VL_SIGW(__Vtemp723,127,0,4);
-    VL_SIGW(__Vtemp724,127,0,4);
-    VL_SIGW(__Vtemp725,127,0,4);
-    VL_SIGW(__Vtemp726,127,0,4);
-    VL_SIGW(__Vtemp727,127,0,4);
-    VL_SIGW(__Vtemp728,127,0,4);
-    VL_SIGW(__Vtemp729,127,0,4);
-    VL_SIGW(__Vtemp730,127,0,4);
-    VL_SIGW(__Vtemp731,127,0,4);
-    VL_SIGW(__Vtemp732,127,0,4);
-    VL_SIGW(__Vtemp733,127,0,4);
-    VL_SIGW(__Vtemp734,127,0,4);
-    VL_SIGW(__Vtemp735,127,0,4);
-    VL_SIGW(__Vtemp736,127,0,4);
-    VL_SIGW(__Vtemp737,127,0,4);
-    VL_SIGW(__Vtemp738,127,0,4);
-    VL_SIGW(__Vtemp739,127,0,4);
-    VL_SIGW(__Vtemp740,127,0,4);
-    VL_SIGW(__Vtemp741,127,0,4);
-    VL_SIGW(__Vtemp742,127,0,4);
-    VL_SIGW(__Vtemp743,127,0,4);
-    VL_SIGW(__Vtemp744,127,0,4);
-    VL_SIGW(__Vtemp745,127,0,4);
-    VL_SIGW(__Vtemp746,127,0,4);
-    VL_SIGW(__Vtemp747,127,0,4);
-    VL_SIGW(__Vtemp748,127,0,4);
-    VL_SIGW(__Vtemp749,127,0,4);
-    VL_SIGW(__Vtemp750,127,0,4);
-    VL_SIGW(__Vtemp751,127,0,4);
     VL_SIGW(__Vtemp752,127,0,4);
     VL_SIGW(__Vtemp753,127,0,4);
     VL_SIGW(__Vtemp754,127,0,4);
@@ -1661,6 +1842,431 @@ void Vcache_simX::traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, Verilat
     VL_SIGW(__Vtemp765,127,0,4);
     VL_SIGW(__Vtemp766,127,0,4);
     VL_SIGW(__Vtemp767,127,0,4);
+    VL_SIGW(__Vtemp742,127,0,4);
+    VL_SIGW(__Vtemp745,127,0,4);
+    VL_SIGW(__Vtemp748,127,0,4);
+    VL_SIGW(__Vtemp751,127,0,4);
+    // Body
+    {
+	vcdp->chgBit  (c+1033,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
+				| (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))));
+	vcdp->chgBus  (c+1034,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual)
+				 ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read
+				 : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read)),32);
+	vcdp->chgBit  (c+1035,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) 
+				| (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)))));
+	vcdp->chgBit  (c+1036,((1U & ((~ ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
+					  | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))) 
+				      & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)))));
+	vcdp->chgBus  (c+1037,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
+				 ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) 
+				    & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))
+				 : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) 
+				    & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))))),4);
+	__Vtemp742[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]);
+	__Vtemp742[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]);
+	__Vtemp742[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]);
+	__Vtemp742[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]);
+	vcdp->chgArray(c+1038,(__Vtemp742),128);
+	__Vtemp745[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 7U))][0U]);
+	__Vtemp745[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 7U))][1U]);
+	__Vtemp745[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 7U))][2U]);
+	__Vtemp745[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 7U))][3U]);
+	vcdp->chgArray(c+1042,(__Vtemp745),128);
+	__Vtemp748[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 0xeU))][0U]);
+	__Vtemp748[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 0xeU))][1U]);
+	__Vtemp748[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 0xeU))][2U]);
+	__Vtemp748[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 0xeU))][3U]);
+	vcdp->chgArray(c+1046,(__Vtemp748),128);
+	__Vtemp751[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 0x15U))][0U]);
+	__Vtemp751[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 0x15U))][1U]);
+	__Vtemp751[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 0x15U))][2U]);
+	__Vtemp751[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
+			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
+			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
+				     >> 0x15U))][3U]);
+	vcdp->chgArray(c+1050,(__Vtemp751),128);
+	vcdp->chgBit  (c+1054,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
+				& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)))));
+	vcdp->chgBit  (c+1055,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
+				& (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state)))));
+	vcdp->chgBit  (c+1056,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+				& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb)))));
+	vcdp->chgBit  (c+1057,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+				& (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state)))));
+	vcdp->chgBit  (c+1058,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
+				| ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
+				   | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))))));
+	vcdp->chgBus  (c+1059,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp752[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp752[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp752[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp752[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1060,(__Vtemp752),128);
+	vcdp->chgBit  (c+1064,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1065,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp753[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp753[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp753[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp753[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1066,(__Vtemp753),128);
+	vcdp->chgBit  (c+1070,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1071,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp754[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp754[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp754[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp754[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1072,(__Vtemp754),128);
+	vcdp->chgBit  (c+1076,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1077,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp755[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp755[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp755[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp755[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1078,(__Vtemp755),128);
+	vcdp->chgBit  (c+1082,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1083,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp756[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp756[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp756[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp756[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1084,(__Vtemp756),128);
+	vcdp->chgBit  (c+1088,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1089,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp757[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp757[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp757[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp757[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1090,(__Vtemp757),128);
+	vcdp->chgBit  (c+1094,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1095,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp758[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp758[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp758[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp758[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1096,(__Vtemp758),128);
+	vcdp->chgBit  (c+1100,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1101,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp759[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp759[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp759[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp759[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1102,(__Vtemp759),128);
+	vcdp->chgBit  (c+1106,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1107,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp760[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp760[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp760[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp760[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1108,(__Vtemp760),128);
+	vcdp->chgBit  (c+1112,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1113,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp761[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp761[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp761[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp761[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1114,(__Vtemp761),128);
+	vcdp->chgBit  (c+1118,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1119,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp762[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp762[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp762[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp762[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1120,(__Vtemp762),128);
+	vcdp->chgBit  (c+1124,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1125,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp763[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp763[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp763[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp763[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1126,(__Vtemp763),128);
+	vcdp->chgBit  (c+1130,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1131,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp764[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp764[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp764[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp764[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1132,(__Vtemp764),128);
+	vcdp->chgBit  (c+1136,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1137,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp765[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp765[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp765[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp765[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1138,(__Vtemp765),128);
+	vcdp->chgBit  (c+1142,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1143,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp766[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp766[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp766[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp766[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1144,(__Vtemp766),128);
+	vcdp->chgBit  (c+1148,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					  >> 6U))]));
+	vcdp->chgBus  (c+1149,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					  >> 6U))]),21);
+	__Vtemp767[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp767[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp767[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp767[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->chgArray(c+1150,(__Vtemp767),128);
+	vcdp->chgBit  (c+1154,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+			       [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					  >> 6U))]));
+    }
+}
+
+void Vcache_simX::traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
+    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
+    int c=code;
+    if (0 && vcdp && c) {}  // Prevent unused
+    // Body
+    {
+	vcdp->chgBus  (c+1155,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->chgBus  (c+1156,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->chgBus  (c+1157,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->chgBus  (c+1158,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->chgBus  (c+1159,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->chgBus  (c+1160,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->chgBus  (c+1161,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->chgBus  (c+1162,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__way_to_update),1);
+    }
+}
+
+void Vcache_simX::traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) {
+    Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
+    int c=code;
+    if (0 && vcdp && c) {}  // Prevent unused
+    // Variables
     VL_SIGW(__Vtemp768,127,0,4);
     VL_SIGW(__Vtemp769,127,0,4);
     VL_SIGW(__Vtemp770,127,0,4);
@@ -1828,4040 +2434,6551 @@ void Vcache_simX::traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, Verilat
     VL_SIGW(__Vtemp932,127,0,4);
     VL_SIGW(__Vtemp933,127,0,4);
     VL_SIGW(__Vtemp934,127,0,4);
+    VL_SIGW(__Vtemp935,127,0,4);
+    VL_SIGW(__Vtemp936,127,0,4);
+    VL_SIGW(__Vtemp937,127,0,4);
+    VL_SIGW(__Vtemp938,127,0,4);
+    VL_SIGW(__Vtemp939,127,0,4);
+    VL_SIGW(__Vtemp940,127,0,4);
+    VL_SIGW(__Vtemp941,127,0,4);
+    VL_SIGW(__Vtemp942,127,0,4);
+    VL_SIGW(__Vtemp943,127,0,4);
+    VL_SIGW(__Vtemp944,127,0,4);
+    VL_SIGW(__Vtemp945,127,0,4);
+    VL_SIGW(__Vtemp946,127,0,4);
+    VL_SIGW(__Vtemp947,127,0,4);
+    VL_SIGW(__Vtemp948,127,0,4);
+    VL_SIGW(__Vtemp949,127,0,4);
+    VL_SIGW(__Vtemp950,127,0,4);
+    VL_SIGW(__Vtemp951,127,0,4);
+    VL_SIGW(__Vtemp952,127,0,4);
+    VL_SIGW(__Vtemp953,127,0,4);
+    VL_SIGW(__Vtemp954,127,0,4);
+    VL_SIGW(__Vtemp955,127,0,4);
+    VL_SIGW(__Vtemp956,127,0,4);
+    VL_SIGW(__Vtemp957,127,0,4);
+    VL_SIGW(__Vtemp958,127,0,4);
+    VL_SIGW(__Vtemp959,127,0,4);
+    VL_SIGW(__Vtemp960,127,0,4);
+    VL_SIGW(__Vtemp961,127,0,4);
+    VL_SIGW(__Vtemp962,127,0,4);
+    VL_SIGW(__Vtemp963,127,0,4);
+    VL_SIGW(__Vtemp964,127,0,4);
+    VL_SIGW(__Vtemp965,127,0,4);
+    VL_SIGW(__Vtemp966,127,0,4);
+    VL_SIGW(__Vtemp967,127,0,4);
+    VL_SIGW(__Vtemp968,127,0,4);
+    VL_SIGW(__Vtemp969,127,0,4);
+    VL_SIGW(__Vtemp970,127,0,4);
+    VL_SIGW(__Vtemp971,127,0,4);
+    VL_SIGW(__Vtemp972,127,0,4);
+    VL_SIGW(__Vtemp973,127,0,4);
+    VL_SIGW(__Vtemp974,127,0,4);
+    VL_SIGW(__Vtemp975,127,0,4);
+    VL_SIGW(__Vtemp976,127,0,4);
+    VL_SIGW(__Vtemp977,127,0,4);
+    VL_SIGW(__Vtemp978,127,0,4);
+    VL_SIGW(__Vtemp979,127,0,4);
+    VL_SIGW(__Vtemp980,127,0,4);
+    VL_SIGW(__Vtemp981,127,0,4);
+    VL_SIGW(__Vtemp982,127,0,4);
+    VL_SIGW(__Vtemp983,127,0,4);
+    VL_SIGW(__Vtemp984,127,0,4);
+    VL_SIGW(__Vtemp985,127,0,4);
+    VL_SIGW(__Vtemp986,127,0,4);
+    VL_SIGW(__Vtemp987,127,0,4);
+    VL_SIGW(__Vtemp988,127,0,4);
+    VL_SIGW(__Vtemp989,127,0,4);
+    VL_SIGW(__Vtemp990,127,0,4);
+    VL_SIGW(__Vtemp991,127,0,4);
+    VL_SIGW(__Vtemp992,127,0,4);
+    VL_SIGW(__Vtemp993,127,0,4);
+    VL_SIGW(__Vtemp994,127,0,4);
+    VL_SIGW(__Vtemp995,127,0,4);
+    VL_SIGW(__Vtemp996,127,0,4);
+    VL_SIGW(__Vtemp997,127,0,4);
+    VL_SIGW(__Vtemp998,127,0,4);
+    VL_SIGW(__Vtemp999,127,0,4);
+    VL_SIGW(__Vtemp1000,127,0,4);
+    VL_SIGW(__Vtemp1001,127,0,4);
+    VL_SIGW(__Vtemp1002,127,0,4);
+    VL_SIGW(__Vtemp1003,127,0,4);
+    VL_SIGW(__Vtemp1004,127,0,4);
+    VL_SIGW(__Vtemp1005,127,0,4);
+    VL_SIGW(__Vtemp1006,127,0,4);
+    VL_SIGW(__Vtemp1007,127,0,4);
+    VL_SIGW(__Vtemp1008,127,0,4);
+    VL_SIGW(__Vtemp1009,127,0,4);
+    VL_SIGW(__Vtemp1010,127,0,4);
+    VL_SIGW(__Vtemp1011,127,0,4);
+    VL_SIGW(__Vtemp1012,127,0,4);
+    VL_SIGW(__Vtemp1013,127,0,4);
+    VL_SIGW(__Vtemp1014,127,0,4);
+    VL_SIGW(__Vtemp1015,127,0,4);
+    VL_SIGW(__Vtemp1016,127,0,4);
+    VL_SIGW(__Vtemp1017,127,0,4);
+    VL_SIGW(__Vtemp1018,127,0,4);
+    VL_SIGW(__Vtemp1019,127,0,4);
+    VL_SIGW(__Vtemp1020,127,0,4);
+    VL_SIGW(__Vtemp1021,127,0,4);
+    VL_SIGW(__Vtemp1022,127,0,4);
+    VL_SIGW(__Vtemp1023,127,0,4);
+    VL_SIGW(__Vtemp1024,127,0,4);
+    VL_SIGW(__Vtemp1025,127,0,4);
+    VL_SIGW(__Vtemp1026,127,0,4);
+    VL_SIGW(__Vtemp1027,127,0,4);
+    VL_SIGW(__Vtemp1028,127,0,4);
+    VL_SIGW(__Vtemp1029,127,0,4);
+    VL_SIGW(__Vtemp1030,127,0,4);
+    VL_SIGW(__Vtemp1031,127,0,4);
+    VL_SIGW(__Vtemp1032,127,0,4);
+    VL_SIGW(__Vtemp1033,127,0,4);
+    VL_SIGW(__Vtemp1034,127,0,4);
+    VL_SIGW(__Vtemp1035,127,0,4);
+    VL_SIGW(__Vtemp1036,127,0,4);
+    VL_SIGW(__Vtemp1037,127,0,4);
+    VL_SIGW(__Vtemp1038,127,0,4);
+    VL_SIGW(__Vtemp1039,127,0,4);
+    VL_SIGW(__Vtemp1040,127,0,4);
+    VL_SIGW(__Vtemp1041,127,0,4);
+    VL_SIGW(__Vtemp1042,127,0,4);
+    VL_SIGW(__Vtemp1043,127,0,4);
+    VL_SIGW(__Vtemp1044,127,0,4);
+    VL_SIGW(__Vtemp1045,127,0,4);
+    VL_SIGW(__Vtemp1046,127,0,4);
+    VL_SIGW(__Vtemp1047,127,0,4);
+    VL_SIGW(__Vtemp1048,127,0,4);
+    VL_SIGW(__Vtemp1049,127,0,4);
+    VL_SIGW(__Vtemp1050,127,0,4);
+    VL_SIGW(__Vtemp1051,127,0,4);
+    VL_SIGW(__Vtemp1052,127,0,4);
+    VL_SIGW(__Vtemp1053,127,0,4);
+    VL_SIGW(__Vtemp1054,127,0,4);
+    VL_SIGW(__Vtemp1055,127,0,4);
+    VL_SIGW(__Vtemp1056,127,0,4);
+    VL_SIGW(__Vtemp1057,127,0,4);
+    VL_SIGW(__Vtemp1058,127,0,4);
+    VL_SIGW(__Vtemp1059,127,0,4);
+    VL_SIGW(__Vtemp1060,127,0,4);
+    VL_SIGW(__Vtemp1061,127,0,4);
+    VL_SIGW(__Vtemp1062,127,0,4);
+    VL_SIGW(__Vtemp1063,127,0,4);
+    VL_SIGW(__Vtemp1064,127,0,4);
+    VL_SIGW(__Vtemp1065,127,0,4);
+    VL_SIGW(__Vtemp1066,127,0,4);
+    VL_SIGW(__Vtemp1067,127,0,4);
+    VL_SIGW(__Vtemp1068,127,0,4);
+    VL_SIGW(__Vtemp1069,127,0,4);
+    VL_SIGW(__Vtemp1070,127,0,4);
+    VL_SIGW(__Vtemp1071,127,0,4);
+    VL_SIGW(__Vtemp1072,127,0,4);
+    VL_SIGW(__Vtemp1073,127,0,4);
+    VL_SIGW(__Vtemp1074,127,0,4);
+    VL_SIGW(__Vtemp1075,127,0,4);
+    VL_SIGW(__Vtemp1076,127,0,4);
+    VL_SIGW(__Vtemp1077,127,0,4);
+    VL_SIGW(__Vtemp1078,127,0,4);
+    VL_SIGW(__Vtemp1079,127,0,4);
+    VL_SIGW(__Vtemp1080,127,0,4);
+    VL_SIGW(__Vtemp1081,127,0,4);
+    VL_SIGW(__Vtemp1082,127,0,4);
+    VL_SIGW(__Vtemp1083,127,0,4);
+    VL_SIGW(__Vtemp1084,127,0,4);
+    VL_SIGW(__Vtemp1085,127,0,4);
+    VL_SIGW(__Vtemp1086,127,0,4);
+    VL_SIGW(__Vtemp1087,127,0,4);
+    VL_SIGW(__Vtemp1088,127,0,4);
+    VL_SIGW(__Vtemp1089,127,0,4);
+    VL_SIGW(__Vtemp1090,127,0,4);
+    VL_SIGW(__Vtemp1091,127,0,4);
+    VL_SIGW(__Vtemp1092,127,0,4);
+    VL_SIGW(__Vtemp1093,127,0,4);
+    VL_SIGW(__Vtemp1094,127,0,4);
+    VL_SIGW(__Vtemp1095,127,0,4);
+    VL_SIGW(__Vtemp1096,127,0,4);
+    VL_SIGW(__Vtemp1097,127,0,4);
+    VL_SIGW(__Vtemp1098,127,0,4);
+    VL_SIGW(__Vtemp1099,127,0,4);
+    VL_SIGW(__Vtemp1100,127,0,4);
+    VL_SIGW(__Vtemp1101,127,0,4);
+    VL_SIGW(__Vtemp1102,127,0,4);
+    VL_SIGW(__Vtemp1103,127,0,4);
+    VL_SIGW(__Vtemp1104,127,0,4);
+    VL_SIGW(__Vtemp1105,127,0,4);
+    VL_SIGW(__Vtemp1106,127,0,4);
+    VL_SIGW(__Vtemp1107,127,0,4);
+    VL_SIGW(__Vtemp1108,127,0,4);
+    VL_SIGW(__Vtemp1109,127,0,4);
+    VL_SIGW(__Vtemp1110,127,0,4);
+    VL_SIGW(__Vtemp1111,127,0,4);
+    VL_SIGW(__Vtemp1112,127,0,4);
+    VL_SIGW(__Vtemp1113,127,0,4);
+    VL_SIGW(__Vtemp1114,127,0,4);
+    VL_SIGW(__Vtemp1115,127,0,4);
+    VL_SIGW(__Vtemp1116,127,0,4);
+    VL_SIGW(__Vtemp1117,127,0,4);
+    VL_SIGW(__Vtemp1118,127,0,4);
+    VL_SIGW(__Vtemp1119,127,0,4);
+    VL_SIGW(__Vtemp1120,127,0,4);
+    VL_SIGW(__Vtemp1121,127,0,4);
+    VL_SIGW(__Vtemp1122,127,0,4);
+    VL_SIGW(__Vtemp1123,127,0,4);
+    VL_SIGW(__Vtemp1124,127,0,4);
+    VL_SIGW(__Vtemp1125,127,0,4);
+    VL_SIGW(__Vtemp1126,127,0,4);
+    VL_SIGW(__Vtemp1127,127,0,4);
+    VL_SIGW(__Vtemp1128,127,0,4);
+    VL_SIGW(__Vtemp1129,127,0,4);
+    VL_SIGW(__Vtemp1130,127,0,4);
+    VL_SIGW(__Vtemp1131,127,0,4);
+    VL_SIGW(__Vtemp1132,127,0,4);
+    VL_SIGW(__Vtemp1133,127,0,4);
+    VL_SIGW(__Vtemp1134,127,0,4);
+    VL_SIGW(__Vtemp1135,127,0,4);
+    VL_SIGW(__Vtemp1136,127,0,4);
+    VL_SIGW(__Vtemp1137,127,0,4);
+    VL_SIGW(__Vtemp1138,127,0,4);
+    VL_SIGW(__Vtemp1139,127,0,4);
+    VL_SIGW(__Vtemp1140,127,0,4);
+    VL_SIGW(__Vtemp1141,127,0,4);
+    VL_SIGW(__Vtemp1142,127,0,4);
+    VL_SIGW(__Vtemp1143,127,0,4);
+    VL_SIGW(__Vtemp1144,127,0,4);
+    VL_SIGW(__Vtemp1145,127,0,4);
+    VL_SIGW(__Vtemp1146,127,0,4);
+    VL_SIGW(__Vtemp1147,127,0,4);
+    VL_SIGW(__Vtemp1148,127,0,4);
+    VL_SIGW(__Vtemp1149,127,0,4);
+    VL_SIGW(__Vtemp1150,127,0,4);
+    VL_SIGW(__Vtemp1151,127,0,4);
+    VL_SIGW(__Vtemp1152,127,0,4);
+    VL_SIGW(__Vtemp1153,127,0,4);
+    VL_SIGW(__Vtemp1154,127,0,4);
+    VL_SIGW(__Vtemp1155,127,0,4);
+    VL_SIGW(__Vtemp1156,127,0,4);
+    VL_SIGW(__Vtemp1157,127,0,4);
+    VL_SIGW(__Vtemp1158,127,0,4);
+    VL_SIGW(__Vtemp1159,127,0,4);
+    VL_SIGW(__Vtemp1160,127,0,4);
+    VL_SIGW(__Vtemp1161,127,0,4);
+    VL_SIGW(__Vtemp1162,127,0,4);
+    VL_SIGW(__Vtemp1163,127,0,4);
+    VL_SIGW(__Vtemp1164,127,0,4);
+    VL_SIGW(__Vtemp1165,127,0,4);
+    VL_SIGW(__Vtemp1166,127,0,4);
+    VL_SIGW(__Vtemp1167,127,0,4);
+    VL_SIGW(__Vtemp1168,127,0,4);
+    VL_SIGW(__Vtemp1169,127,0,4);
+    VL_SIGW(__Vtemp1170,127,0,4);
+    VL_SIGW(__Vtemp1171,127,0,4);
+    VL_SIGW(__Vtemp1172,127,0,4);
+    VL_SIGW(__Vtemp1173,127,0,4);
+    VL_SIGW(__Vtemp1174,127,0,4);
+    VL_SIGW(__Vtemp1175,127,0,4);
+    VL_SIGW(__Vtemp1176,127,0,4);
+    VL_SIGW(__Vtemp1177,127,0,4);
+    VL_SIGW(__Vtemp1178,127,0,4);
+    VL_SIGW(__Vtemp1179,127,0,4);
+    VL_SIGW(__Vtemp1180,127,0,4);
+    VL_SIGW(__Vtemp1181,127,0,4);
+    VL_SIGW(__Vtemp1182,127,0,4);
+    VL_SIGW(__Vtemp1183,127,0,4);
+    VL_SIGW(__Vtemp1184,127,0,4);
+    VL_SIGW(__Vtemp1185,127,0,4);
+    VL_SIGW(__Vtemp1186,127,0,4);
+    VL_SIGW(__Vtemp1187,127,0,4);
+    VL_SIGW(__Vtemp1188,127,0,4);
+    VL_SIGW(__Vtemp1189,127,0,4);
+    VL_SIGW(__Vtemp1190,127,0,4);
+    VL_SIGW(__Vtemp1191,127,0,4);
+    VL_SIGW(__Vtemp1192,127,0,4);
+    VL_SIGW(__Vtemp1193,127,0,4);
+    VL_SIGW(__Vtemp1194,127,0,4);
+    VL_SIGW(__Vtemp1195,127,0,4);
+    VL_SIGW(__Vtemp1196,127,0,4);
+    VL_SIGW(__Vtemp1197,127,0,4);
+    VL_SIGW(__Vtemp1198,127,0,4);
+    VL_SIGW(__Vtemp1199,127,0,4);
+    VL_SIGW(__Vtemp1200,127,0,4);
+    VL_SIGW(__Vtemp1201,127,0,4);
+    VL_SIGW(__Vtemp1202,127,0,4);
+    VL_SIGW(__Vtemp1203,127,0,4);
+    VL_SIGW(__Vtemp1204,127,0,4);
+    VL_SIGW(__Vtemp1205,127,0,4);
+    VL_SIGW(__Vtemp1206,127,0,4);
+    VL_SIGW(__Vtemp1207,127,0,4);
+    VL_SIGW(__Vtemp1208,127,0,4);
+    VL_SIGW(__Vtemp1209,127,0,4);
+    VL_SIGW(__Vtemp1210,127,0,4);
+    VL_SIGW(__Vtemp1211,127,0,4);
+    VL_SIGW(__Vtemp1212,127,0,4);
+    VL_SIGW(__Vtemp1213,127,0,4);
+    VL_SIGW(__Vtemp1214,127,0,4);
+    VL_SIGW(__Vtemp1215,127,0,4);
+    VL_SIGW(__Vtemp1216,127,0,4);
+    VL_SIGW(__Vtemp1217,127,0,4);
+    VL_SIGW(__Vtemp1218,127,0,4);
+    VL_SIGW(__Vtemp1219,127,0,4);
+    VL_SIGW(__Vtemp1220,127,0,4);
+    VL_SIGW(__Vtemp1221,127,0,4);
+    VL_SIGW(__Vtemp1222,127,0,4);
+    VL_SIGW(__Vtemp1223,127,0,4);
+    VL_SIGW(__Vtemp1224,127,0,4);
+    VL_SIGW(__Vtemp1225,127,0,4);
+    VL_SIGW(__Vtemp1226,127,0,4);
+    VL_SIGW(__Vtemp1227,127,0,4);
+    VL_SIGW(__Vtemp1228,127,0,4);
+    VL_SIGW(__Vtemp1229,127,0,4);
+    VL_SIGW(__Vtemp1230,127,0,4);
+    VL_SIGW(__Vtemp1231,127,0,4);
+    VL_SIGW(__Vtemp1232,127,0,4);
+    VL_SIGW(__Vtemp1233,127,0,4);
+    VL_SIGW(__Vtemp1234,127,0,4);
+    VL_SIGW(__Vtemp1235,127,0,4);
+    VL_SIGW(__Vtemp1236,127,0,4);
+    VL_SIGW(__Vtemp1237,127,0,4);
+    VL_SIGW(__Vtemp1238,127,0,4);
+    VL_SIGW(__Vtemp1239,127,0,4);
+    VL_SIGW(__Vtemp1240,127,0,4);
+    VL_SIGW(__Vtemp1241,127,0,4);
+    VL_SIGW(__Vtemp1242,127,0,4);
+    VL_SIGW(__Vtemp1243,127,0,4);
+    VL_SIGW(__Vtemp1244,127,0,4);
+    VL_SIGW(__Vtemp1245,127,0,4);
+    VL_SIGW(__Vtemp1246,127,0,4);
+    VL_SIGW(__Vtemp1247,127,0,4);
+    VL_SIGW(__Vtemp1248,127,0,4);
+    VL_SIGW(__Vtemp1249,127,0,4);
+    VL_SIGW(__Vtemp1250,127,0,4);
+    VL_SIGW(__Vtemp1251,127,0,4);
+    VL_SIGW(__Vtemp1252,127,0,4);
+    VL_SIGW(__Vtemp1253,127,0,4);
+    VL_SIGW(__Vtemp1254,127,0,4);
+    VL_SIGW(__Vtemp1255,127,0,4);
+    VL_SIGW(__Vtemp1256,127,0,4);
+    VL_SIGW(__Vtemp1257,127,0,4);
+    VL_SIGW(__Vtemp1258,127,0,4);
+    VL_SIGW(__Vtemp1259,127,0,4);
+    VL_SIGW(__Vtemp1260,127,0,4);
+    VL_SIGW(__Vtemp1261,127,0,4);
+    VL_SIGW(__Vtemp1262,127,0,4);
+    VL_SIGW(__Vtemp1263,127,0,4);
+    VL_SIGW(__Vtemp1264,127,0,4);
+    VL_SIGW(__Vtemp1265,127,0,4);
+    VL_SIGW(__Vtemp1266,127,0,4);
+    VL_SIGW(__Vtemp1267,127,0,4);
+    VL_SIGW(__Vtemp1268,127,0,4);
+    VL_SIGW(__Vtemp1269,127,0,4);
+    VL_SIGW(__Vtemp1270,127,0,4);
+    VL_SIGW(__Vtemp1271,127,0,4);
+    VL_SIGW(__Vtemp1272,127,0,4);
+    VL_SIGW(__Vtemp1273,127,0,4);
+    VL_SIGW(__Vtemp1274,127,0,4);
+    VL_SIGW(__Vtemp1275,127,0,4);
+    VL_SIGW(__Vtemp1276,127,0,4);
+    VL_SIGW(__Vtemp1277,127,0,4);
+    VL_SIGW(__Vtemp1278,127,0,4);
+    VL_SIGW(__Vtemp1279,127,0,4);
     // Body
     {
-	vcdp->chgBit  (c+708,(vlTOPp->cache_simX__DOT__icache_i_m_ready));
-	vcdp->chgBit  (c+709,(vlTOPp->cache_simX__DOT__dcache_i_m_ready));
-	vcdp->chgBus  (c+710,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests),4);
-	vcdp->chgBit  (c+711,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))));
-	vcdp->chgBus  (c+712,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
-	vcdp->chgBus  (c+713,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
-	vcdp->chgBus  (c+714,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
-	vcdp->chgBus  (c+715,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
-	vcdp->chgBus  (c+716,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr)),32);
-	vcdp->chgBit  (c+717,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))));
-	vcdp->chgArray(c+718,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read),128);
-	vcdp->chgBus  (c+722,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict),1);
-	vcdp->chgBus  (c+723,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state),4);
-	vcdp->chgBus  (c+724,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid),4);
-	vcdp->chgBus  (c+725,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr),32);
-	vcdp->chgBus  (c+726,((0xfffffff0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr)),32);
-	vcdp->chgBit  (c+727,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))));
-	vcdp->chgBus  (c+728,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read),32);
-	vcdp->chgBus  (c+729,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict),1);
-	vcdp->chgBus  (c+730,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state),4);
-	vcdp->chgBus  (c+731,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid),1);
-	vcdp->chgBus  (c+732,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr),32);
-	vcdp->chgBus  (c+733,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			      [0U]),23);
-	__Vtemp605[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	vcdp->chgBit  (c+1163,(vlTOPp->cache_simX__DOT__icache_i_m_ready));
+	vcdp->chgBit  (c+1164,(vlTOPp->cache_simX__DOT__dcache_i_m_ready));
+	vcdp->chgBus  (c+1165,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests),4);
+	vcdp->chgBit  (c+1166,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))));
+	vcdp->chgBus  (c+1167,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
+	vcdp->chgBus  (c+1168,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
+	vcdp->chgBus  (c+1169,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
+	vcdp->chgBus  (c+1170,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
+	vcdp->chgBus  (c+1171,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr)),32);
+	vcdp->chgBit  (c+1172,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))));
+	vcdp->chgArray(c+1173,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read),128);
+	vcdp->chgBus  (c+1177,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict),1);
+	vcdp->chgBus  (c+1178,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state),4);
+	vcdp->chgBus  (c+1179,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid),4);
+	vcdp->chgBus  (c+1180,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr),32);
+	vcdp->chgBus  (c+1181,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr)),32);
+	vcdp->chgBit  (c+1182,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))));
+	vcdp->chgBus  (c+1183,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read),32);
+	vcdp->chgBus  (c+1184,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict),1);
+	vcdp->chgBus  (c+1185,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state),4);
+	vcdp->chgBus  (c+1186,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid),1);
+	vcdp->chgBus  (c+1187,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr),32);
+	__Vtemp768[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [0U][0U];
-	__Vtemp605[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	__Vtemp768[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [0U][1U];
-	__Vtemp605[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	__Vtemp768[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [0U][2U];
-	__Vtemp605[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	__Vtemp768[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [0U][3U];
-	vcdp->chgArray(c+734,(__Vtemp605),128);
-	vcdp->chgBit  (c+738,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-			      [0U]));
-	vcdp->chgBit  (c+739,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-			      [0U]));
-	__Vtemp606[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	    [0U][0U];
-	__Vtemp606[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	    [0U][1U];
-	__Vtemp606[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	    [0U][2U];
-	__Vtemp606[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	    [0U][3U];
-	vcdp->chgArray(c+740,(__Vtemp606),128);
-	__Vtemp607[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	vcdp->chgArray(c+1188,(__Vtemp768),128);
+	__Vtemp769[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [1U][0U];
-	__Vtemp607[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	__Vtemp769[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [1U][1U];
-	__Vtemp607[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	__Vtemp769[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
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+	vcdp->chgBit  (c+2725,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[21]));
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+	vcdp->chgBit  (c+2727,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[23]));
+	vcdp->chgBit  (c+2728,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[24]));
+	vcdp->chgBit  (c+2729,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[25]));
+	vcdp->chgBit  (c+2730,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[26]));
+	vcdp->chgBit  (c+2731,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[27]));
+	vcdp->chgBit  (c+2732,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[28]));
+	vcdp->chgBit  (c+2733,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[29]));
+	vcdp->chgBit  (c+2734,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[30]));
+	vcdp->chgBit  (c+2735,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[31]));
+	vcdp->chgBit  (c+2736,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0]));
+	vcdp->chgBit  (c+2737,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[1]));
+	vcdp->chgBit  (c+2738,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[2]));
+	vcdp->chgBit  (c+2739,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[3]));
+	vcdp->chgBit  (c+2740,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[4]));
+	vcdp->chgBit  (c+2741,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[5]));
+	vcdp->chgBit  (c+2742,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[6]));
+	vcdp->chgBit  (c+2743,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[7]));
+	vcdp->chgBit  (c+2744,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[8]));
+	vcdp->chgBit  (c+2745,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[9]));
+	vcdp->chgBit  (c+2746,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[10]));
+	vcdp->chgBit  (c+2747,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[11]));
+	vcdp->chgBit  (c+2748,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[12]));
+	vcdp->chgBit  (c+2749,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[13]));
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+	vcdp->chgBit  (c+2754,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[18]));
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+	vcdp->chgBit  (c+2758,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[22]));
+	vcdp->chgBit  (c+2759,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[23]));
+	vcdp->chgBit  (c+2760,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[24]));
+	vcdp->chgBit  (c+2761,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[25]));
+	vcdp->chgBit  (c+2762,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[26]));
+	vcdp->chgBit  (c+2763,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[27]));
+	vcdp->chgBit  (c+2764,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[28]));
+	vcdp->chgBit  (c+2765,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[29]));
+	vcdp->chgBit  (c+2766,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[30]));
+	vcdp->chgBit  (c+2767,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[31]));
+	vcdp->chgBus  (c+2768,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f),32);
+	vcdp->chgBus  (c+2769,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind),32);
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 	    [0U][1U];
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+	__Vtemp992[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
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+	__Vtemp992[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
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+	vcdp->chgBit  (c+3444,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[30]));
+	vcdp->chgBit  (c+3445,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[31]));
+	vcdp->chgBus  (c+3446,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f),32);
+	vcdp->chgBus  (c+3447,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind),32);
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+	    [0U][0U];
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+	    [0xeU][3U];
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+	vcdp->chgArray(c+3508,(__Vtemp1103),128);
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+	    [0x10U][1U];
+	__Vtemp1104[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x10U][2U];
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+	    [0x10U][3U];
+	vcdp->chgArray(c+3512,(__Vtemp1104),128);
+	__Vtemp1105[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x11U][0U];
+	__Vtemp1105[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x11U][1U];
+	__Vtemp1105[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x11U][2U];
+	__Vtemp1105[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x11U][3U];
+	vcdp->chgArray(c+3516,(__Vtemp1105),128);
+	__Vtemp1106[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x12U][0U];
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+	    [0x12U][1U];
+	__Vtemp1106[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x12U][2U];
+	__Vtemp1106[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x12U][3U];
+	vcdp->chgArray(c+3520,(__Vtemp1106),128);
+	__Vtemp1107[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
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+	    [0x13U][1U];
+	__Vtemp1107[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x13U][2U];
+	__Vtemp1107[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x13U][3U];
+	vcdp->chgArray(c+3524,(__Vtemp1107),128);
+	__Vtemp1108[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x14U][0U];
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+	    [0x14U][1U];
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+	    [0x14U][2U];
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+	    [0x14U][3U];
+	vcdp->chgArray(c+3528,(__Vtemp1108),128);
+	__Vtemp1109[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
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+	    [0x15U][1U];
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+	    [0x15U][2U];
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+	    [0x15U][3U];
+	vcdp->chgArray(c+3532,(__Vtemp1109),128);
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+	    [0x16U][1U];
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+	    [0x16U][2U];
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+	vcdp->chgArray(c+3536,(__Vtemp1110),128);
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+	    [0x17U][0U];
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+	    [0x17U][1U];
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+	    [0x17U][2U];
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+	    [0x17U][3U];
+	vcdp->chgArray(c+3540,(__Vtemp1111),128);
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+	    [0x18U][2U];
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+	    [0x18U][3U];
+	vcdp->chgArray(c+3544,(__Vtemp1112),128);
+	__Vtemp1113[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
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+	    [0x19U][1U];
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+	    [0x19U][2U];
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+	    [0x19U][3U];
+	vcdp->chgArray(c+3548,(__Vtemp1113),128);
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+	    [0x1aU][1U];
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+	    [0x1aU][2U];
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+	    [0x1aU][3U];
+	vcdp->chgArray(c+3552,(__Vtemp1114),128);
+	__Vtemp1115[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x1bU][0U];
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+	    [0x1bU][1U];
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+	    [0x1bU][2U];
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+	    [0x1bU][3U];
+	vcdp->chgArray(c+3556,(__Vtemp1115),128);
+	__Vtemp1116[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x1cU][0U];
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+	    [0x1cU][1U];
+	__Vtemp1116[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x1cU][2U];
+	__Vtemp1116[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x1cU][3U];
+	vcdp->chgArray(c+3560,(__Vtemp1116),128);
+	__Vtemp1117[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x1dU][0U];
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+	    [0x1dU][1U];
+	__Vtemp1117[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x1dU][2U];
+	__Vtemp1117[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x1dU][3U];
+	vcdp->chgArray(c+3564,(__Vtemp1117),128);
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+	    [0x1eU][0U];
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+	    [0x1eU][1U];
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+	    [0x1eU][2U];
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+	    [0x1eU][3U];
+	vcdp->chgArray(c+3568,(__Vtemp1118),128);
+	__Vtemp1119[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x1fU][0U];
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+	    [0x1fU][1U];
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+	    [0x1fU][2U];
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+	    [0x1fU][3U];
+	vcdp->chgArray(c+3572,(__Vtemp1119),128);
+	vcdp->chgBus  (c+3576,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0]),21);
+	vcdp->chgBus  (c+3577,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[1]),21);
+	vcdp->chgBus  (c+3578,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[2]),21);
+	vcdp->chgBus  (c+3579,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[3]),21);
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+	vcdp->chgBit  (c+3659,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[19]));
+	vcdp->chgBit  (c+3660,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[20]));
+	vcdp->chgBit  (c+3661,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[21]));
+	vcdp->chgBit  (c+3662,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[22]));
+	vcdp->chgBit  (c+3663,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[23]));
+	vcdp->chgBit  (c+3664,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[24]));
+	vcdp->chgBit  (c+3665,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[25]));
+	vcdp->chgBit  (c+3666,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[26]));
+	vcdp->chgBit  (c+3667,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[27]));
+	vcdp->chgBit  (c+3668,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[28]));
+	vcdp->chgBit  (c+3669,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[29]));
+	vcdp->chgBit  (c+3670,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[30]));
+	vcdp->chgBit  (c+3671,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[31]));
+	vcdp->chgBus  (c+3672,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f),32);
+	vcdp->chgBus  (c+3673,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind),32);
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+	    [0U][0U];
+	__Vtemp1120[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0U][1U];
+	__Vtemp1120[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0U][2U];
+	__Vtemp1120[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0U][3U];
+	vcdp->chgArray(c+3674,(__Vtemp1120),128);
+	__Vtemp1121[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [1U][0U];
+	__Vtemp1121[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [1U][1U];
+	__Vtemp1121[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [1U][2U];
+	__Vtemp1121[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [1U][3U];
+	vcdp->chgArray(c+3678,(__Vtemp1121),128);
+	__Vtemp1122[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [2U][0U];
+	__Vtemp1122[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [2U][1U];
+	__Vtemp1122[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [2U][2U];
+	__Vtemp1122[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [2U][3U];
+	vcdp->chgArray(c+3682,(__Vtemp1122),128);
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+	    [3U][0U];
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+	    [3U][1U];
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+	    [3U][2U];
+	__Vtemp1123[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [3U][3U];
+	vcdp->chgArray(c+3686,(__Vtemp1123),128);
+	__Vtemp1124[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [4U][0U];
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+	    [4U][1U];
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+	    [4U][2U];
+	__Vtemp1124[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [4U][3U];
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+	    [5U][0U];
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+	    [5U][1U];
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+	    [5U][2U];
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+	    [5U][3U];
+	vcdp->chgArray(c+3694,(__Vtemp1125),128);
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+	    [6U][0U];
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+	    [6U][1U];
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+	    [6U][2U];
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+	    [6U][3U];
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+	    [7U][1U];
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+	    [7U][2U];
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+	    [7U][3U];
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+	    [8U][0U];
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+	    [8U][1U];
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+	    [8U][2U];
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+	    [8U][3U];
+	vcdp->chgArray(c+3706,(__Vtemp1128),128);
+	__Vtemp1129[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [9U][0U];
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+	    [9U][1U];
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+	    [9U][2U];
+	__Vtemp1129[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [9U][3U];
+	vcdp->chgArray(c+3710,(__Vtemp1129),128);
+	__Vtemp1130[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xaU][0U];
+	__Vtemp1130[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xaU][1U];
+	__Vtemp1130[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xaU][2U];
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+	    [0xaU][3U];
+	vcdp->chgArray(c+3714,(__Vtemp1130),128);
+	__Vtemp1131[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xbU][0U];
+	__Vtemp1131[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xbU][1U];
+	__Vtemp1131[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xbU][2U];
+	__Vtemp1131[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xbU][3U];
+	vcdp->chgArray(c+3718,(__Vtemp1131),128);
+	__Vtemp1132[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xcU][0U];
+	__Vtemp1132[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xcU][1U];
+	__Vtemp1132[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xcU][2U];
+	__Vtemp1132[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xcU][3U];
+	vcdp->chgArray(c+3722,(__Vtemp1132),128);
+	__Vtemp1133[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xdU][0U];
+	__Vtemp1133[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xdU][1U];
+	__Vtemp1133[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xdU][2U];
+	__Vtemp1133[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xdU][3U];
+	vcdp->chgArray(c+3726,(__Vtemp1133),128);
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+	vcdp->chgArray(c+3758,(__Vtemp1141),128);
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+	vcdp->chgArray(c+3770,(__Vtemp1144),128);
+	__Vtemp1145[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
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+	    [0x19U][3U];
+	vcdp->chgArray(c+3774,(__Vtemp1145),128);
+	__Vtemp1146[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
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+	    [0x1aU][3U];
+	vcdp->chgArray(c+3778,(__Vtemp1146),128);
+	__Vtemp1147[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
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+	    [0x1bU][3U];
+	vcdp->chgArray(c+3782,(__Vtemp1147),128);
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+	    [0x1cU][3U];
+	vcdp->chgArray(c+3786,(__Vtemp1148),128);
+	__Vtemp1149[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
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+	    [0x1dU][3U];
+	vcdp->chgArray(c+3790,(__Vtemp1149),128);
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+	    [0x1eU][3U];
+	vcdp->chgArray(c+3794,(__Vtemp1150),128);
+	__Vtemp1151[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
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+	vcdp->chgBit  (c+3891,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[25]));
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+	vcdp->chgBit  (c+3896,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[30]));
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+	vcdp->chgBus  (c+3898,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f),32);
+	vcdp->chgBus  (c+3899,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind),32);
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+	    [0U][0U];
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+	    [0U][1U];
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+	    [0U][2U];
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+	    [0U][3U];
+	vcdp->chgArray(c+3900,(__Vtemp1152),128);
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+	    [1U][0U];
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+	    [1U][1U];
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+	    [1U][2U];
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+	    [1U][3U];
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+	    [2U][1U];
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+	    [2U][2U];
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+	    [2U][3U];
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+	    [3U][0U];
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+	    [8U][3U];
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+	    [9U][3U];
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+	    [0xaU][3U];
+	vcdp->chgArray(c+3940,(__Vtemp1162),128);
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+	    [0xbU][0U];
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+	    [0xbU][1U];
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+	    [0xbU][3U];
+	vcdp->chgArray(c+3944,(__Vtemp1163),128);
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+	    [0xcU][0U];
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+	vcdp->chgBit  (c+4117,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[25]));
+	vcdp->chgBit  (c+4118,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[26]));
+	vcdp->chgBit  (c+4119,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[27]));
+	vcdp->chgBit  (c+4120,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[28]));
+	vcdp->chgBit  (c+4121,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[29]));
+	vcdp->chgBit  (c+4122,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[30]));
+	vcdp->chgBit  (c+4123,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[31]));
+	vcdp->chgBus  (c+4124,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f),32);
+	vcdp->chgBus  (c+4125,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind),32);
+	__Vtemp1184[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0U][0U];
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+	    [0U][1U];
+	__Vtemp1184[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0U][2U];
+	__Vtemp1184[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0U][3U];
+	vcdp->chgArray(c+4126,(__Vtemp1184),128);
+	__Vtemp1185[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [1U][0U];
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+	    [1U][1U];
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+	    [1U][2U];
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+	    [1U][3U];
+	vcdp->chgArray(c+4130,(__Vtemp1185),128);
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+	    [2U][0U];
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+	    [2U][1U];
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+	    [2U][2U];
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+	    [2U][3U];
+	vcdp->chgArray(c+4134,(__Vtemp1186),128);
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+	    [3U][0U];
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+	    [3U][1U];
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+	    [3U][2U];
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+	    [3U][3U];
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+	    [4U][0U];
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+	    [4U][1U];
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+	    [4U][2U];
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+	    [4U][3U];
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+	    [5U][0U];
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+	    [5U][1U];
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+	    [5U][2U];
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+	    [5U][3U];
+	vcdp->chgArray(c+4146,(__Vtemp1189),128);
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+	    [6U][0U];
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+	    [6U][1U];
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+	    [6U][2U];
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+	    [6U][3U];
+	vcdp->chgArray(c+4150,(__Vtemp1190),128);
+	__Vtemp1191[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [7U][0U];
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+	    [7U][1U];
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+	    [7U][2U];
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+	    [7U][3U];
+	vcdp->chgArray(c+4154,(__Vtemp1191),128);
+	__Vtemp1192[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [8U][0U];
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+	    [8U][1U];
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+	    [8U][2U];
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+	    [8U][3U];
+	vcdp->chgArray(c+4158,(__Vtemp1192),128);
+	__Vtemp1193[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [9U][0U];
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+	    [9U][1U];
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+	    [9U][2U];
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+	    [9U][3U];
+	vcdp->chgArray(c+4162,(__Vtemp1193),128);
+	__Vtemp1194[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xaU][0U];
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+	    [0xaU][1U];
+	__Vtemp1194[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xaU][2U];
+	__Vtemp1194[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xaU][3U];
+	vcdp->chgArray(c+4166,(__Vtemp1194),128);
+	__Vtemp1195[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xbU][0U];
+	__Vtemp1195[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xbU][1U];
+	__Vtemp1195[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xbU][2U];
+	__Vtemp1195[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xbU][3U];
+	vcdp->chgArray(c+4170,(__Vtemp1195),128);
+	__Vtemp1196[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xcU][0U];
+	__Vtemp1196[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xcU][1U];
+	__Vtemp1196[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xcU][2U];
+	__Vtemp1196[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xcU][3U];
+	vcdp->chgArray(c+4174,(__Vtemp1196),128);
+	__Vtemp1197[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xdU][0U];
+	__Vtemp1197[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xdU][1U];
+	__Vtemp1197[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xdU][2U];
+	__Vtemp1197[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xdU][3U];
+	vcdp->chgArray(c+4178,(__Vtemp1197),128);
+	__Vtemp1198[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xeU][0U];
+	__Vtemp1198[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xeU][1U];
+	__Vtemp1198[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xeU][2U];
+	__Vtemp1198[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xeU][3U];
+	vcdp->chgArray(c+4182,(__Vtemp1198),128);
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+	    [0xfU][0U];
+	__Vtemp1199[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xfU][1U];
+	__Vtemp1199[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xfU][2U];
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+	    [0xfU][3U];
+	vcdp->chgArray(c+4186,(__Vtemp1199),128);
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+	    [0x10U][0U];
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+	    [0x10U][1U];
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+	    [0x10U][2U];
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+	    [0x10U][3U];
+	vcdp->chgArray(c+4190,(__Vtemp1200),128);
+	__Vtemp1201[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x11U][0U];
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+	    [0x11U][1U];
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+	    [0x11U][2U];
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+	    [0x11U][3U];
+	vcdp->chgArray(c+4194,(__Vtemp1201),128);
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+	    [0x12U][0U];
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+	    [0x12U][1U];
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+	    [0x12U][3U];
+	vcdp->chgArray(c+4198,(__Vtemp1202),128);
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+	    [0x13U][1U];
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+	    [0x13U][3U];
+	vcdp->chgArray(c+4202,(__Vtemp1203),128);
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+	    [0x14U][2U];
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+	    [0x14U][3U];
+	vcdp->chgArray(c+4206,(__Vtemp1204),128);
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+	    [0x15U][0U];
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+	    [0x15U][1U];
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+	    [0x15U][2U];
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+	    [0x15U][3U];
+	vcdp->chgArray(c+4210,(__Vtemp1205),128);
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+	    [0x16U][0U];
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+	    [0x16U][1U];
+	__Vtemp1206[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x16U][2U];
+	__Vtemp1206[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x16U][3U];
+	vcdp->chgArray(c+4214,(__Vtemp1206),128);
+	__Vtemp1207[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x17U][0U];
+	__Vtemp1207[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x17U][1U];
+	__Vtemp1207[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x17U][2U];
+	__Vtemp1207[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x17U][3U];
+	vcdp->chgArray(c+4218,(__Vtemp1207),128);
+	__Vtemp1208[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x18U][0U];
+	__Vtemp1208[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x18U][1U];
+	__Vtemp1208[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x18U][2U];
+	__Vtemp1208[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x18U][3U];
+	vcdp->chgArray(c+4222,(__Vtemp1208),128);
+	__Vtemp1209[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x19U][0U];
+	__Vtemp1209[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x19U][1U];
+	__Vtemp1209[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x19U][2U];
+	__Vtemp1209[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x19U][3U];
+	vcdp->chgArray(c+4226,(__Vtemp1209),128);
+	__Vtemp1210[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x1aU][0U];
+	__Vtemp1210[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x1aU][1U];
+	__Vtemp1210[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x1aU][2U];
+	__Vtemp1210[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x1aU][3U];
+	vcdp->chgArray(c+4230,(__Vtemp1210),128);
+	__Vtemp1211[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x1bU][0U];
+	__Vtemp1211[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x1bU][1U];
+	__Vtemp1211[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x1bU][2U];
+	__Vtemp1211[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
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+	vcdp->chgBit  (c+4329,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[11]));
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+	vcdp->chgBit  (c+4331,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[13]));
+	vcdp->chgBit  (c+4332,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[14]));
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+	vcdp->chgBit  (c+4337,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[19]));
+	vcdp->chgBit  (c+4338,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[20]));
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+	vcdp->chgBit  (c+4340,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[22]));
+	vcdp->chgBit  (c+4341,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[23]));
+	vcdp->chgBit  (c+4342,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[24]));
+	vcdp->chgBit  (c+4343,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[25]));
+	vcdp->chgBit  (c+4344,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[26]));
+	vcdp->chgBit  (c+4345,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[27]));
+	vcdp->chgBit  (c+4346,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[28]));
+	vcdp->chgBit  (c+4347,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[29]));
+	vcdp->chgBit  (c+4348,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[30]));
+	vcdp->chgBit  (c+4349,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[31]));
+	vcdp->chgBus  (c+4350,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f),32);
+	vcdp->chgBus  (c+4351,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind),32);
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+	    [0U][0U];
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+	    [0U][1U];
+	__Vtemp1216[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0U][2U];
+	__Vtemp1216[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0U][3U];
+	vcdp->chgArray(c+4352,(__Vtemp1216),128);
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+	    [1U][0U];
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+	    [1U][1U];
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+	    [1U][2U];
+	__Vtemp1217[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [1U][3U];
+	vcdp->chgArray(c+4356,(__Vtemp1217),128);
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+	    [2U][0U];
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+	    [2U][1U];
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+	    [2U][2U];
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+	    [2U][3U];
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+	    [3U][0U];
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+	    [3U][2U];
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+	    [3U][3U];
+	vcdp->chgArray(c+4364,(__Vtemp1219),128);
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+	    [4U][0U];
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+	    [4U][1U];
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+	    [4U][2U];
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+	    [4U][3U];
+	vcdp->chgArray(c+4368,(__Vtemp1220),128);
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+	    [5U][0U];
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+	    [5U][1U];
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+	    [5U][2U];
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+	    [5U][3U];
+	vcdp->chgArray(c+4372,(__Vtemp1221),128);
+	__Vtemp1222[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [6U][0U];
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+	    [6U][1U];
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+	    [6U][2U];
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+	    [6U][3U];
+	vcdp->chgArray(c+4376,(__Vtemp1222),128);
+	__Vtemp1223[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [7U][0U];
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+	    [7U][1U];
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+	    [7U][2U];
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+	    [7U][3U];
+	vcdp->chgArray(c+4380,(__Vtemp1223),128);
+	__Vtemp1224[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [8U][0U];
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+	    [8U][1U];
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+	    [8U][2U];
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+	    [8U][3U];
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+	vcdp->chgArray(c+4444,(__Vtemp1239),128);
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+	vcdp->chgArray(c+4452,(__Vtemp1241),128);
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+	vcdp->chgBit  (c+4551,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[7]));
+	vcdp->chgBit  (c+4552,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[8]));
+	vcdp->chgBit  (c+4553,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[9]));
+	vcdp->chgBit  (c+4554,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[10]));
+	vcdp->chgBit  (c+4555,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[11]));
+	vcdp->chgBit  (c+4556,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[12]));
+	vcdp->chgBit  (c+4557,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[13]));
+	vcdp->chgBit  (c+4558,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[14]));
+	vcdp->chgBit  (c+4559,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[15]));
+	vcdp->chgBit  (c+4560,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[16]));
+	vcdp->chgBit  (c+4561,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[17]));
+	vcdp->chgBit  (c+4562,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[18]));
+	vcdp->chgBit  (c+4563,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[19]));
+	vcdp->chgBit  (c+4564,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[20]));
+	vcdp->chgBit  (c+4565,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[21]));
+	vcdp->chgBit  (c+4566,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[22]));
+	vcdp->chgBit  (c+4567,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[23]));
+	vcdp->chgBit  (c+4568,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[24]));
+	vcdp->chgBit  (c+4569,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[25]));
+	vcdp->chgBit  (c+4570,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[26]));
+	vcdp->chgBit  (c+4571,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[27]));
+	vcdp->chgBit  (c+4572,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[28]));
+	vcdp->chgBit  (c+4573,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[29]));
+	vcdp->chgBit  (c+4574,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[30]));
+	vcdp->chgBit  (c+4575,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[31]));
+	vcdp->chgBus  (c+4576,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f),32);
+	vcdp->chgBus  (c+4577,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind),32);
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+	    [0U][0U];
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+	    [0U][1U];
+	__Vtemp1248[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0U][2U];
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+	    [0U][3U];
+	vcdp->chgArray(c+4578,(__Vtemp1248),128);
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+	    [1U][0U];
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+	    [1U][1U];
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+	    [1U][2U];
+	__Vtemp1249[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [1U][3U];
+	vcdp->chgArray(c+4582,(__Vtemp1249),128);
+	__Vtemp1250[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [2U][0U];
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+	    [2U][1U];
+	__Vtemp1250[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [2U][2U];
+	__Vtemp1250[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [2U][3U];
+	vcdp->chgArray(c+4586,(__Vtemp1250),128);
+	__Vtemp1251[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [3U][0U];
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+	    [3U][1U];
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+	    [3U][2U];
+	__Vtemp1251[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [3U][3U];
+	vcdp->chgArray(c+4590,(__Vtemp1251),128);
+	__Vtemp1252[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [4U][0U];
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+	    [4U][1U];
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+	    [4U][2U];
+	__Vtemp1252[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [4U][3U];
+	vcdp->chgArray(c+4594,(__Vtemp1252),128);
+	__Vtemp1253[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [5U][0U];
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+	    [5U][1U];
+	__Vtemp1253[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [5U][2U];
+	__Vtemp1253[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [5U][3U];
+	vcdp->chgArray(c+4598,(__Vtemp1253),128);
+	__Vtemp1254[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [6U][0U];
+	__Vtemp1254[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [6U][1U];
+	__Vtemp1254[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [6U][2U];
+	__Vtemp1254[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
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+	vcdp->chgArray(c+4602,(__Vtemp1254),128);
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+	vcdp->chgBit  (c+4748,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[10]));
+	vcdp->chgBit  (c+4749,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[11]));
+	vcdp->chgBit  (c+4750,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[12]));
+	vcdp->chgBit  (c+4751,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[13]));
+	vcdp->chgBit  (c+4752,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[14]));
+	vcdp->chgBit  (c+4753,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[15]));
+	vcdp->chgBit  (c+4754,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[16]));
+	vcdp->chgBit  (c+4755,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[17]));
+	vcdp->chgBit  (c+4756,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[18]));
+	vcdp->chgBit  (c+4757,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[19]));
+	vcdp->chgBit  (c+4758,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[20]));
+	vcdp->chgBit  (c+4759,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[21]));
+	vcdp->chgBit  (c+4760,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[22]));
+	vcdp->chgBit  (c+4761,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[23]));
+	vcdp->chgBit  (c+4762,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[24]));
+	vcdp->chgBit  (c+4763,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[25]));
+	vcdp->chgBit  (c+4764,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[26]));
+	vcdp->chgBit  (c+4765,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[27]));
+	vcdp->chgBit  (c+4766,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[28]));
+	vcdp->chgBit  (c+4767,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[29]));
+	vcdp->chgBit  (c+4768,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[30]));
+	vcdp->chgBit  (c+4769,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[31]));
+	vcdp->chgBit  (c+4770,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0]));
+	vcdp->chgBit  (c+4771,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[1]));
+	vcdp->chgBit  (c+4772,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[2]));
+	vcdp->chgBit  (c+4773,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[3]));
+	vcdp->chgBit  (c+4774,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[4]));
+	vcdp->chgBit  (c+4775,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[5]));
+	vcdp->chgBit  (c+4776,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[6]));
+	vcdp->chgBit  (c+4777,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[7]));
+	vcdp->chgBit  (c+4778,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[8]));
+	vcdp->chgBit  (c+4779,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[9]));
+	vcdp->chgBit  (c+4780,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[10]));
+	vcdp->chgBit  (c+4781,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[11]));
+	vcdp->chgBit  (c+4782,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[12]));
+	vcdp->chgBit  (c+4783,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[13]));
+	vcdp->chgBit  (c+4784,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[14]));
+	vcdp->chgBit  (c+4785,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[15]));
+	vcdp->chgBit  (c+4786,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[16]));
+	vcdp->chgBit  (c+4787,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[17]));
+	vcdp->chgBit  (c+4788,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[18]));
+	vcdp->chgBit  (c+4789,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[19]));
+	vcdp->chgBit  (c+4790,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[20]));
+	vcdp->chgBit  (c+4791,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[21]));
+	vcdp->chgBit  (c+4792,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[22]));
+	vcdp->chgBit  (c+4793,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[23]));
+	vcdp->chgBit  (c+4794,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[24]));
+	vcdp->chgBit  (c+4795,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[25]));
+	vcdp->chgBit  (c+4796,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[26]));
+	vcdp->chgBit  (c+4797,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[27]));
+	vcdp->chgBit  (c+4798,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[28]));
+	vcdp->chgBit  (c+4799,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[29]));
+	vcdp->chgBit  (c+4800,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[30]));
+	vcdp->chgBit  (c+4801,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[31]));
+	vcdp->chgBus  (c+4802,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f),32);
+	vcdp->chgBus  (c+4803,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind),32);
     }
 }
 
@@ -5871,23 +8988,23 @@ void Vcache_simX::traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, Verilat
     if (0 && vcdp && c) {}  // Prevent unused
     // Body
     {
-	vcdp->chgBit  (c+3063,(vlTOPp->clk));
-	vcdp->chgBit  (c+3064,(vlTOPp->reset));
-	vcdp->chgBus  (c+3065,(vlTOPp->in_icache_pc_addr),32);
-	vcdp->chgBit  (c+3066,(vlTOPp->in_icache_valid_pc_addr));
-	vcdp->chgBit  (c+3067,(vlTOPp->out_icache_stall));
-	vcdp->chgBus  (c+3068,(vlTOPp->in_dcache_mem_read),3);
-	vcdp->chgBus  (c+3069,(vlTOPp->in_dcache_mem_write),3);
-	vcdp->chgBit  (c+3070,(vlTOPp->in_dcache_in_valid[0]));
-	vcdp->chgBit  (c+3071,(vlTOPp->in_dcache_in_valid[1]));
-	vcdp->chgBit  (c+3072,(vlTOPp->in_dcache_in_valid[2]));
-	vcdp->chgBit  (c+3073,(vlTOPp->in_dcache_in_valid[3]));
-	vcdp->chgBus  (c+3074,(vlTOPp->in_dcache_in_address[0]),32);
-	vcdp->chgBus  (c+3075,(vlTOPp->in_dcache_in_address[1]),32);
-	vcdp->chgBus  (c+3076,(vlTOPp->in_dcache_in_address[2]),32);
-	vcdp->chgBus  (c+3077,(vlTOPp->in_dcache_in_address[3]),32);
-	vcdp->chgBit  (c+3078,(vlTOPp->out_dcache_stall));
-	vcdp->chgBus  (c+3079,(((IData)(vlTOPp->in_icache_valid_pc_addr)
+	vcdp->chgBit  (c+4804,(vlTOPp->clk));
+	vcdp->chgBit  (c+4805,(vlTOPp->reset));
+	vcdp->chgBus  (c+4806,(vlTOPp->in_icache_pc_addr),32);
+	vcdp->chgBit  (c+4807,(vlTOPp->in_icache_valid_pc_addr));
+	vcdp->chgBit  (c+4808,(vlTOPp->out_icache_stall));
+	vcdp->chgBus  (c+4809,(vlTOPp->in_dcache_mem_read),3);
+	vcdp->chgBus  (c+4810,(vlTOPp->in_dcache_mem_write),3);
+	vcdp->chgBit  (c+4811,(vlTOPp->in_dcache_in_valid[0]));
+	vcdp->chgBit  (c+4812,(vlTOPp->in_dcache_in_valid[1]));
+	vcdp->chgBit  (c+4813,(vlTOPp->in_dcache_in_valid[2]));
+	vcdp->chgBit  (c+4814,(vlTOPp->in_dcache_in_valid[3]));
+	vcdp->chgBus  (c+4815,(vlTOPp->in_dcache_in_address[0]),32);
+	vcdp->chgBus  (c+4816,(vlTOPp->in_dcache_in_address[1]),32);
+	vcdp->chgBus  (c+4817,(vlTOPp->in_dcache_in_address[2]),32);
+	vcdp->chgBus  (c+4818,(vlTOPp->in_dcache_in_address[3]),32);
+	vcdp->chgBit  (c+4819,(vlTOPp->out_dcache_stall));
+	vcdp->chgBus  (c+4820,(((IData)(vlTOPp->in_icache_valid_pc_addr)
 				 ? 2U : 7U)),3);
     }
 }
diff --git a/simX/obj_dir/Vcache_simX__Trace__Slow.cpp b/simX/obj_dir/Vcache_simX__Trace__Slow.cpp
index 7b113aa4..5ee1798e 100644
--- a/simX/obj_dir/Vcache_simX__Trace__Slow.cpp
+++ b/simX/obj_dir/Vcache_simX__Trace__Slow.cpp
@@ -57,41 +57,41 @@ void Vcache_simX::traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
     if (0 && vcdp && c) {}  // Prevent unused
     // Body
     {
-	vcdp->declBit  (c+3063,"clk",-1);
-	vcdp->declBit  (c+3064,"reset",-1);
-	vcdp->declBus  (c+3065,"in_icache_pc_addr",-1,31,0);
-	vcdp->declBit  (c+3066,"in_icache_valid_pc_addr",-1);
-	vcdp->declBit  (c+3067,"out_icache_stall",-1);
-	vcdp->declBus  (c+3068,"in_dcache_mem_read",-1,2,0);
-	vcdp->declBus  (c+3069,"in_dcache_mem_write",-1,2,0);
+	vcdp->declBit  (c+4804,"clk",-1);
+	vcdp->declBit  (c+4805,"reset",-1);
+	vcdp->declBus  (c+4806,"in_icache_pc_addr",-1,31,0);
+	vcdp->declBit  (c+4807,"in_icache_valid_pc_addr",-1);
+	vcdp->declBit  (c+4808,"out_icache_stall",-1);
+	vcdp->declBus  (c+4809,"in_dcache_mem_read",-1,2,0);
+	vcdp->declBus  (c+4810,"in_dcache_mem_write",-1,2,0);
 	{int i; for (i=0; i<4; i++) {
-		vcdp->declBit  (c+3070+i*1,"in_dcache_in_valid",(i+0));}}
+		vcdp->declBit  (c+4811+i*1,"in_dcache_in_valid",(i+0));}}
 	{int i; for (i=0; i<4; i++) {
-		vcdp->declBus  (c+3074+i*1,"in_dcache_in_address",(i+0),31,0);}}
-	vcdp->declBit  (c+3078,"out_dcache_stall",-1);
-	vcdp->declBit  (c+3063,"cache_simX clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX reset",-1);
-	vcdp->declBus  (c+3065,"cache_simX in_icache_pc_addr",-1,31,0);
-	vcdp->declBit  (c+3066,"cache_simX in_icache_valid_pc_addr",-1);
-	vcdp->declBit  (c+3067,"cache_simX out_icache_stall",-1);
-	vcdp->declBus  (c+3068,"cache_simX in_dcache_mem_read",-1,2,0);
-	vcdp->declBus  (c+3069,"cache_simX in_dcache_mem_write",-1,2,0);
+		vcdp->declBus  (c+4815+i*1,"in_dcache_in_address",(i+0),31,0);}}
+	vcdp->declBit  (c+4819,"out_dcache_stall",-1);
+	vcdp->declBit  (c+4804,"cache_simX clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX reset",-1);
+	vcdp->declBus  (c+4806,"cache_simX in_icache_pc_addr",-1,31,0);
+	vcdp->declBit  (c+4807,"cache_simX in_icache_valid_pc_addr",-1);
+	vcdp->declBit  (c+4808,"cache_simX out_icache_stall",-1);
+	vcdp->declBus  (c+4809,"cache_simX in_dcache_mem_read",-1,2,0);
+	vcdp->declBus  (c+4810,"cache_simX in_dcache_mem_write",-1,2,0);
 	{int i; for (i=0; i<4; i++) {
-		vcdp->declBit  (c+3070+i*1,"cache_simX in_dcache_in_valid",(i+0));}}
+		vcdp->declBit  (c+4811+i*1,"cache_simX in_dcache_in_valid",(i+0));}}
 	{int i; for (i=0; i<4; i++) {
-		vcdp->declBus  (c+3074+i*1,"cache_simX in_dcache_in_address",(i+0),31,0);}}
-	vcdp->declBit  (c+3078,"cache_simX out_dcache_stall",-1);
+		vcdp->declBus  (c+4815+i*1,"cache_simX in_dcache_in_address",(i+0),31,0);}}
+	vcdp->declBit  (c+4819,"cache_simX out_dcache_stall",-1);
 	// Tracing: cache_simX VX_icache_req__Viftop // Ignored: Verilator trace_off at cache_simX.v:28
 	// Tracing: cache_simX VX_icache_rsp__Viftop // Ignored: Verilator trace_off at cache_simX.v:36
 	// Tracing: cache_simX VX_dram_req_rsp_icache__Viftop // Ignored: Verilator trace_off at cache_simX.v:45
-	vcdp->declBit  (c+708,"cache_simX icache_i_m_ready",-1);
+	vcdp->declBit  (c+1163,"cache_simX icache_i_m_ready",-1);
 	// Tracing: cache_simX VX_dcache_req__Viftop // Ignored: Verilator trace_off at cache_simX.v:55
 	// Tracing: cache_simX curr_t // Ignored: Verilator trace_off at cache_simX.v:60
 	// Tracing: cache_simX VX_dcache_rsp__Viftop // Ignored: Verilator trace_off at cache_simX.v:67
 	// Tracing: cache_simX VX_dram_req_rsp__Viftop // Ignored: Verilator trace_off at cache_simX.v:76
-	vcdp->declBit  (c+709,"cache_simX dcache_i_m_ready",-1);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller reset",-1);
+	vcdp->declBit  (c+1164,"cache_simX dcache_i_m_ready",-1);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller reset",-1);
 	// Tracing: cache_simX dmem_controller VX_dram_req_rsp // Ignored: Unsupported: data type at ../rtl/VX_dmem_controller.v:8
 	// Tracing: cache_simX dmem_controller VX_dram_req_rsp_icache // Ignored: Unsupported: data type at ../rtl/VX_dmem_controller.v:9
 	// Tracing: cache_simX dmem_controller VX_icache_req // Ignored: Unsupported: data type at ../rtl/VX_dmem_controller.v:11
@@ -105,42 +105,42 @@ void Vcache_simX::traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 	vcdp->declArray(c+5,"cache_simX dmem_controller cache_driver_in_address",-1,127,0);
 	vcdp->declBus  (c+9,"cache_simX dmem_controller cache_driver_in_mem_read",-1,2,0);
 	vcdp->declBus  (c+10,"cache_simX dmem_controller cache_driver_in_mem_write",-1,2,0);
-	vcdp->declArray(c+3080,"cache_simX dmem_controller cache_driver_in_data",-1,127,0);
+	vcdp->declArray(c+4821,"cache_simX dmem_controller cache_driver_in_data",-1,127,0);
 	vcdp->declBus  (c+11,"cache_simX dmem_controller sm_driver_in_mem_read",-1,2,0);
 	vcdp->declBus  (c+12,"cache_simX dmem_controller sm_driver_in_mem_write",-1,2,0);
 	vcdp->declArray(c+13,"cache_simX dmem_controller cache_driver_out_data",-1,127,0);
 	vcdp->declArray(c+17,"cache_simX dmem_controller sm_driver_out_data",-1,127,0);
 	vcdp->declBus  (c+21,"cache_simX dmem_controller cache_driver_out_valid",-1,3,0);
 	vcdp->declBit  (c+22,"cache_simX dmem_controller sm_delay",-1);
-	vcdp->declBit  (c+583,"cache_simX dmem_controller cache_delay",-1);
-	vcdp->declBus  (c+584,"cache_simX dmem_controller icache_instruction_out",-1,31,0);
-	vcdp->declBit  (c+585,"cache_simX dmem_controller icache_delay",-1);
-	vcdp->declBit  (c+3066,"cache_simX dmem_controller icache_driver_in_valid",-1);
-	vcdp->declBus  (c+3065,"cache_simX dmem_controller icache_driver_in_address",-1,31,0);
+	vcdp->declBit  (c+1033,"cache_simX dmem_controller cache_delay",-1);
+	vcdp->declBus  (c+1034,"cache_simX dmem_controller icache_instruction_out",-1,31,0);
+	vcdp->declBit  (c+1035,"cache_simX dmem_controller icache_delay",-1);
+	vcdp->declBit  (c+4807,"cache_simX dmem_controller icache_driver_in_valid",-1);
+	vcdp->declBus  (c+4806,"cache_simX dmem_controller icache_driver_in_address",-1,31,0);
 	vcdp->declBus  (c+23,"cache_simX dmem_controller icache_driver_in_mem_read",-1,2,0);
-	vcdp->declBus  (c+3084,"cache_simX dmem_controller icache_driver_in_mem_write",-1,2,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache_driver_in_data",-1,31,0);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller read_or_write_ic",-1);
-	vcdp->declBit  (c+586,"cache_simX dmem_controller valid_read_cache",-1);
-	vcdp->declBus  (c+3087,"cache_simX dmem_controller shared_memory SM_SIZE",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory SM_BANKS",-1,31,0);
-	vcdp->declBus  (c+3089,"cache_simX dmem_controller shared_memory SM_BYTES_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory SM_WORDS_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller shared_memory SM_LOG_WORDS_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3091,"cache_simX dmem_controller shared_memory SM_HEIGHT",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller shared_memory SM_BANK_OFFSET_START",-1,31,0);
-	vcdp->declBus  (c+3092,"cache_simX dmem_controller shared_memory SM_BANK_OFFSET_END",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory SM_BLOCK_OFFSET_START",-1,31,0);
-	vcdp->declBus  (c+3093,"cache_simX dmem_controller shared_memory SM_BLOCK_OFFSET_END",-1,31,0);
-	vcdp->declBus  (c+3094,"cache_simX dmem_controller shared_memory SM_INDEX_START",-1,31,0);
-	vcdp->declBus  (c+3095,"cache_simX dmem_controller shared_memory SM_INDEX_END",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller shared_memory BITS_PER_BANK",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller shared_memory clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller shared_memory reset",-1);
+	vcdp->declBus  (c+4825,"cache_simX dmem_controller icache_driver_in_mem_write",-1,2,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache_driver_in_data",-1,31,0);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller read_or_write_ic",-1);
+	vcdp->declBit  (c+1036,"cache_simX dmem_controller valid_read_cache",-1);
+	vcdp->declBus  (c+4828,"cache_simX dmem_controller shared_memory SM_SIZE",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory SM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4830,"cache_simX dmem_controller shared_memory SM_BYTES_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory SM_WORDS_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller shared_memory SM_LOG_WORDS_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4832,"cache_simX dmem_controller shared_memory SM_HEIGHT",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller shared_memory SM_BANK_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4833,"cache_simX dmem_controller shared_memory SM_BANK_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory SM_BLOCK_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4834,"cache_simX dmem_controller shared_memory SM_BLOCK_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller shared_memory SM_INDEX_START",-1,31,0);
+	vcdp->declBus  (c+4836,"cache_simX dmem_controller shared_memory SM_INDEX_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller shared_memory BITS_PER_BANK",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller shared_memory clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller shared_memory reset",-1);
 	vcdp->declBus  (c+2,"cache_simX dmem_controller shared_memory in_valid",-1,3,0);
 	vcdp->declArray(c+5,"cache_simX dmem_controller shared_memory in_address",-1,127,0);
-	vcdp->declArray(c+3080,"cache_simX dmem_controller shared_memory in_data",-1,127,0);
+	vcdp->declArray(c+4821,"cache_simX dmem_controller shared_memory in_data",-1,127,0);
 	vcdp->declBus  (c+11,"cache_simX dmem_controller shared_memory mem_read",-1,2,0);
 	vcdp->declBus  (c+12,"cache_simX dmem_controller shared_memory mem_write",-1,2,0);
 	vcdp->declBus  (c+21,"cache_simX dmem_controller shared_memory out_valid",-1,3,0);
@@ -160,192 +160,192 @@ void Vcache_simX::traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 	vcdp->declBus  (c+74,"cache_simX dmem_controller shared_memory orig_in_valid",-1,3,0);
 	// Tracing: cache_simX dmem_controller shared_memory f // Ignored: Verilator trace_off at ../rtl/shared_memory/VX_shared_memory.v:62
 	// Tracing: cache_simX dmem_controller shared_memory j // Ignored: Verilator trace_off at ../rtl/shared_memory/VX_shared_memory.v:91
-	vcdp->declBus  (c+3096,"cache_simX dmem_controller shared_memory i",-1,31,0);
+	vcdp->declBus  (c+4837,"cache_simX dmem_controller shared_memory i",-1,31,0);
 	vcdp->declBit  (c+75,"cache_simX dmem_controller shared_memory genblk2[0] shm_write",-1);
 	vcdp->declBit  (c+76,"cache_simX dmem_controller shared_memory genblk2[1] shm_write",-1);
 	vcdp->declBit  (c+77,"cache_simX dmem_controller shared_memory genblk2[2] shm_write",-1);
 	vcdp->declBit  (c+78,"cache_simX dmem_controller shared_memory genblk2[3] shm_write",-1);
-	vcdp->declBus  (c+3092,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm NB",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm BITS_PER_BANK",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm NUM_REQ",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm reset",-1);
+	vcdp->declBus  (c+4833,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm NB",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm BITS_PER_BANK",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm NUM_REQ",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm reset",-1);
 	vcdp->declBus  (c+74,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm in_valid",-1,3,0);
 	vcdp->declArray(c+5,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm in_address",-1,127,0);
-	vcdp->declArray(c+3080,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm in_data",-1,127,0);
+	vcdp->declArray(c+4821,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm in_data",-1,127,0);
 	vcdp->declBus  (c+32,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm out_valid",-1,3,0);
 	vcdp->declArray(c+24,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm out_address",-1,127,0);
 	vcdp->declArray(c+28,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm out_data",-1,127,0);
 	vcdp->declBus  (c+73,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm req_num",-1,11,0);
 	vcdp->declBit  (c+22,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm stall",-1);
 	vcdp->declBit  (c+72,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm send_data",-1);
-	vcdp->declBus  (c+710,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm left_requests",-1,3,0);
+	vcdp->declBus  (c+1165,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm left_requests",-1,3,0);
 	vcdp->declBus  (c+79,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm serviced",-1,3,0);
 	vcdp->declBus  (c+80,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm use_valid",-1,3,0);
-	vcdp->declBit  (c+711,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm requests_left",-1);
+	vcdp->declBit  (c+1166,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm requests_left",-1);
 	vcdp->declBus  (c+81,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm bank_valids",-1,15,0);
 	vcdp->declBus  (c+82,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm more_than_one_valid",-1,3,0);
 	// Tracing: cache_simX dmem_controller shared_memory vx_priority_encoder_sm curr_bank // Ignored: Verilator trace_off at ../rtl/shared_memory/VX_priority_encoder_sm.v:49
 	vcdp->declBus  (c+83,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm internal_req_num",-1,7,0);
 	vcdp->declBus  (c+32,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm internal_out_valid",-1,3,0);
 	// Tracing: cache_simX dmem_controller shared_memory vx_priority_encoder_sm curr_bank_o // Ignored: Verilator trace_off at ../rtl/shared_memory/VX_priority_encoder_sm.v:73
-	vcdp->declBus  (c+3096,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm curr_b",-1,31,0);
+	vcdp->declBus  (c+4837,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm curr_b",-1,31,0);
 	vcdp->declBus  (c+84,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm serviced_qual",-1,3,0);
-	vcdp->declBus  (c+587,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm new_left_requests",-1,3,0);
+	vcdp->declBus  (c+1037,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm new_left_requests",-1,3,0);
 	vcdp->declBus  (c+85,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] num_valids",-1,2,0);
 	vcdp->declBus  (c+86,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] num_valids",-1,2,0);
 	vcdp->declBus  (c+87,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] num_valids",-1,2,0);
 	vcdp->declBus  (c+88,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] num_valids",-1,2,0);
-	vcdp->declBus  (c+3092,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid NB",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid BITS_PER_BANK",-1,31,0);
+	vcdp->declBus  (c+4833,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid NB",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid BITS_PER_BANK",-1,31,0);
 	vcdp->declBus  (c+80,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid in_valids",-1,3,0);
 	vcdp->declArray(c+5,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid in_addr",-1,127,0);
 	vcdp->declBus  (c+81,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid bank_valids",-1,15,0);
-	vcdp->declBus  (c+3096,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid i",-1,31,0);
-	vcdp->declBus  (c+3096,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid j",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter N",-1,31,0);
+	vcdp->declBus  (c+4837,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid i",-1,31,0);
+	vcdp->declBus  (c+4837,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid j",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter N",-1,31,0);
 	vcdp->declBus  (c+89,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter valids",-1,3,0);
 	vcdp->declBus  (c+85,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter count",-1,2,0);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter i",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter N",-1,31,0);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter i",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter N",-1,31,0);
 	vcdp->declBus  (c+90,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter valids",-1,3,0);
 	vcdp->declBus  (c+86,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter count",-1,2,0);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter i",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter N",-1,31,0);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter i",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter N",-1,31,0);
 	vcdp->declBus  (c+91,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter valids",-1,3,0);
 	vcdp->declBus  (c+87,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter count",-1,2,0);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter i",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter N",-1,31,0);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter i",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter N",-1,31,0);
 	vcdp->declBus  (c+92,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter valids",-1,3,0);
 	vcdp->declBus  (c+88,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter count",-1,2,0);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter i",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder N",-1,31,0);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter i",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder N",-1,31,0);
 	vcdp->declBus  (c+89,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder valids",-1,3,0);
 	vcdp->declBus  (c+93,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder index",-1,1,0);
 	vcdp->declBit  (c+94,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder found",-1);
 	vcdp->declBus  (c+95,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder i",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder N",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder N",-1,31,0);
 	vcdp->declBus  (c+90,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder valids",-1,3,0);
 	vcdp->declBus  (c+96,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder index",-1,1,0);
 	vcdp->declBit  (c+97,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder found",-1);
 	vcdp->declBus  (c+98,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder i",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder N",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder N",-1,31,0);
 	vcdp->declBus  (c+91,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder valids",-1,3,0);
 	vcdp->declBus  (c+99,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder index",-1,1,0);
 	vcdp->declBit  (c+100,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder found",-1);
 	vcdp->declBus  (c+101,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder i",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder N",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder N",-1,31,0);
 	vcdp->declBus  (c+92,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder valids",-1,3,0);
 	vcdp->declBus  (c+102,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder index",-1,1,0);
 	vcdp->declBit  (c+103,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder found",-1);
 	vcdp->declBus  (c+104,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder i",-1,31,0);
-	vcdp->declBus  (c+3098,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_SIZE",-1,31,0);
-	vcdp->declBus  (c+3089,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3091,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_HEIGHT",-1,31,0);
-	vcdp->declBus  (c+3092,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block BITS_PER_BANK",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block reset",-1);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_SIZE",-1,31,0);
+	vcdp->declBus  (c+4830,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4832,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_HEIGHT",-1,31,0);
+	vcdp->declBus  (c+4833,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block BITS_PER_BANK",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block reset",-1);
 	vcdp->declBus  (c+105,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block addr",-1,6,0);
 	vcdp->declArray(c+106,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block wdata",-1,127,0);
 	vcdp->declBus  (c+110,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block we",-1,1,0);
 	vcdp->declBit  (c+75,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block shm_write",-1);
-	vcdp->declArray(c+588,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block data_out",-1,127,0);
+	vcdp->declArray(c+1038,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block data_out",-1,127,0);
 	// Tracing: cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block shared_memory // Ignored: Wide memory > --trace-max-array ents at ../rtl/shared_memory/VX_shared_memory_block.v:32
-	vcdp->declBus  (c+712,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block curr_ind",-1,31,0);
-	vcdp->declBus  (c+3098,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_SIZE",-1,31,0);
-	vcdp->declBus  (c+3089,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3091,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_HEIGHT",-1,31,0);
-	vcdp->declBus  (c+3092,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block BITS_PER_BANK",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block reset",-1);
+	vcdp->declBus  (c+1167,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block curr_ind",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_SIZE",-1,31,0);
+	vcdp->declBus  (c+4830,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4832,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_HEIGHT",-1,31,0);
+	vcdp->declBus  (c+4833,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block BITS_PER_BANK",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block reset",-1);
 	vcdp->declBus  (c+111,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block addr",-1,6,0);
 	vcdp->declArray(c+112,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block wdata",-1,127,0);
 	vcdp->declBus  (c+116,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block we",-1,1,0);
 	vcdp->declBit  (c+76,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block shm_write",-1);
-	vcdp->declArray(c+592,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block data_out",-1,127,0);
+	vcdp->declArray(c+1042,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block data_out",-1,127,0);
 	// Tracing: cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block shared_memory // Ignored: Wide memory > --trace-max-array ents at ../rtl/shared_memory/VX_shared_memory_block.v:32
-	vcdp->declBus  (c+713,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block curr_ind",-1,31,0);
-	vcdp->declBus  (c+3098,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_SIZE",-1,31,0);
-	vcdp->declBus  (c+3089,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3091,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_HEIGHT",-1,31,0);
-	vcdp->declBus  (c+3092,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block BITS_PER_BANK",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block reset",-1);
+	vcdp->declBus  (c+1168,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block curr_ind",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_SIZE",-1,31,0);
+	vcdp->declBus  (c+4830,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4832,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_HEIGHT",-1,31,0);
+	vcdp->declBus  (c+4833,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block BITS_PER_BANK",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block reset",-1);
 	vcdp->declBus  (c+117,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block addr",-1,6,0);
 	vcdp->declArray(c+118,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block wdata",-1,127,0);
 	vcdp->declBus  (c+122,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block we",-1,1,0);
 	vcdp->declBit  (c+77,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block shm_write",-1);
-	vcdp->declArray(c+596,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block data_out",-1,127,0);
+	vcdp->declArray(c+1046,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block data_out",-1,127,0);
 	// Tracing: cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block shared_memory // Ignored: Wide memory > --trace-max-array ents at ../rtl/shared_memory/VX_shared_memory_block.v:32
-	vcdp->declBus  (c+714,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block curr_ind",-1,31,0);
-	vcdp->declBus  (c+3098,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_SIZE",-1,31,0);
-	vcdp->declBus  (c+3089,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0);
-	vcdp->declBus  (c+3091,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_HEIGHT",-1,31,0);
-	vcdp->declBus  (c+3092,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block BITS_PER_BANK",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block reset",-1);
+	vcdp->declBus  (c+1169,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block curr_ind",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_SIZE",-1,31,0);
+	vcdp->declBus  (c+4830,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0);
+	vcdp->declBus  (c+4832,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_HEIGHT",-1,31,0);
+	vcdp->declBus  (c+4833,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block BITS_PER_BANK",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block reset",-1);
 	vcdp->declBus  (c+123,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block addr",-1,6,0);
 	vcdp->declArray(c+124,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block wdata",-1,127,0);
 	vcdp->declBus  (c+128,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block we",-1,1,0);
 	vcdp->declBit  (c+78,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block shm_write",-1);
-	vcdp->declArray(c+600,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block data_out",-1,127,0);
+	vcdp->declArray(c+1050,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block data_out",-1,127,0);
 	// Tracing: cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block shared_memory // Ignored: Wide memory > --trace-max-array ents at ../rtl/shared_memory/VX_shared_memory_block.v:32
-	vcdp->declBus  (c+715,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block curr_ind",-1,31,0);
-	vcdp->declBus  (c+3098,"cache_simX dmem_controller dcache CACHE_SIZE",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3099,"cache_simX dmem_controller dcache CACHE_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache CACHE_BANKS",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache LOG_NUM_BANKS",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache LOG_NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache OFFSET_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache OFFSET_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache IND_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3103,"cache_simX dmem_controller dcache ADDR_TAG_START",-1,31,0);
-	vcdp->declBus  (c+3104,"cache_simX dmem_controller dcache ADDR_TAG_END",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache ADDR_OFFSET_START",-1,31,0);
-	vcdp->declBus  (c+3093,"cache_simX dmem_controller dcache ADDR_OFFSET_END",-1,31,0);
-	vcdp->declBus  (c+3094,"cache_simX dmem_controller dcache ADDR_IND_START",-1,31,0);
-	vcdp->declBus  (c+3105,"cache_simX dmem_controller dcache ADDR_IND_END",-1,31,0);
-	vcdp->declBus  (c+3106,"cache_simX dmem_controller dcache MEM_ADDR_REQ_MASK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache rst",-1);
+	vcdp->declBus  (c+1170,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block curr_ind",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller dcache CACHE_SIZE",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4840,"cache_simX dmem_controller dcache CACHE_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache CACHE_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache LOG_NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache OFFSET_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache OFFSET_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache IND_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4844,"cache_simX dmem_controller dcache ADDR_TAG_START",-1,31,0);
+	vcdp->declBus  (c+4845,"cache_simX dmem_controller dcache ADDR_TAG_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache ADDR_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4834,"cache_simX dmem_controller dcache ADDR_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller dcache ADDR_IND_START",-1,31,0);
+	vcdp->declBus  (c+4846,"cache_simX dmem_controller dcache ADDR_IND_END",-1,31,0);
+	vcdp->declBus  (c+4847,"cache_simX dmem_controller dcache MEM_ADDR_REQ_MASK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache rst",-1);
 	vcdp->declBus  (c+3,"cache_simX dmem_controller dcache i_p_valid",-1,3,0);
 	vcdp->declArray(c+5,"cache_simX dmem_controller dcache i_p_addr",-1,127,0);
-	vcdp->declArray(c+3080,"cache_simX dmem_controller dcache i_p_writedata",-1,127,0);
+	vcdp->declArray(c+4821,"cache_simX dmem_controller dcache i_p_writedata",-1,127,0);
 	vcdp->declBit  (c+4,"cache_simX dmem_controller dcache i_p_read_or_write",-1);
 	vcdp->declArray(c+13,"cache_simX dmem_controller dcache o_p_readdata",-1,127,0);
-	vcdp->declBit  (c+583,"cache_simX dmem_controller dcache o_p_delay",-1);
+	vcdp->declBit  (c+1033,"cache_simX dmem_controller dcache o_p_delay",-1);
 	vcdp->declBus  (c+129,"cache_simX dmem_controller dcache o_m_evict_addr",-1,31,0);
-	vcdp->declBus  (c+716,"cache_simX dmem_controller dcache o_m_read_addr",-1,31,0);
-	vcdp->declBit  (c+717,"cache_simX dmem_controller dcache o_m_valid",-1);
+	vcdp->declBus  (c+1171,"cache_simX dmem_controller dcache o_m_read_addr",-1,31,0);
+	vcdp->declBit  (c+1172,"cache_simX dmem_controller dcache o_m_valid",-1);
 	vcdp->declArray(c+130,"cache_simX dmem_controller dcache o_m_writedata",-1,511,0);
-	vcdp->declBit  (c+604,"cache_simX dmem_controller dcache o_m_read_or_write",-1);
-	vcdp->declArray(c+3107,"cache_simX dmem_controller dcache i_m_readdata",-1,511,0);
-	vcdp->declBit  (c+709,"cache_simX dmem_controller dcache i_m_ready",-1);
+	vcdp->declBit  (c+1054,"cache_simX dmem_controller dcache o_m_read_or_write",-1);
+	vcdp->declArray(c+4848,"cache_simX dmem_controller dcache i_m_readdata",-1,511,0);
+	vcdp->declBit  (c+1164,"cache_simX dmem_controller dcache i_m_ready",-1);
 	vcdp->declBus  (c+9,"cache_simX dmem_controller dcache i_p_mem_read",-1,2,0);
 	vcdp->declBus  (c+10,"cache_simX dmem_controller dcache i_p_mem_write",-1,2,0);
-	vcdp->declArray(c+718,"cache_simX dmem_controller dcache final_data_read",-1,127,0);
+	vcdp->declArray(c+1173,"cache_simX dmem_controller dcache final_data_read",-1,127,0);
 	vcdp->declArray(c+146,"cache_simX dmem_controller dcache new_final_data_read",-1,127,0);
 	vcdp->declArray(c+13,"cache_simX dmem_controller dcache new_final_data_read_Qual",-1,127,0);
-	vcdp->declBus  (c+722,"cache_simX dmem_controller dcache global_way_to_evict",-1,0,0);
+	vcdp->declBus  (c+1177,"cache_simX dmem_controller dcache global_way_to_evict",-1,0,0);
 	vcdp->declBus  (c+150,"cache_simX dmem_controller dcache thread_track_banks",-1,15,0);
 	vcdp->declBus  (c+151,"cache_simX dmem_controller dcache index_per_bank",-1,7,0);
 	vcdp->declBus  (c+152,"cache_simX dmem_controller dcache use_mask_per_bank",-1,15,0);
@@ -354,30 +354,30 @@ void Vcache_simX::traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 	vcdp->declArray(c+155,"cache_simX dmem_controller dcache readdata_per_bank",-1,127,0);
 	vcdp->declBus  (c+159,"cache_simX dmem_controller dcache hit_per_bank",-1,3,0);
 	vcdp->declBus  (c+160,"cache_simX dmem_controller dcache eviction_wb",-1,3,0);
-	vcdp->declBus  (c+3123,"cache_simX dmem_controller dcache eviction_wb_old",-1,3,0);
-	vcdp->declBus  (c+723,"cache_simX dmem_controller dcache state",-1,3,0);
+	vcdp->declBus  (c+4864,"cache_simX dmem_controller dcache eviction_wb_old",-1,3,0);
+	vcdp->declBus  (c+1178,"cache_simX dmem_controller dcache state",-1,3,0);
 	vcdp->declBus  (c+161,"cache_simX dmem_controller dcache new_state",-1,3,0);
 	vcdp->declBus  (c+162,"cache_simX dmem_controller dcache use_valid",-1,3,0);
-	vcdp->declBus  (c+724,"cache_simX dmem_controller dcache stored_valid",-1,3,0);
+	vcdp->declBus  (c+1179,"cache_simX dmem_controller dcache stored_valid",-1,3,0);
 	vcdp->declBus  (c+163,"cache_simX dmem_controller dcache new_stored_valid",-1,3,0);
 	vcdp->declArray(c+164,"cache_simX dmem_controller dcache eviction_addr_per_bank",-1,127,0);
-	vcdp->declBus  (c+725,"cache_simX dmem_controller dcache miss_addr",-1,31,0);
+	vcdp->declBus  (c+1180,"cache_simX dmem_controller dcache miss_addr",-1,31,0);
 	vcdp->declBit  (c+168,"cache_simX dmem_controller dcache curr_processor_request_valid",-1);
 	vcdp->declBus  (c+169,"cache_simX dmem_controller dcache threads_serviced_Qual",-1,3,0);
 	{int i; for (i=0; i<4; i++) {
 		vcdp->declBus  (c+170+i*1,"cache_simX dmem_controller dcache debug_hit_per_bank_mask",(i+0),3,0);}}
 	// Tracing: cache_simX dmem_controller dcache bid // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:163
-	vcdp->declBus  (c+3096,"cache_simX dmem_controller dcache test_bid",-1,31,0);
+	vcdp->declBus  (c+4837,"cache_simX dmem_controller dcache test_bid",-1,31,0);
 	vcdp->declBus  (c+174,"cache_simX dmem_controller dcache detect_bank_miss",-1,3,0);
-	vcdp->declBus  (c+3096,"cache_simX dmem_controller dcache bbid",-1,31,0);
+	vcdp->declBus  (c+4837,"cache_simX dmem_controller dcache bbid",-1,31,0);
 	// Tracing: cache_simX dmem_controller dcache tid // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:209
-	vcdp->declBit  (c+583,"cache_simX dmem_controller dcache delay",-1);
+	vcdp->declBit  (c+1033,"cache_simX dmem_controller dcache delay",-1);
 	vcdp->declBus  (c+151,"cache_simX dmem_controller dcache send_index_to_bank",-1,7,0);
 	vcdp->declBus  (c+175,"cache_simX dmem_controller dcache miss_bank_index",-1,1,0);
 	vcdp->declBit  (c+176,"cache_simX dmem_controller dcache miss_found",-1);
-	vcdp->declBit  (c+605,"cache_simX dmem_controller dcache update_global_way_to_evict",-1);
+	vcdp->declBit  (c+1055,"cache_simX dmem_controller dcache update_global_way_to_evict",-1);
 	// Tracing: cache_simX dmem_controller dcache cur_t // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:249
-	vcdp->declBus  (c+3124,"cache_simX dmem_controller dcache init_b",-1,31,0);
+	vcdp->declBus  (c+4865,"cache_simX dmem_controller dcache init_b",-1,31,0);
 	// Tracing: cache_simX dmem_controller dcache bank_id // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:294
 	vcdp->declBus  (c+177,"cache_simX dmem_controller dcache genblk1[0] use_threads_track_banks",-1,3,0);
 	vcdp->declBus  (c+178,"cache_simX dmem_controller dcache genblk1[0] use_thread_index",-1,1,0);
@@ -398,1478 +398,2291 @@ void Vcache_simX::traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 	vcdp->declBus  (c+193,"cache_simX dmem_controller dcache genblk3[0] bank_addr",-1,31,0);
 	vcdp->declBus  (c+194,"cache_simX dmem_controller dcache genblk3[0] byte_select",-1,1,0);
 	vcdp->declBus  (c+195,"cache_simX dmem_controller dcache genblk3[0] cache_tag",-1,20,0);
-	vcdp->declBus  (c+3125,"cache_simX dmem_controller dcache genblk3[0] cache_offset",-1,1,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[0] cache_index",-1,4,0);
-	vcdp->declBit  (c+196,"cache_simX dmem_controller dcache genblk3[0] normal_valid_in",-1);
-	vcdp->declBit  (c+197,"cache_simX dmem_controller dcache genblk3[0] use_valid_in",-1);
-	vcdp->declBus  (c+198,"cache_simX dmem_controller dcache genblk3[1] bank_addr",-1,31,0);
-	vcdp->declBus  (c+199,"cache_simX dmem_controller dcache genblk3[1] byte_select",-1,1,0);
-	vcdp->declBus  (c+200,"cache_simX dmem_controller dcache genblk3[1] cache_tag",-1,20,0);
-	vcdp->declBus  (c+3125,"cache_simX dmem_controller dcache genblk3[1] cache_offset",-1,1,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[1] cache_index",-1,4,0);
-	vcdp->declBit  (c+201,"cache_simX dmem_controller dcache genblk3[1] normal_valid_in",-1);
-	vcdp->declBit  (c+202,"cache_simX dmem_controller dcache genblk3[1] use_valid_in",-1);
-	vcdp->declBus  (c+203,"cache_simX dmem_controller dcache genblk3[2] bank_addr",-1,31,0);
-	vcdp->declBus  (c+204,"cache_simX dmem_controller dcache genblk3[2] byte_select",-1,1,0);
-	vcdp->declBus  (c+205,"cache_simX dmem_controller dcache genblk3[2] cache_tag",-1,20,0);
-	vcdp->declBus  (c+3125,"cache_simX dmem_controller dcache genblk3[2] cache_offset",-1,1,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[2] cache_index",-1,4,0);
-	vcdp->declBit  (c+206,"cache_simX dmem_controller dcache genblk3[2] normal_valid_in",-1);
-	vcdp->declBit  (c+207,"cache_simX dmem_controller dcache genblk3[2] use_valid_in",-1);
-	vcdp->declBus  (c+208,"cache_simX dmem_controller dcache genblk3[3] bank_addr",-1,31,0);
-	vcdp->declBus  (c+209,"cache_simX dmem_controller dcache genblk3[3] byte_select",-1,1,0);
-	vcdp->declBus  (c+210,"cache_simX dmem_controller dcache genblk3[3] cache_tag",-1,20,0);
-	vcdp->declBus  (c+3125,"cache_simX dmem_controller dcache genblk3[3] cache_offset",-1,1,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[3] cache_index",-1,4,0);
-	vcdp->declBit  (c+211,"cache_simX dmem_controller dcache genblk3[3] normal_valid_in",-1);
-	vcdp->declBit  (c+212,"cache_simX dmem_controller dcache genblk3[3] use_valid_in",-1);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache multip_banks NUMBER_BANKS",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache multip_banks LOG_NUM_BANKS",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache multip_banks NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+196,"cache_simX dmem_controller dcache genblk3[0] cache_offset",-1,1,0);
+	vcdp->declBus  (c+197,"cache_simX dmem_controller dcache genblk3[0] cache_index",-1,4,0);
+	vcdp->declBit  (c+198,"cache_simX dmem_controller dcache genblk3[0] normal_valid_in",-1);
+	vcdp->declBit  (c+199,"cache_simX dmem_controller dcache genblk3[0] use_valid_in",-1);
+	vcdp->declBus  (c+200,"cache_simX dmem_controller dcache genblk3[1] bank_addr",-1,31,0);
+	vcdp->declBus  (c+201,"cache_simX dmem_controller dcache genblk3[1] byte_select",-1,1,0);
+	vcdp->declBus  (c+202,"cache_simX dmem_controller dcache genblk3[1] cache_tag",-1,20,0);
+	vcdp->declBus  (c+203,"cache_simX dmem_controller dcache genblk3[1] cache_offset",-1,1,0);
+	vcdp->declBus  (c+204,"cache_simX dmem_controller dcache genblk3[1] cache_index",-1,4,0);
+	vcdp->declBit  (c+205,"cache_simX dmem_controller dcache genblk3[1] normal_valid_in",-1);
+	vcdp->declBit  (c+206,"cache_simX dmem_controller dcache genblk3[1] use_valid_in",-1);
+	vcdp->declBus  (c+207,"cache_simX dmem_controller dcache genblk3[2] bank_addr",-1,31,0);
+	vcdp->declBus  (c+208,"cache_simX dmem_controller dcache genblk3[2] byte_select",-1,1,0);
+	vcdp->declBus  (c+209,"cache_simX dmem_controller dcache genblk3[2] cache_tag",-1,20,0);
+	vcdp->declBus  (c+210,"cache_simX dmem_controller dcache genblk3[2] cache_offset",-1,1,0);
+	vcdp->declBus  (c+211,"cache_simX dmem_controller dcache genblk3[2] cache_index",-1,4,0);
+	vcdp->declBit  (c+212,"cache_simX dmem_controller dcache genblk3[2] normal_valid_in",-1);
+	vcdp->declBit  (c+213,"cache_simX dmem_controller dcache genblk3[2] use_valid_in",-1);
+	vcdp->declBus  (c+214,"cache_simX dmem_controller dcache genblk3[3] bank_addr",-1,31,0);
+	vcdp->declBus  (c+215,"cache_simX dmem_controller dcache genblk3[3] byte_select",-1,1,0);
+	vcdp->declBus  (c+216,"cache_simX dmem_controller dcache genblk3[3] cache_tag",-1,20,0);
+	vcdp->declBus  (c+217,"cache_simX dmem_controller dcache genblk3[3] cache_offset",-1,1,0);
+	vcdp->declBus  (c+218,"cache_simX dmem_controller dcache genblk3[3] cache_index",-1,4,0);
+	vcdp->declBit  (c+219,"cache_simX dmem_controller dcache genblk3[3] normal_valid_in",-1);
+	vcdp->declBit  (c+220,"cache_simX dmem_controller dcache genblk3[3] use_valid_in",-1);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache multip_banks NUMBER_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache multip_banks LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache multip_banks NUM_REQ",-1,31,0);
 	vcdp->declBus  (c+162,"cache_simX dmem_controller dcache multip_banks i_p_valid",-1,3,0);
 	vcdp->declArray(c+5,"cache_simX dmem_controller dcache multip_banks i_p_addr",-1,127,0);
 	vcdp->declBus  (c+150,"cache_simX dmem_controller dcache multip_banks thread_track_banks",-1,15,0);
-	vcdp->declBus  (c+3096,"cache_simX dmem_controller dcache multip_banks t_id",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache get_miss_index N",-1,31,0);
+	vcdp->declBus  (c+4837,"cache_simX dmem_controller dcache multip_banks t_id",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache get_miss_index N",-1,31,0);
 	vcdp->declBus  (c+174,"cache_simX dmem_controller dcache get_miss_index valids",-1,3,0);
 	vcdp->declBus  (c+175,"cache_simX dmem_controller dcache get_miss_index index",-1,1,0);
 	vcdp->declBit  (c+176,"cache_simX dmem_controller dcache get_miss_index found",-1);
-	vcdp->declBus  (c+213,"cache_simX dmem_controller dcache get_miss_index i",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk1[0] choose_thread N",-1,31,0);
+	vcdp->declBus  (c+221,"cache_simX dmem_controller dcache get_miss_index i",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk1[0] choose_thread N",-1,31,0);
 	vcdp->declBus  (c+177,"cache_simX dmem_controller dcache genblk1[0] choose_thread valids",-1,3,0);
-	vcdp->declBus  (c+214,"cache_simX dmem_controller dcache genblk1[0] choose_thread mask",-1,3,0);
-	vcdp->declBus  (c+215,"cache_simX dmem_controller dcache genblk1[0] choose_thread index",-1,1,0);
-	vcdp->declBit  (c+216,"cache_simX dmem_controller dcache genblk1[0] choose_thread found",-1);
-	vcdp->declBus  (c+217,"cache_simX dmem_controller dcache genblk1[0] choose_thread i",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk1[1] choose_thread N",-1,31,0);
+	vcdp->declBus  (c+222,"cache_simX dmem_controller dcache genblk1[0] choose_thread mask",-1,3,0);
+	vcdp->declBus  (c+223,"cache_simX dmem_controller dcache genblk1[0] choose_thread index",-1,1,0);
+	vcdp->declBit  (c+224,"cache_simX dmem_controller dcache genblk1[0] choose_thread found",-1);
+	vcdp->declBus  (c+225,"cache_simX dmem_controller dcache genblk1[0] choose_thread i",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk1[1] choose_thread N",-1,31,0);
 	vcdp->declBus  (c+181,"cache_simX dmem_controller dcache genblk1[1] choose_thread valids",-1,3,0);
-	vcdp->declBus  (c+218,"cache_simX dmem_controller dcache genblk1[1] choose_thread mask",-1,3,0);
-	vcdp->declBus  (c+219,"cache_simX dmem_controller dcache genblk1[1] choose_thread index",-1,1,0);
-	vcdp->declBit  (c+220,"cache_simX dmem_controller dcache genblk1[1] choose_thread found",-1);
-	vcdp->declBus  (c+221,"cache_simX dmem_controller dcache genblk1[1] choose_thread i",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk1[2] choose_thread N",-1,31,0);
+	vcdp->declBus  (c+226,"cache_simX dmem_controller dcache genblk1[1] choose_thread mask",-1,3,0);
+	vcdp->declBus  (c+227,"cache_simX dmem_controller dcache genblk1[1] choose_thread index",-1,1,0);
+	vcdp->declBit  (c+228,"cache_simX dmem_controller dcache genblk1[1] choose_thread found",-1);
+	vcdp->declBus  (c+229,"cache_simX dmem_controller dcache genblk1[1] choose_thread i",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk1[2] choose_thread N",-1,31,0);
 	vcdp->declBus  (c+185,"cache_simX dmem_controller dcache genblk1[2] choose_thread valids",-1,3,0);
-	vcdp->declBus  (c+222,"cache_simX dmem_controller dcache genblk1[2] choose_thread mask",-1,3,0);
-	vcdp->declBus  (c+223,"cache_simX dmem_controller dcache genblk1[2] choose_thread index",-1,1,0);
-	vcdp->declBit  (c+224,"cache_simX dmem_controller dcache genblk1[2] choose_thread found",-1);
-	vcdp->declBus  (c+225,"cache_simX dmem_controller dcache genblk1[2] choose_thread i",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk1[3] choose_thread N",-1,31,0);
+	vcdp->declBus  (c+230,"cache_simX dmem_controller dcache genblk1[2] choose_thread mask",-1,3,0);
+	vcdp->declBus  (c+231,"cache_simX dmem_controller dcache genblk1[2] choose_thread index",-1,1,0);
+	vcdp->declBit  (c+232,"cache_simX dmem_controller dcache genblk1[2] choose_thread found",-1);
+	vcdp->declBus  (c+233,"cache_simX dmem_controller dcache genblk1[2] choose_thread i",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk1[3] choose_thread N",-1,31,0);
 	vcdp->declBus  (c+189,"cache_simX dmem_controller dcache genblk1[3] choose_thread valids",-1,3,0);
-	vcdp->declBus  (c+226,"cache_simX dmem_controller dcache genblk1[3] choose_thread mask",-1,3,0);
-	vcdp->declBus  (c+227,"cache_simX dmem_controller dcache genblk1[3] choose_thread index",-1,1,0);
-	vcdp->declBit  (c+228,"cache_simX dmem_controller dcache genblk1[3] choose_thread found",-1);
-	vcdp->declBus  (c+229,"cache_simX dmem_controller dcache genblk1[3] choose_thread i",-1,31,0);
-	vcdp->declBus  (c+3127,"cache_simX dmem_controller icache CACHE_SIZE",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller icache CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3089,"cache_simX dmem_controller icache CACHE_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache CACHE_BANKS",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache LOG_NUM_BANKS",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache LOG_NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller icache NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache OFFSET_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache OFFSET_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3128,"cache_simX dmem_controller icache TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache IND_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3129,"cache_simX dmem_controller icache ADDR_TAG_START",-1,31,0);
-	vcdp->declBus  (c+3104,"cache_simX dmem_controller icache ADDR_TAG_END",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller icache ADDR_OFFSET_START",-1,31,0);
-	vcdp->declBus  (c+3092,"cache_simX dmem_controller icache ADDR_OFFSET_END",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache ADDR_IND_START",-1,31,0);
-	vcdp->declBus  (c+3130,"cache_simX dmem_controller icache ADDR_IND_END",-1,31,0);
-	vcdp->declBus  (c+3131,"cache_simX dmem_controller icache MEM_ADDR_REQ_MASK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller icache RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller icache clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller icache rst",-1);
-	vcdp->declBus  (c+3066,"cache_simX dmem_controller icache i_p_valid",-1,0,0);
-	vcdp->declBus  (c+3065,"cache_simX dmem_controller icache i_p_addr",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache i_p_writedata",-1,31,0);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller icache i_p_read_or_write",-1);
-	vcdp->declBus  (c+584,"cache_simX dmem_controller icache o_p_readdata",-1,31,0);
-	vcdp->declBit  (c+585,"cache_simX dmem_controller icache o_p_delay",-1);
-	vcdp->declBus  (c+230,"cache_simX dmem_controller icache o_m_evict_addr",-1,31,0);
-	vcdp->declBus  (c+726,"cache_simX dmem_controller icache o_m_read_addr",-1,31,0);
-	vcdp->declBit  (c+727,"cache_simX dmem_controller icache o_m_valid",-1);
-	vcdp->declArray(c+606,"cache_simX dmem_controller icache o_m_writedata",-1,127,0);
-	vcdp->declBit  (c+610,"cache_simX dmem_controller icache o_m_read_or_write",-1);
-	vcdp->declArray(c+3132,"cache_simX dmem_controller icache i_m_readdata",-1,127,0);
-	vcdp->declBit  (c+708,"cache_simX dmem_controller icache i_m_ready",-1);
+	vcdp->declBus  (c+234,"cache_simX dmem_controller dcache genblk1[3] choose_thread mask",-1,3,0);
+	vcdp->declBus  (c+235,"cache_simX dmem_controller dcache genblk1[3] choose_thread index",-1,1,0);
+	vcdp->declBit  (c+236,"cache_simX dmem_controller dcache genblk1[3] choose_thread found",-1);
+	vcdp->declBus  (c+237,"cache_simX dmem_controller dcache genblk1[3] choose_thread i",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller icache CACHE_SIZE",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4840,"cache_simX dmem_controller icache CACHE_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache CACHE_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache LOG_NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache OFFSET_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache OFFSET_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache IND_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4844,"cache_simX dmem_controller icache ADDR_TAG_START",-1,31,0);
+	vcdp->declBus  (c+4845,"cache_simX dmem_controller icache ADDR_TAG_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache ADDR_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4834,"cache_simX dmem_controller icache ADDR_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller icache ADDR_IND_START",-1,31,0);
+	vcdp->declBus  (c+4846,"cache_simX dmem_controller icache ADDR_IND_END",-1,31,0);
+	vcdp->declBus  (c+4847,"cache_simX dmem_controller icache MEM_ADDR_REQ_MASK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache rst",-1);
+	vcdp->declBus  (c+4807,"cache_simX dmem_controller icache i_p_valid",-1,0,0);
+	vcdp->declBus  (c+4806,"cache_simX dmem_controller icache i_p_addr",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache i_p_writedata",-1,31,0);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache i_p_read_or_write",-1);
+	vcdp->declBus  (c+1034,"cache_simX dmem_controller icache o_p_readdata",-1,31,0);
+	vcdp->declBit  (c+1035,"cache_simX dmem_controller icache o_p_delay",-1);
+	vcdp->declBus  (c+238,"cache_simX dmem_controller icache o_m_evict_addr",-1,31,0);
+	vcdp->declBus  (c+1181,"cache_simX dmem_controller icache o_m_read_addr",-1,31,0);
+	vcdp->declBit  (c+1182,"cache_simX dmem_controller icache o_m_valid",-1);
+	vcdp->declArray(c+239,"cache_simX dmem_controller icache o_m_writedata",-1,511,0);
+	vcdp->declBit  (c+1056,"cache_simX dmem_controller icache o_m_read_or_write",-1);
+	vcdp->declArray(c+4866,"cache_simX dmem_controller icache i_m_readdata",-1,511,0);
+	vcdp->declBit  (c+1163,"cache_simX dmem_controller icache i_m_ready",-1);
 	vcdp->declBus  (c+23,"cache_simX dmem_controller icache i_p_mem_read",-1,2,0);
-	vcdp->declBus  (c+3084,"cache_simX dmem_controller icache i_p_mem_write",-1,2,0);
-	vcdp->declBus  (c+728,"cache_simX dmem_controller icache final_data_read",-1,31,0);
-	vcdp->declBus  (c+231,"cache_simX dmem_controller icache new_final_data_read",-1,31,0);
-	vcdp->declBus  (c+584,"cache_simX dmem_controller icache new_final_data_read_Qual",-1,31,0);
-	vcdp->declBus  (c+729,"cache_simX dmem_controller icache global_way_to_evict",-1,0,0);
-	vcdp->declBus  (c+232,"cache_simX dmem_controller icache thread_track_banks",-1,0,0);
-	vcdp->declBus  (c+233,"cache_simX dmem_controller icache index_per_bank",-1,0,0);
-	vcdp->declBus  (c+234,"cache_simX dmem_controller icache use_mask_per_bank",-1,0,0);
-	vcdp->declBus  (c+235,"cache_simX dmem_controller icache valid_per_bank",-1,0,0);
-	vcdp->declBus  (c+236,"cache_simX dmem_controller icache threads_serviced_per_bank",-1,0,0);
-	vcdp->declBus  (c+237,"cache_simX dmem_controller icache readdata_per_bank",-1,31,0);
-	vcdp->declBus  (c+238,"cache_simX dmem_controller icache hit_per_bank",-1,0,0);
-	vcdp->declBus  (c+611,"cache_simX dmem_controller icache eviction_wb",-1,0,0);
-	vcdp->declBus  (c+3136,"cache_simX dmem_controller icache eviction_wb_old",-1,0,0);
-	vcdp->declBus  (c+730,"cache_simX dmem_controller icache state",-1,3,0);
-	vcdp->declBus  (c+239,"cache_simX dmem_controller icache new_state",-1,3,0);
-	vcdp->declBus  (c+240,"cache_simX dmem_controller icache use_valid",-1,0,0);
-	vcdp->declBus  (c+731,"cache_simX dmem_controller icache stored_valid",-1,0,0);
-	vcdp->declBus  (c+241,"cache_simX dmem_controller icache new_stored_valid",-1,0,0);
-	vcdp->declBus  (c+242,"cache_simX dmem_controller icache eviction_addr_per_bank",-1,31,0);
-	vcdp->declBus  (c+732,"cache_simX dmem_controller icache miss_addr",-1,31,0);
-	vcdp->declBit  (c+3066,"cache_simX dmem_controller icache curr_processor_request_valid",-1);
-	vcdp->declBus  (c+243,"cache_simX dmem_controller icache threads_serviced_Qual",-1,0,0);
-	{int i; for (i=0; i<1; i++) {
-		vcdp->declBus  (c+244+i*1,"cache_simX dmem_controller icache debug_hit_per_bank_mask",(i+0),0,0);}}
+	vcdp->declBus  (c+4825,"cache_simX dmem_controller icache i_p_mem_write",-1,2,0);
+	vcdp->declBus  (c+1183,"cache_simX dmem_controller icache final_data_read",-1,31,0);
+	vcdp->declBus  (c+255,"cache_simX dmem_controller icache new_final_data_read",-1,31,0);
+	vcdp->declBus  (c+1034,"cache_simX dmem_controller icache new_final_data_read_Qual",-1,31,0);
+	vcdp->declBus  (c+1184,"cache_simX dmem_controller icache global_way_to_evict",-1,0,0);
+	vcdp->declBus  (c+256,"cache_simX dmem_controller icache thread_track_banks",-1,3,0);
+	vcdp->declBus  (c+257,"cache_simX dmem_controller icache index_per_bank",-1,3,0);
+	vcdp->declBus  (c+258,"cache_simX dmem_controller icache use_mask_per_bank",-1,3,0);
+	vcdp->declBus  (c+259,"cache_simX dmem_controller icache valid_per_bank",-1,3,0);
+	vcdp->declBus  (c+260,"cache_simX dmem_controller icache threads_serviced_per_bank",-1,3,0);
+	vcdp->declArray(c+261,"cache_simX dmem_controller icache readdata_per_bank",-1,127,0);
+	vcdp->declBus  (c+265,"cache_simX dmem_controller icache hit_per_bank",-1,3,0);
+	vcdp->declBus  (c+266,"cache_simX dmem_controller icache eviction_wb",-1,3,0);
+	vcdp->declBus  (c+4882,"cache_simX dmem_controller icache eviction_wb_old",-1,3,0);
+	vcdp->declBus  (c+1185,"cache_simX dmem_controller icache state",-1,3,0);
+	vcdp->declBus  (c+267,"cache_simX dmem_controller icache new_state",-1,3,0);
+	vcdp->declBus  (c+268,"cache_simX dmem_controller icache use_valid",-1,0,0);
+	vcdp->declBus  (c+1186,"cache_simX dmem_controller icache stored_valid",-1,0,0);
+	vcdp->declBus  (c+269,"cache_simX dmem_controller icache new_stored_valid",-1,0,0);
+	vcdp->declArray(c+270,"cache_simX dmem_controller icache eviction_addr_per_bank",-1,127,0);
+	vcdp->declBus  (c+1187,"cache_simX dmem_controller icache miss_addr",-1,31,0);
+	vcdp->declBit  (c+4807,"cache_simX dmem_controller icache curr_processor_request_valid",-1);
+	vcdp->declBus  (c+274,"cache_simX dmem_controller icache threads_serviced_Qual",-1,0,0);
+	{int i; for (i=0; i<4; i++) {
+		vcdp->declBus  (c+275+i*1,"cache_simX dmem_controller icache debug_hit_per_bank_mask",(i+0),0,0);}}
 	// Tracing: cache_simX dmem_controller icache bid // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:163
-	vcdp->declBus  (c+3137,"cache_simX dmem_controller icache test_bid",-1,31,0);
-	vcdp->declBus  (c+245,"cache_simX dmem_controller icache detect_bank_miss",-1,0,0);
-	vcdp->declBus  (c+3137,"cache_simX dmem_controller icache bbid",-1,31,0);
+	vcdp->declBus  (c+4837,"cache_simX dmem_controller icache test_bid",-1,31,0);
+	vcdp->declBus  (c+279,"cache_simX dmem_controller icache detect_bank_miss",-1,3,0);
+	vcdp->declBus  (c+4837,"cache_simX dmem_controller icache bbid",-1,31,0);
 	// Tracing: cache_simX dmem_controller icache tid // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:209
-	vcdp->declBit  (c+585,"cache_simX dmem_controller icache delay",-1);
-	vcdp->declBus  (c+233,"cache_simX dmem_controller icache send_index_to_bank",-1,0,0);
-	vcdp->declBus  (c+246,"cache_simX dmem_controller icache miss_bank_index",-1,0,0);
-	vcdp->declBit  (c+247,"cache_simX dmem_controller icache miss_found",-1);
-	vcdp->declBit  (c+612,"cache_simX dmem_controller icache update_global_way_to_evict",-1);
+	vcdp->declBit  (c+1035,"cache_simX dmem_controller icache delay",-1);
+	vcdp->declBus  (c+257,"cache_simX dmem_controller icache send_index_to_bank",-1,3,0);
+	vcdp->declBus  (c+280,"cache_simX dmem_controller icache miss_bank_index",-1,1,0);
+	vcdp->declBit  (c+281,"cache_simX dmem_controller icache miss_found",-1);
+	vcdp->declBit  (c+1057,"cache_simX dmem_controller icache update_global_way_to_evict",-1);
 	// Tracing: cache_simX dmem_controller icache cur_t // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:249
-	vcdp->declBus  (c+3138,"cache_simX dmem_controller icache init_b",-1,31,0);
+	vcdp->declBus  (c+4883,"cache_simX dmem_controller icache init_b",-1,31,0);
 	// Tracing: cache_simX dmem_controller icache bank_id // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:294
-	vcdp->declBus  (c+232,"cache_simX dmem_controller icache genblk1[0] use_threads_track_banks",-1,0,0);
-	vcdp->declBus  (c+233,"cache_simX dmem_controller icache genblk1[0] use_thread_index",-1,0,0);
-	vcdp->declBit  (c+248,"cache_simX dmem_controller icache genblk1[0] use_write_final_data",-1);
-	vcdp->declBus  (c+237,"cache_simX dmem_controller icache genblk1[0] use_data_final_data",-1,31,0);
-	vcdp->declBus  (c+249,"cache_simX dmem_controller icache genblk3[0] bank_addr",-1,31,0);
-	vcdp->declBus  (c+250,"cache_simX dmem_controller icache genblk3[0] byte_select",-1,1,0);
-	vcdp->declBus  (c+251,"cache_simX dmem_controller icache genblk3[0] cache_tag",-1,22,0);
-	vcdp->declBus  (c+3125,"cache_simX dmem_controller icache genblk3[0] cache_offset",-1,1,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller icache genblk3[0] cache_index",-1,4,0);
-	vcdp->declBit  (c+252,"cache_simX dmem_controller icache genblk3[0] normal_valid_in",-1);
-	vcdp->declBit  (c+253,"cache_simX dmem_controller icache genblk3[0] use_valid_in",-1);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache multip_banks NUMBER_BANKS",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache multip_banks LOG_NUM_BANKS",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache multip_banks NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+240,"cache_simX dmem_controller icache multip_banks i_p_valid",-1,0,0);
-	vcdp->declBus  (c+3065,"cache_simX dmem_controller icache multip_banks i_p_addr",-1,31,0);
-	vcdp->declBus  (c+232,"cache_simX dmem_controller icache multip_banks thread_track_banks",-1,0,0);
-	vcdp->declBus  (c+3137,"cache_simX dmem_controller icache multip_banks t_id",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache get_miss_index N",-1,31,0);
-	vcdp->declBus  (c+245,"cache_simX dmem_controller icache get_miss_index valids",-1,0,0);
-	vcdp->declBus  (c+246,"cache_simX dmem_controller icache get_miss_index index",-1,0,0);
-	vcdp->declBit  (c+247,"cache_simX dmem_controller icache get_miss_index found",-1);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller icache get_miss_index i",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache genblk1[0] choose_thread N",-1,31,0);
-	vcdp->declBus  (c+232,"cache_simX dmem_controller icache genblk1[0] choose_thread valids",-1,0,0);
-	vcdp->declBus  (c+234,"cache_simX dmem_controller icache genblk1[0] choose_thread mask",-1,0,0);
-	vcdp->declBus  (c+233,"cache_simX dmem_controller icache genblk1[0] choose_thread index",-1,0,0);
-	vcdp->declBit  (c+235,"cache_simX dmem_controller icache genblk1[0] choose_thread found",-1);
-	vcdp->declBus  (c+3137,"cache_simX dmem_controller icache genblk1[0] choose_thread i",-1,31,0);
-	vcdp->declBus  (c+3127,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_SIZE",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3089,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_BANKS",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure LOG_NUM_BANKS",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure LOG_NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure OFFSET_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure OFFSET_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3128,"cache_simX dmem_controller icache genblk3[0] bank_structure TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure IND_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3129,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_TAG_START",-1,31,0);
-	vcdp->declBus  (c+3104,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_TAG_END",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_OFFSET_START",-1,31,0);
-	vcdp->declBus  (c+3092,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_OFFSET_END",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_IND_START",-1,31,0);
-	vcdp->declBus  (c+3130,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_IND_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure BLOCK_NUM_BITS",-1,31,0);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller icache genblk3[0] bank_structure rst",-1);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller icache genblk3[0] bank_structure clk",-1);
-	vcdp->declBus  (c+730,"cache_simX dmem_controller icache genblk3[0] bank_structure state",-1,3,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller icache genblk3[0] bank_structure actual_index",-1,4,0);
-	vcdp->declBus  (c+251,"cache_simX dmem_controller icache genblk3[0] bank_structure o_tag",-1,22,0);
-	vcdp->declBus  (c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure block_offset",-1,1,0);
-	vcdp->declBus  (c+254,"cache_simX dmem_controller icache genblk3[0] bank_structure writedata",-1,31,0);
-	vcdp->declBit  (c+253,"cache_simX dmem_controller icache genblk3[0] bank_structure valid_in",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure read_or_write",-1);
-	vcdp->declArray(c+3132,"cache_simX dmem_controller icache genblk3[0] bank_structure fetched_writedata",-1,127,0);
-	vcdp->declBus  (c+23,"cache_simX dmem_controller icache genblk3[0] bank_structure i_p_mem_read",-1,2,0);
-	vcdp->declBus  (c+3084,"cache_simX dmem_controller icache genblk3[0] bank_structure i_p_mem_write",-1,2,0);
-	vcdp->declBus  (c+250,"cache_simX dmem_controller icache genblk3[0] bank_structure byte_select",-1,1,0);
-	vcdp->declBus  (c+729,"cache_simX dmem_controller icache genblk3[0] bank_structure evicted_way",-1,0,0);
-	vcdp->declBus  (c+237,"cache_simX dmem_controller icache genblk3[0] bank_structure readdata",-1,31,0);
-	vcdp->declBit  (c+238,"cache_simX dmem_controller icache genblk3[0] bank_structure hit",-1);
-	vcdp->declBit  (c+611,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_wb",-1);
-	vcdp->declBus  (c+242,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_addr",-1,31,0);
-	vcdp->declArray(c+606,"cache_simX dmem_controller icache genblk3[0] bank_structure data_evicted",-1,127,0);
-	vcdp->declArray(c+606,"cache_simX dmem_controller icache genblk3[0] bank_structure data_use",-1,127,0);
-	vcdp->declBus  (c+255,"cache_simX dmem_controller icache genblk3[0] bank_structure tag_use",-1,22,0);
-	vcdp->declBus  (c+255,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_tag",-1,22,0);
-	vcdp->declBit  (c+256,"cache_simX dmem_controller icache genblk3[0] bank_structure valid_use",-1);
-	vcdp->declBit  (c+611,"cache_simX dmem_controller icache genblk3[0] bank_structure dirty_use",-1);
-	vcdp->declBit  (c+257,"cache_simX dmem_controller icache genblk3[0] bank_structure access",-1);
-	vcdp->declBit  (c+258,"cache_simX dmem_controller icache genblk3[0] bank_structure write_from_mem",-1);
-	vcdp->declBit  (c+259,"cache_simX dmem_controller icache genblk3[0] bank_structure miss",-1);
-	vcdp->declBus  (c+628,"cache_simX dmem_controller icache genblk3[0] bank_structure way_to_update",-1,0,0);
-	vcdp->declBit  (c+260,"cache_simX dmem_controller icache genblk3[0] bank_structure lw",-1);
-	vcdp->declBit  (c+261,"cache_simX dmem_controller icache genblk3[0] bank_structure lb",-1);
-	vcdp->declBit  (c+262,"cache_simX dmem_controller icache genblk3[0] bank_structure lh",-1);
-	vcdp->declBit  (c+263,"cache_simX dmem_controller icache genblk3[0] bank_structure lhu",-1);
-	vcdp->declBit  (c+264,"cache_simX dmem_controller icache genblk3[0] bank_structure lbu",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure sw",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure sb",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure sh",-1);
-	vcdp->declBit  (c+265,"cache_simX dmem_controller icache genblk3[0] bank_structure b0",-1);
-	vcdp->declBit  (c+266,"cache_simX dmem_controller icache genblk3[0] bank_structure b1",-1);
-	vcdp->declBit  (c+267,"cache_simX dmem_controller icache genblk3[0] bank_structure b2",-1);
-	vcdp->declBit  (c+268,"cache_simX dmem_controller icache genblk3[0] bank_structure b3",-1);
-	vcdp->declBus  (c+269,"cache_simX dmem_controller icache genblk3[0] bank_structure data_unQual",-1,31,0);
-	vcdp->declBus  (c+270,"cache_simX dmem_controller icache genblk3[0] bank_structure lb_data",-1,31,0);
-	vcdp->declBus  (c+271,"cache_simX dmem_controller icache genblk3[0] bank_structure lh_data",-1,31,0);
-	vcdp->declBus  (c+272,"cache_simX dmem_controller icache genblk3[0] bank_structure lbu_data",-1,31,0);
-	vcdp->declBus  (c+273,"cache_simX dmem_controller icache genblk3[0] bank_structure lhu_data",-1,31,0);
-	vcdp->declBus  (c+269,"cache_simX dmem_controller icache genblk3[0] bank_structure lw_data",-1,31,0);
-	vcdp->declBus  (c+254,"cache_simX dmem_controller icache genblk3[0] bank_structure sw_data",-1,31,0);
-	vcdp->declBus  (c+274,"cache_simX dmem_controller icache genblk3[0] bank_structure sb_data",-1,31,0);
-	vcdp->declBus  (c+275,"cache_simX dmem_controller icache genblk3[0] bank_structure sh_data",-1,31,0);
-	vcdp->declBus  (c+254,"cache_simX dmem_controller icache genblk3[0] bank_structure use_write_data",-1,31,0);
-	vcdp->declBus  (c+276,"cache_simX dmem_controller icache genblk3[0] bank_structure data_Qual",-1,31,0);
-	vcdp->declBus  (c+277,"cache_simX dmem_controller icache genblk3[0] bank_structure sb_mask",-1,3,0);
-	vcdp->declBus  (c+278,"cache_simX dmem_controller icache genblk3[0] bank_structure sh_mask",-1,3,0);
-	vcdp->declBus  (c+279,"cache_simX dmem_controller icache genblk3[0] bank_structure we",-1,15,0);
-	vcdp->declArray(c+280,"cache_simX dmem_controller icache genblk3[0] bank_structure data_write",-1,127,0);
-	// Tracing: cache_simX dmem_controller icache genblk3[0] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[0] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[1] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[2] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[3] normal_write",-1);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3128,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures rst",-1);
-	vcdp->declBit  (c+253,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_in",-1);
-	vcdp->declBus  (c+730,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures state",-1,3,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures addr",-1,4,0);
-	vcdp->declBus  (c+279,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures we",-1,15,0);
-	vcdp->declBit  (c+258,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures evict",-1);
-	vcdp->declBus  (c+628,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_to_update",-1,0,0);
-	vcdp->declArray(c+280,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+251,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_write",-1,22,0);
-	vcdp->declBus  (c+255,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_use",-1,22,0);
-	vcdp->declArray(c+606,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+256,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_use",-1);
-	vcdp->declBit  (c+611,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures dirty_use",-1);
-	vcdp->declQuad (c+629,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_use_per_way",-1,45,0);
-	vcdp->declArray(c+631,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_use_per_way",-1,255,0);
-	vcdp->declBus  (c+639,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_use_per_way",-1,1,0);
-	vcdp->declBus  (c+640,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures dirty_use_per_way",-1,1,0);
-	vcdp->declBus  (c+284,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures hit_per_way",-1,1,0);
-	vcdp->declBus  (c+285,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures we_per_way",-1,31,0);
-	vcdp->declArray(c+286,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_write_per_way",-1,255,0);
-	vcdp->declBus  (c+294,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures write_from_mem_per_way",-1,1,0);
-	vcdp->declBit  (c+641,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures invalid_found",-1);
-	vcdp->declBus  (c+295,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_index",-1,0,0);
-	vcdp->declBus  (c+642,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures invalid_index",-1,0,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBus  (c+296,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_use_Qual",-1,0,0);
-	// Tracing: cache_simX dmem_controller icache genblk3[0] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index N",-1,31,0);
-	vcdp->declBus  (c+643,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
-	vcdp->declBus  (c+642,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index index",-1,0,0);
-	vcdp->declBit  (c+641,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index found",-1);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index i",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
-	vcdp->declBus  (c+284,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
-	vcdp->declBus  (c+295,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
-	vcdp->declBit  (c+297,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing found",-1);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3128,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures rst",-1);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
-	vcdp->declBus  (c+298,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
-	vcdp->declBit  (c+299,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures evict",-1);
-	vcdp->declArray(c+300,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+251,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_write",-1,22,0);
-	vcdp->declBus  (c+733,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_use",-1,22,0);
-	vcdp->declArray(c+734,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+738,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures valid_use",-1);
-	vcdp->declBit  (c+739,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
-	vcdp->declBit  (c+304,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
-	vcdp->declBit  (c+613,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
-	vcdp->declBit  (c+305,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
-	vcdp->declArray(c+740,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
-	vcdp->declArray(c+744,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
-	vcdp->declArray(c+748,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
-	vcdp->declArray(c+752,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
-	vcdp->declArray(c+756,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
-	vcdp->declArray(c+760,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
-	vcdp->declArray(c+764,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
-	vcdp->declArray(c+768,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
-	vcdp->declArray(c+772,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
-	vcdp->declArray(c+776,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
-	vcdp->declArray(c+780,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
-	vcdp->declArray(c+784,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
-	vcdp->declArray(c+788,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
-	vcdp->declArray(c+792,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
-	vcdp->declArray(c+796,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
-	vcdp->declArray(c+800,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
-	vcdp->declArray(c+804,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
-	vcdp->declArray(c+808,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
-	vcdp->declArray(c+812,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
-	vcdp->declArray(c+816,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
-	vcdp->declArray(c+820,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
-	vcdp->declArray(c+824,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
-	vcdp->declArray(c+828,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
-	vcdp->declArray(c+832,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
-	vcdp->declArray(c+836,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
-	vcdp->declArray(c+840,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
-	vcdp->declArray(c+844,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
-	vcdp->declArray(c+848,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
-	vcdp->declArray(c+852,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
-	vcdp->declArray(c+856,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
-	vcdp->declArray(c+860,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
-	vcdp->declArray(c+864,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
-	{int i; for (i=0; i<32; i++) {
-		vcdp->declBus  (c+868+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag",(i+0),22,0);}}
-	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+900+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
-	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+932+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
-	vcdp->declBus  (c+964,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
-	vcdp->declBus  (c+965,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3128,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures rst",-1);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
-	vcdp->declBus  (c+306,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
-	vcdp->declBit  (c+307,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures evict",-1);
-	vcdp->declArray(c+308,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+251,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_write",-1,22,0);
-	vcdp->declBus  (c+966,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_use",-1,22,0);
-	vcdp->declArray(c+967,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+971,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures valid_use",-1);
-	vcdp->declBit  (c+972,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
-	vcdp->declBit  (c+312,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
-	vcdp->declBit  (c+614,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
-	vcdp->declBit  (c+313,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
-	vcdp->declArray(c+973,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
-	vcdp->declArray(c+977,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
-	vcdp->declArray(c+981,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
-	vcdp->declArray(c+985,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
-	vcdp->declArray(c+989,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
-	vcdp->declArray(c+993,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
-	vcdp->declArray(c+997,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
-	vcdp->declArray(c+1001,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
-	vcdp->declArray(c+1005,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
-	vcdp->declArray(c+1009,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
-	vcdp->declArray(c+1013,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
-	vcdp->declArray(c+1017,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
-	vcdp->declArray(c+1021,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
-	vcdp->declArray(c+1025,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
-	vcdp->declArray(c+1029,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
-	vcdp->declArray(c+1033,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
-	vcdp->declArray(c+1037,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
-	vcdp->declArray(c+1041,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
-	vcdp->declArray(c+1045,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
-	vcdp->declArray(c+1049,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
-	vcdp->declArray(c+1053,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
-	vcdp->declArray(c+1057,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
-	vcdp->declArray(c+1061,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
-	vcdp->declArray(c+1065,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
-	vcdp->declArray(c+1069,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
-	vcdp->declArray(c+1073,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
-	vcdp->declArray(c+1077,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
-	vcdp->declArray(c+1081,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
-	vcdp->declArray(c+1085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
-	vcdp->declArray(c+1089,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
-	vcdp->declArray(c+1093,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
-	vcdp->declArray(c+1097,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
-	{int i; for (i=0; i<32; i++) {
-		vcdp->declBus  (c+1101+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag",(i+0),22,0);}}
-	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+1133+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
-	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+1165+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
-	vcdp->declBus  (c+1197,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
-	vcdp->declBus  (c+1198,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
-	vcdp->declBus  (c+3065,"cache_simX VX_icache_req pc_address",-1,31,0);
-	vcdp->declBus  (c+3079,"cache_simX VX_icache_req out_cache_driver_in_mem_read",-1,2,0);
-	vcdp->declBus  (c+3084,"cache_simX VX_icache_req out_cache_driver_in_mem_write",-1,2,0);
-	vcdp->declBit  (c+3066,"cache_simX VX_icache_req out_cache_driver_in_valid",-1);
-	vcdp->declBus  (c+3085,"cache_simX VX_icache_req out_cache_driver_in_data",-1,31,0);
-	vcdp->declBus  (c+584,"cache_simX VX_icache_rsp instruction",-1,31,0);
-	vcdp->declBit  (c+585,"cache_simX VX_icache_rsp delay",-1);
-	vcdp->declBus  (c+3088,"cache_simX VX_dram_req_rsp NUMBER_BANKS",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX VX_dram_req_rsp NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+282,"cache_simX dmem_controller icache genblk1[0] use_threads_track_banks",-1,0,0);
+	vcdp->declBus  (c+283,"cache_simX dmem_controller icache genblk1[0] use_thread_index",-1,0,0);
+	vcdp->declBit  (c+284,"cache_simX dmem_controller icache genblk1[0] use_write_final_data",-1);
+	vcdp->declBus  (c+285,"cache_simX dmem_controller icache genblk1[0] use_data_final_data",-1,31,0);
+	vcdp->declBus  (c+286,"cache_simX dmem_controller icache genblk1[1] use_threads_track_banks",-1,0,0);
+	vcdp->declBus  (c+287,"cache_simX dmem_controller icache genblk1[1] use_thread_index",-1,0,0);
+	vcdp->declBit  (c+288,"cache_simX dmem_controller icache genblk1[1] use_write_final_data",-1);
+	vcdp->declBus  (c+289,"cache_simX dmem_controller icache genblk1[1] use_data_final_data",-1,31,0);
+	vcdp->declBus  (c+290,"cache_simX dmem_controller icache genblk1[2] use_threads_track_banks",-1,0,0);
+	vcdp->declBus  (c+291,"cache_simX dmem_controller icache genblk1[2] use_thread_index",-1,0,0);
+	vcdp->declBit  (c+292,"cache_simX dmem_controller icache genblk1[2] use_write_final_data",-1);
+	vcdp->declBus  (c+293,"cache_simX dmem_controller icache genblk1[2] use_data_final_data",-1,31,0);
+	vcdp->declBus  (c+294,"cache_simX dmem_controller icache genblk1[3] use_threads_track_banks",-1,0,0);
+	vcdp->declBus  (c+295,"cache_simX dmem_controller icache genblk1[3] use_thread_index",-1,0,0);
+	vcdp->declBit  (c+296,"cache_simX dmem_controller icache genblk1[3] use_write_final_data",-1);
+	vcdp->declBus  (c+297,"cache_simX dmem_controller icache genblk1[3] use_data_final_data",-1,31,0);
+	vcdp->declBus  (c+298,"cache_simX dmem_controller icache genblk3[0] bank_addr",-1,31,0);
+	vcdp->declBus  (c+299,"cache_simX dmem_controller icache genblk3[0] byte_select",-1,1,0);
+	vcdp->declBus  (c+300,"cache_simX dmem_controller icache genblk3[0] cache_tag",-1,20,0);
+	vcdp->declBus  (c+301,"cache_simX dmem_controller icache genblk3[0] cache_offset",-1,1,0);
+	vcdp->declBus  (c+302,"cache_simX dmem_controller icache genblk3[0] cache_index",-1,4,0);
+	vcdp->declBit  (c+303,"cache_simX dmem_controller icache genblk3[0] normal_valid_in",-1);
+	vcdp->declBit  (c+304,"cache_simX dmem_controller icache genblk3[0] use_valid_in",-1);
+	vcdp->declBus  (c+305,"cache_simX dmem_controller icache genblk3[1] bank_addr",-1,31,0);
+	vcdp->declBus  (c+306,"cache_simX dmem_controller icache genblk3[1] byte_select",-1,1,0);
+	vcdp->declBus  (c+307,"cache_simX dmem_controller icache genblk3[1] cache_tag",-1,20,0);
+	vcdp->declBus  (c+308,"cache_simX dmem_controller icache genblk3[1] cache_offset",-1,1,0);
+	vcdp->declBus  (c+309,"cache_simX dmem_controller icache genblk3[1] cache_index",-1,4,0);
+	vcdp->declBit  (c+310,"cache_simX dmem_controller icache genblk3[1] normal_valid_in",-1);
+	vcdp->declBit  (c+311,"cache_simX dmem_controller icache genblk3[1] use_valid_in",-1);
+	vcdp->declBus  (c+312,"cache_simX dmem_controller icache genblk3[2] bank_addr",-1,31,0);
+	vcdp->declBus  (c+313,"cache_simX dmem_controller icache genblk3[2] byte_select",-1,1,0);
+	vcdp->declBus  (c+314,"cache_simX dmem_controller icache genblk3[2] cache_tag",-1,20,0);
+	vcdp->declBus  (c+315,"cache_simX dmem_controller icache genblk3[2] cache_offset",-1,1,0);
+	vcdp->declBus  (c+316,"cache_simX dmem_controller icache genblk3[2] cache_index",-1,4,0);
+	vcdp->declBit  (c+317,"cache_simX dmem_controller icache genblk3[2] normal_valid_in",-1);
+	vcdp->declBit  (c+318,"cache_simX dmem_controller icache genblk3[2] use_valid_in",-1);
+	vcdp->declBus  (c+319,"cache_simX dmem_controller icache genblk3[3] bank_addr",-1,31,0);
+	vcdp->declBus  (c+320,"cache_simX dmem_controller icache genblk3[3] byte_select",-1,1,0);
+	vcdp->declBus  (c+321,"cache_simX dmem_controller icache genblk3[3] cache_tag",-1,20,0);
+	vcdp->declBus  (c+322,"cache_simX dmem_controller icache genblk3[3] cache_offset",-1,1,0);
+	vcdp->declBus  (c+323,"cache_simX dmem_controller icache genblk3[3] cache_index",-1,4,0);
+	vcdp->declBit  (c+324,"cache_simX dmem_controller icache genblk3[3] normal_valid_in",-1);
+	vcdp->declBit  (c+325,"cache_simX dmem_controller icache genblk3[3] use_valid_in",-1);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache multip_banks NUMBER_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache multip_banks LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache multip_banks NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+268,"cache_simX dmem_controller icache multip_banks i_p_valid",-1,0,0);
+	vcdp->declBus  (c+4806,"cache_simX dmem_controller icache multip_banks i_p_addr",-1,31,0);
+	vcdp->declBus  (c+256,"cache_simX dmem_controller icache multip_banks thread_track_banks",-1,3,0);
+	vcdp->declBus  (c+4884,"cache_simX dmem_controller icache multip_banks t_id",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache get_miss_index N",-1,31,0);
+	vcdp->declBus  (c+279,"cache_simX dmem_controller icache get_miss_index valids",-1,3,0);
+	vcdp->declBus  (c+280,"cache_simX dmem_controller icache get_miss_index index",-1,1,0);
+	vcdp->declBit  (c+281,"cache_simX dmem_controller icache get_miss_index found",-1);
+	vcdp->declBus  (c+326,"cache_simX dmem_controller icache get_miss_index i",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk1[0] choose_thread N",-1,31,0);
+	vcdp->declBus  (c+282,"cache_simX dmem_controller icache genblk1[0] choose_thread valids",-1,0,0);
+	vcdp->declBus  (c+327,"cache_simX dmem_controller icache genblk1[0] choose_thread mask",-1,0,0);
+	vcdp->declBus  (c+328,"cache_simX dmem_controller icache genblk1[0] choose_thread index",-1,0,0);
+	vcdp->declBit  (c+329,"cache_simX dmem_controller icache genblk1[0] choose_thread found",-1);
+	vcdp->declBus  (c+4884,"cache_simX dmem_controller icache genblk1[0] choose_thread i",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk1[1] choose_thread N",-1,31,0);
+	vcdp->declBus  (c+286,"cache_simX dmem_controller icache genblk1[1] choose_thread valids",-1,0,0);
+	vcdp->declBus  (c+330,"cache_simX dmem_controller icache genblk1[1] choose_thread mask",-1,0,0);
+	vcdp->declBus  (c+331,"cache_simX dmem_controller icache genblk1[1] choose_thread index",-1,0,0);
+	vcdp->declBit  (c+332,"cache_simX dmem_controller icache genblk1[1] choose_thread found",-1);
+	vcdp->declBus  (c+4884,"cache_simX dmem_controller icache genblk1[1] choose_thread i",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk1[2] choose_thread N",-1,31,0);
+	vcdp->declBus  (c+290,"cache_simX dmem_controller icache genblk1[2] choose_thread valids",-1,0,0);
+	vcdp->declBus  (c+333,"cache_simX dmem_controller icache genblk1[2] choose_thread mask",-1,0,0);
+	vcdp->declBus  (c+334,"cache_simX dmem_controller icache genblk1[2] choose_thread index",-1,0,0);
+	vcdp->declBit  (c+335,"cache_simX dmem_controller icache genblk1[2] choose_thread found",-1);
+	vcdp->declBus  (c+4884,"cache_simX dmem_controller icache genblk1[2] choose_thread i",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk1[3] choose_thread N",-1,31,0);
+	vcdp->declBus  (c+294,"cache_simX dmem_controller icache genblk1[3] choose_thread valids",-1,0,0);
+	vcdp->declBus  (c+336,"cache_simX dmem_controller icache genblk1[3] choose_thread mask",-1,0,0);
+	vcdp->declBus  (c+337,"cache_simX dmem_controller icache genblk1[3] choose_thread index",-1,0,0);
+	vcdp->declBit  (c+338,"cache_simX dmem_controller icache genblk1[3] choose_thread found",-1);
+	vcdp->declBus  (c+4884,"cache_simX dmem_controller icache genblk1[3] choose_thread i",-1,31,0);
+	vcdp->declBus  (c+4806,"cache_simX VX_icache_req pc_address",-1,31,0);
+	vcdp->declBus  (c+4820,"cache_simX VX_icache_req out_cache_driver_in_mem_read",-1,2,0);
+	vcdp->declBus  (c+4825,"cache_simX VX_icache_req out_cache_driver_in_mem_write",-1,2,0);
+	vcdp->declBit  (c+4807,"cache_simX VX_icache_req out_cache_driver_in_valid",-1);
+	vcdp->declBus  (c+4826,"cache_simX VX_icache_req out_cache_driver_in_data",-1,31,0);
+	vcdp->declBus  (c+1034,"cache_simX VX_icache_rsp instruction",-1,31,0);
+	vcdp->declBit  (c+1035,"cache_simX VX_icache_rsp delay",-1);
+	vcdp->declBus  (c+4829,"cache_simX VX_dram_req_rsp_icache NUMBER_BANKS",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX VX_dram_req_rsp_icache NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+238,"cache_simX VX_dram_req_rsp_icache o_m_evict_addr",-1,31,0);
+	vcdp->declBus  (c+1181,"cache_simX VX_dram_req_rsp_icache o_m_read_addr",-1,31,0);
+	vcdp->declBit  (c+1182,"cache_simX VX_dram_req_rsp_icache o_m_valid",-1);
+	vcdp->declArray(c+239,"cache_simX VX_dram_req_rsp_icache o_m_writedata",-1,511,0);
+	vcdp->declBit  (c+1056,"cache_simX VX_dram_req_rsp_icache o_m_read_or_write",-1);
+	vcdp->declArray(c+4866,"cache_simX VX_dram_req_rsp_icache i_m_readdata",-1,511,0);
+	vcdp->declBit  (c+1163,"cache_simX VX_dram_req_rsp_icache i_m_ready",-1);
+	vcdp->declBus  (c+4829,"cache_simX VX_dram_req_rsp NUMBER_BANKS",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX VX_dram_req_rsp NUM_WORDS_PER_BLOCK",-1,31,0);
 	vcdp->declBus  (c+129,"cache_simX VX_dram_req_rsp o_m_evict_addr",-1,31,0);
-	vcdp->declBus  (c+716,"cache_simX VX_dram_req_rsp o_m_read_addr",-1,31,0);
-	vcdp->declBit  (c+717,"cache_simX VX_dram_req_rsp o_m_valid",-1);
+	vcdp->declBus  (c+1171,"cache_simX VX_dram_req_rsp o_m_read_addr",-1,31,0);
+	vcdp->declBit  (c+1172,"cache_simX VX_dram_req_rsp o_m_valid",-1);
 	vcdp->declArray(c+130,"cache_simX VX_dram_req_rsp o_m_writedata",-1,511,0);
-	vcdp->declBit  (c+604,"cache_simX VX_dram_req_rsp o_m_read_or_write",-1);
-	vcdp->declArray(c+3107,"cache_simX VX_dram_req_rsp i_m_readdata",-1,511,0);
-	vcdp->declBit  (c+709,"cache_simX VX_dram_req_rsp i_m_ready",-1);
-	vcdp->declBus  (c+3101,"cache_simX VX_dram_req_rsp_icache NUMBER_BANKS",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX VX_dram_req_rsp_icache NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+230,"cache_simX VX_dram_req_rsp_icache o_m_evict_addr",-1,31,0);
-	vcdp->declBus  (c+726,"cache_simX VX_dram_req_rsp_icache o_m_read_addr",-1,31,0);
-	vcdp->declBit  (c+727,"cache_simX VX_dram_req_rsp_icache o_m_valid",-1);
-	vcdp->declArray(c+606,"cache_simX VX_dram_req_rsp_icache o_m_writedata",-1,127,0);
-	vcdp->declBit  (c+610,"cache_simX VX_dram_req_rsp_icache o_m_read_or_write",-1);
-	vcdp->declArray(c+3132,"cache_simX VX_dram_req_rsp_icache i_m_readdata",-1,127,0);
-	vcdp->declBit  (c+708,"cache_simX VX_dram_req_rsp_icache i_m_ready",-1);
+	vcdp->declBit  (c+1054,"cache_simX VX_dram_req_rsp o_m_read_or_write",-1);
+	vcdp->declArray(c+4848,"cache_simX VX_dram_req_rsp i_m_readdata",-1,511,0);
+	vcdp->declBit  (c+1164,"cache_simX VX_dram_req_rsp i_m_ready",-1);
 	vcdp->declArray(c+5,"cache_simX VX_dcache_req out_cache_driver_in_address",-1,127,0);
-	vcdp->declBus  (c+3068,"cache_simX VX_dcache_req out_cache_driver_in_mem_read",-1,2,0);
-	vcdp->declBus  (c+3069,"cache_simX VX_dcache_req out_cache_driver_in_mem_write",-1,2,0);
-	vcdp->declBus  (c+314,"cache_simX VX_dcache_req out_cache_driver_in_valid",-1,3,0);
-	vcdp->declArray(c+3080,"cache_simX VX_dcache_req out_cache_driver_in_data",-1,127,0);
-	vcdp->declArray(c+315,"cache_simX VX_dcache_rsp in_cache_driver_out_data",-1,127,0);
-	vcdp->declBit  (c+615,"cache_simX VX_dcache_rsp delay",-1);
-	vcdp->declBus  (c+3098,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_SIZE",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3099,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_BANKS",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure LOG_NUM_BANKS",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure LOG_NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure OFFSET_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[0] bank_structure OFFSET_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure IND_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3103,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_TAG_START",-1,31,0);
-	vcdp->declBus  (c+3104,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_TAG_END",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_OFFSET_START",-1,31,0);
-	vcdp->declBus  (c+3093,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_OFFSET_END",-1,31,0);
-	vcdp->declBus  (c+3094,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_IND_START",-1,31,0);
-	vcdp->declBus  (c+3105,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_IND_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[0] bank_structure SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBus  (c+3094,"cache_simX dmem_controller dcache genblk3[0] bank_structure BLOCK_NUM_BITS",-1,31,0);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[0] bank_structure rst",-1);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[0] bank_structure clk",-1);
-	vcdp->declBus  (c+723,"cache_simX dmem_controller dcache genblk3[0] bank_structure state",-1,3,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[0] bank_structure actual_index",-1,4,0);
+	vcdp->declBus  (c+4809,"cache_simX VX_dcache_req out_cache_driver_in_mem_read",-1,2,0);
+	vcdp->declBus  (c+4810,"cache_simX VX_dcache_req out_cache_driver_in_mem_write",-1,2,0);
+	vcdp->declBus  (c+339,"cache_simX VX_dcache_req out_cache_driver_in_valid",-1,3,0);
+	vcdp->declArray(c+4821,"cache_simX VX_dcache_req out_cache_driver_in_data",-1,127,0);
+	vcdp->declArray(c+340,"cache_simX VX_dcache_rsp in_cache_driver_out_data",-1,127,0);
+	vcdp->declBit  (c+1058,"cache_simX VX_dcache_rsp delay",-1);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_SIZE",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4840,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[0] bank_structure LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[0] bank_structure LOG_NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[0] bank_structure OFFSET_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[0] bank_structure OFFSET_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[0] bank_structure TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[0] bank_structure TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[0] bank_structure IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[0] bank_structure IND_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4844,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_TAG_START",-1,31,0);
+	vcdp->declBus  (c+4845,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_TAG_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4834,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_IND_START",-1,31,0);
+	vcdp->declBus  (c+4846,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_IND_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[0] bank_structure SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[0] bank_structure RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller icache genblk3[0] bank_structure BLOCK_NUM_BITS",-1,31,0);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[0] bank_structure rst",-1);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[0] bank_structure clk",-1);
+	vcdp->declBus  (c+1185,"cache_simX dmem_controller icache genblk3[0] bank_structure state",-1,3,0);
+	vcdp->declBus  (c+302,"cache_simX dmem_controller icache genblk3[0] bank_structure actual_index",-1,4,0);
+	vcdp->declBus  (c+300,"cache_simX dmem_controller icache genblk3[0] bank_structure o_tag",-1,20,0);
+	vcdp->declBus  (c+301,"cache_simX dmem_controller icache genblk3[0] bank_structure block_offset",-1,1,0);
+	vcdp->declBus  (c+344,"cache_simX dmem_controller icache genblk3[0] bank_structure writedata",-1,31,0);
+	vcdp->declBit  (c+304,"cache_simX dmem_controller icache genblk3[0] bank_structure valid_in",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[0] bank_structure read_or_write",-1);
+	vcdp->declArray(c+4885,"cache_simX dmem_controller icache genblk3[0] bank_structure fetched_writedata",-1,127,0);
+	vcdp->declBus  (c+23,"cache_simX dmem_controller icache genblk3[0] bank_structure i_p_mem_read",-1,2,0);
+	vcdp->declBus  (c+4825,"cache_simX dmem_controller icache genblk3[0] bank_structure i_p_mem_write",-1,2,0);
+	vcdp->declBus  (c+299,"cache_simX dmem_controller icache genblk3[0] bank_structure byte_select",-1,1,0);
+	vcdp->declBus  (c+1184,"cache_simX dmem_controller icache genblk3[0] bank_structure evicted_way",-1,0,0);
+	vcdp->declBus  (c+345,"cache_simX dmem_controller icache genblk3[0] bank_structure readdata",-1,31,0);
+	vcdp->declBit  (c+346,"cache_simX dmem_controller icache genblk3[0] bank_structure hit",-1);
+	vcdp->declBit  (c+347,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_wb",-1);
+	vcdp->declBus  (c+348,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_addr",-1,31,0);
+	vcdp->declArray(c+349,"cache_simX dmem_controller icache genblk3[0] bank_structure data_evicted",-1,127,0);
+	vcdp->declArray(c+349,"cache_simX dmem_controller icache genblk3[0] bank_structure data_use",-1,127,0);
+	vcdp->declBus  (c+353,"cache_simX dmem_controller icache genblk3[0] bank_structure tag_use",-1,20,0);
+	vcdp->declBus  (c+353,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_tag",-1,20,0);
+	vcdp->declBit  (c+354,"cache_simX dmem_controller icache genblk3[0] bank_structure valid_use",-1);
+	vcdp->declBit  (c+347,"cache_simX dmem_controller icache genblk3[0] bank_structure dirty_use",-1);
+	vcdp->declBit  (c+355,"cache_simX dmem_controller icache genblk3[0] bank_structure access",-1);
+	vcdp->declBit  (c+356,"cache_simX dmem_controller icache genblk3[0] bank_structure write_from_mem",-1);
+	vcdp->declBit  (c+357,"cache_simX dmem_controller icache genblk3[0] bank_structure miss",-1);
+	vcdp->declBus  (c+1155,"cache_simX dmem_controller icache genblk3[0] bank_structure way_to_update",-1,0,0);
+	vcdp->declBit  (c+358,"cache_simX dmem_controller icache genblk3[0] bank_structure lw",-1);
+	vcdp->declBit  (c+359,"cache_simX dmem_controller icache genblk3[0] bank_structure lb",-1);
+	vcdp->declBit  (c+360,"cache_simX dmem_controller icache genblk3[0] bank_structure lh",-1);
+	vcdp->declBit  (c+361,"cache_simX dmem_controller icache genblk3[0] bank_structure lhu",-1);
+	vcdp->declBit  (c+362,"cache_simX dmem_controller icache genblk3[0] bank_structure lbu",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[0] bank_structure sw",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[0] bank_structure sb",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[0] bank_structure sh",-1);
+	vcdp->declBit  (c+363,"cache_simX dmem_controller icache genblk3[0] bank_structure b0",-1);
+	vcdp->declBit  (c+364,"cache_simX dmem_controller icache genblk3[0] bank_structure b1",-1);
+	vcdp->declBit  (c+365,"cache_simX dmem_controller icache genblk3[0] bank_structure b2",-1);
+	vcdp->declBit  (c+366,"cache_simX dmem_controller icache genblk3[0] bank_structure b3",-1);
+	vcdp->declBus  (c+367,"cache_simX dmem_controller icache genblk3[0] bank_structure data_unQual",-1,31,0);
+	vcdp->declBus  (c+368,"cache_simX dmem_controller icache genblk3[0] bank_structure lb_data",-1,31,0);
+	vcdp->declBus  (c+369,"cache_simX dmem_controller icache genblk3[0] bank_structure lh_data",-1,31,0);
+	vcdp->declBus  (c+370,"cache_simX dmem_controller icache genblk3[0] bank_structure lbu_data",-1,31,0);
+	vcdp->declBus  (c+371,"cache_simX dmem_controller icache genblk3[0] bank_structure lhu_data",-1,31,0);
+	vcdp->declBus  (c+367,"cache_simX dmem_controller icache genblk3[0] bank_structure lw_data",-1,31,0);
+	vcdp->declBus  (c+344,"cache_simX dmem_controller icache genblk3[0] bank_structure sw_data",-1,31,0);
+	vcdp->declBus  (c+372,"cache_simX dmem_controller icache genblk3[0] bank_structure sb_data",-1,31,0);
+	vcdp->declBus  (c+373,"cache_simX dmem_controller icache genblk3[0] bank_structure sh_data",-1,31,0);
+	vcdp->declBus  (c+344,"cache_simX dmem_controller icache genblk3[0] bank_structure use_write_data",-1,31,0);
+	vcdp->declBus  (c+374,"cache_simX dmem_controller icache genblk3[0] bank_structure data_Qual",-1,31,0);
+	vcdp->declBus  (c+375,"cache_simX dmem_controller icache genblk3[0] bank_structure sb_mask",-1,3,0);
+	vcdp->declBus  (c+376,"cache_simX dmem_controller icache genblk3[0] bank_structure sh_mask",-1,3,0);
+	vcdp->declBus  (c+377,"cache_simX dmem_controller icache genblk3[0] bank_structure we",-1,15,0);
+	vcdp->declArray(c+378,"cache_simX dmem_controller icache genblk3[0] bank_structure data_write",-1,127,0);
+	// Tracing: cache_simX dmem_controller icache genblk3[0] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[0] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[1] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[2] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[3] normal_write",-1);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures rst",-1);
+	vcdp->declBit  (c+304,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_in",-1);
+	vcdp->declBus  (c+1185,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures state",-1,3,0);
+	vcdp->declBus  (c+302,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures addr",-1,4,0);
+	vcdp->declBus  (c+377,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures we",-1,15,0);
+	vcdp->declBit  (c+356,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures evict",-1);
+	vcdp->declBus  (c+1155,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_to_update",-1,0,0);
+	vcdp->declArray(c+378,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+300,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+353,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+349,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+354,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_use",-1);
+	vcdp->declBit  (c+347,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures dirty_use",-1);
+	vcdp->declQuad (c+382,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_use_per_way",-1,41,0);
+	vcdp->declArray(c+384,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_use_per_way",-1,255,0);
+	vcdp->declBus  (c+392,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_use_per_way",-1,1,0);
+	vcdp->declBus  (c+393,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures dirty_use_per_way",-1,1,0);
+	vcdp->declBus  (c+394,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures hit_per_way",-1,1,0);
+	vcdp->declBus  (c+395,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures we_per_way",-1,31,0);
+	vcdp->declArray(c+396,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_write_per_way",-1,255,0);
+	vcdp->declBus  (c+404,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures write_from_mem_per_way",-1,1,0);
+	vcdp->declBit  (c+405,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures invalid_found",-1);
+	vcdp->declBus  (c+406,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_index",-1,0,0);
+	vcdp->declBus  (c+407,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures invalid_index",-1,0,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+408,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_use_Qual",-1,0,0);
+	// Tracing: cache_simX dmem_controller icache genblk3[0] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index N",-1,31,0);
+	vcdp->declBus  (c+409,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
+	vcdp->declBus  (c+407,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index index",-1,0,0);
+	vcdp->declBit  (c+405,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index i",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
+	vcdp->declBus  (c+394,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
+	vcdp->declBus  (c+406,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
+	vcdp->declBit  (c+410,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures rst",-1);
+	vcdp->declBus  (c+302,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+411,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
+	vcdp->declBit  (c+412,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures evict",-1);
+	vcdp->declArray(c+413,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+300,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1059,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1060,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1064,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures valid_use",-1);
+	vcdp->declBit  (c+417,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
+	vcdp->declBit  (c+418,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
+	vcdp->declBit  (c+419,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
+	vcdp->declBit  (c+420,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
+	vcdp->declArray(c+1188,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+1192,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+1196,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+1200,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+1204,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+1208,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+1212,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+1216,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+1220,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+1224,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+1228,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+1232,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+1236,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+1240,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+1244,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+1248,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+1252,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+1256,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+1260,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+1264,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+1268,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+1272,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+1276,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+1280,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+1284,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+1288,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+1292,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+1296,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+1300,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+1304,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+1308,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+1312,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBus  (c+1316+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+1348+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+1380+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+1412,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
+	vcdp->declBus  (c+1413,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures rst",-1);
+	vcdp->declBus  (c+302,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+421,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
+	vcdp->declBit  (c+422,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures evict",-1);
+	vcdp->declArray(c+423,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+300,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1065,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1066,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1070,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures valid_use",-1);
+	vcdp->declBit  (c+427,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
+	vcdp->declBit  (c+428,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
+	vcdp->declBit  (c+429,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
+	vcdp->declBit  (c+430,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
+	vcdp->declArray(c+1414,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+1418,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+1422,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+1426,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+1430,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+1434,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+1438,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+1442,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+1446,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+1450,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+1454,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+1458,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+1462,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+1466,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+1470,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+1474,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+1478,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+1482,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+1486,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+1490,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+1494,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+1498,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+1502,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+1506,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+1510,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+1514,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+1518,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+1522,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+1526,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+1530,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+1534,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+1538,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBus  (c+1542+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+1574+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+1606+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+1638,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
+	vcdp->declBus  (c+1639,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller icache genblk3[1] bank_structure CACHE_SIZE",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[1] bank_structure CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4840,"cache_simX dmem_controller icache genblk3[1] bank_structure CACHE_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[1] bank_structure CACHE_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[1] bank_structure LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[1] bank_structure NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[1] bank_structure LOG_NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[1] bank_structure NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[1] bank_structure CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[1] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[1] bank_structure OFFSET_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[1] bank_structure OFFSET_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[1] bank_structure TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[1] bank_structure TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[1] bank_structure IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[1] bank_structure IND_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4844,"cache_simX dmem_controller icache genblk3[1] bank_structure ADDR_TAG_START",-1,31,0);
+	vcdp->declBus  (c+4845,"cache_simX dmem_controller icache genblk3[1] bank_structure ADDR_TAG_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[1] bank_structure ADDR_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4834,"cache_simX dmem_controller icache genblk3[1] bank_structure ADDR_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller icache genblk3[1] bank_structure ADDR_IND_START",-1,31,0);
+	vcdp->declBus  (c+4846,"cache_simX dmem_controller icache genblk3[1] bank_structure ADDR_IND_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[1] bank_structure CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[1] bank_structure SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[1] bank_structure RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller icache genblk3[1] bank_structure BLOCK_NUM_BITS",-1,31,0);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[1] bank_structure rst",-1);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[1] bank_structure clk",-1);
+	vcdp->declBus  (c+1185,"cache_simX dmem_controller icache genblk3[1] bank_structure state",-1,3,0);
+	vcdp->declBus  (c+309,"cache_simX dmem_controller icache genblk3[1] bank_structure actual_index",-1,4,0);
+	vcdp->declBus  (c+307,"cache_simX dmem_controller icache genblk3[1] bank_structure o_tag",-1,20,0);
+	vcdp->declBus  (c+308,"cache_simX dmem_controller icache genblk3[1] bank_structure block_offset",-1,1,0);
+	vcdp->declBus  (c+431,"cache_simX dmem_controller icache genblk3[1] bank_structure writedata",-1,31,0);
+	vcdp->declBit  (c+311,"cache_simX dmem_controller icache genblk3[1] bank_structure valid_in",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[1] bank_structure read_or_write",-1);
+	vcdp->declArray(c+4889,"cache_simX dmem_controller icache genblk3[1] bank_structure fetched_writedata",-1,127,0);
+	vcdp->declBus  (c+23,"cache_simX dmem_controller icache genblk3[1] bank_structure i_p_mem_read",-1,2,0);
+	vcdp->declBus  (c+4825,"cache_simX dmem_controller icache genblk3[1] bank_structure i_p_mem_write",-1,2,0);
+	vcdp->declBus  (c+306,"cache_simX dmem_controller icache genblk3[1] bank_structure byte_select",-1,1,0);
+	vcdp->declBus  (c+1184,"cache_simX dmem_controller icache genblk3[1] bank_structure evicted_way",-1,0,0);
+	vcdp->declBus  (c+432,"cache_simX dmem_controller icache genblk3[1] bank_structure readdata",-1,31,0);
+	vcdp->declBit  (c+433,"cache_simX dmem_controller icache genblk3[1] bank_structure hit",-1);
+	vcdp->declBit  (c+434,"cache_simX dmem_controller icache genblk3[1] bank_structure eviction_wb",-1);
+	vcdp->declBus  (c+435,"cache_simX dmem_controller icache genblk3[1] bank_structure eviction_addr",-1,31,0);
+	vcdp->declArray(c+436,"cache_simX dmem_controller icache genblk3[1] bank_structure data_evicted",-1,127,0);
+	vcdp->declArray(c+436,"cache_simX dmem_controller icache genblk3[1] bank_structure data_use",-1,127,0);
+	vcdp->declBus  (c+440,"cache_simX dmem_controller icache genblk3[1] bank_structure tag_use",-1,20,0);
+	vcdp->declBus  (c+440,"cache_simX dmem_controller icache genblk3[1] bank_structure eviction_tag",-1,20,0);
+	vcdp->declBit  (c+441,"cache_simX dmem_controller icache genblk3[1] bank_structure valid_use",-1);
+	vcdp->declBit  (c+434,"cache_simX dmem_controller icache genblk3[1] bank_structure dirty_use",-1);
+	vcdp->declBit  (c+442,"cache_simX dmem_controller icache genblk3[1] bank_structure access",-1);
+	vcdp->declBit  (c+443,"cache_simX dmem_controller icache genblk3[1] bank_structure write_from_mem",-1);
+	vcdp->declBit  (c+444,"cache_simX dmem_controller icache genblk3[1] bank_structure miss",-1);
+	vcdp->declBus  (c+1156,"cache_simX dmem_controller icache genblk3[1] bank_structure way_to_update",-1,0,0);
+	vcdp->declBit  (c+358,"cache_simX dmem_controller icache genblk3[1] bank_structure lw",-1);
+	vcdp->declBit  (c+359,"cache_simX dmem_controller icache genblk3[1] bank_structure lb",-1);
+	vcdp->declBit  (c+360,"cache_simX dmem_controller icache genblk3[1] bank_structure lh",-1);
+	vcdp->declBit  (c+361,"cache_simX dmem_controller icache genblk3[1] bank_structure lhu",-1);
+	vcdp->declBit  (c+362,"cache_simX dmem_controller icache genblk3[1] bank_structure lbu",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[1] bank_structure sw",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[1] bank_structure sb",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[1] bank_structure sh",-1);
+	vcdp->declBit  (c+445,"cache_simX dmem_controller icache genblk3[1] bank_structure b0",-1);
+	vcdp->declBit  (c+446,"cache_simX dmem_controller icache genblk3[1] bank_structure b1",-1);
+	vcdp->declBit  (c+447,"cache_simX dmem_controller icache genblk3[1] bank_structure b2",-1);
+	vcdp->declBit  (c+448,"cache_simX dmem_controller icache genblk3[1] bank_structure b3",-1);
+	vcdp->declBus  (c+449,"cache_simX dmem_controller icache genblk3[1] bank_structure data_unQual",-1,31,0);
+	vcdp->declBus  (c+450,"cache_simX dmem_controller icache genblk3[1] bank_structure lb_data",-1,31,0);
+	vcdp->declBus  (c+451,"cache_simX dmem_controller icache genblk3[1] bank_structure lh_data",-1,31,0);
+	vcdp->declBus  (c+452,"cache_simX dmem_controller icache genblk3[1] bank_structure lbu_data",-1,31,0);
+	vcdp->declBus  (c+453,"cache_simX dmem_controller icache genblk3[1] bank_structure lhu_data",-1,31,0);
+	vcdp->declBus  (c+449,"cache_simX dmem_controller icache genblk3[1] bank_structure lw_data",-1,31,0);
+	vcdp->declBus  (c+431,"cache_simX dmem_controller icache genblk3[1] bank_structure sw_data",-1,31,0);
+	vcdp->declBus  (c+454,"cache_simX dmem_controller icache genblk3[1] bank_structure sb_data",-1,31,0);
+	vcdp->declBus  (c+455,"cache_simX dmem_controller icache genblk3[1] bank_structure sh_data",-1,31,0);
+	vcdp->declBus  (c+431,"cache_simX dmem_controller icache genblk3[1] bank_structure use_write_data",-1,31,0);
+	vcdp->declBus  (c+456,"cache_simX dmem_controller icache genblk3[1] bank_structure data_Qual",-1,31,0);
+	vcdp->declBus  (c+457,"cache_simX dmem_controller icache genblk3[1] bank_structure sb_mask",-1,3,0);
+	vcdp->declBus  (c+458,"cache_simX dmem_controller icache genblk3[1] bank_structure sh_mask",-1,3,0);
+	vcdp->declBus  (c+459,"cache_simX dmem_controller icache genblk3[1] bank_structure we",-1,15,0);
+	vcdp->declArray(c+460,"cache_simX dmem_controller icache genblk3[1] bank_structure data_write",-1,127,0);
+	// Tracing: cache_simX dmem_controller icache genblk3[1] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[1] bank_structure genblk1[0] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[1] bank_structure genblk1[1] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[1] bank_structure genblk1[2] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[1] bank_structure genblk1[3] normal_write",-1);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures rst",-1);
+	vcdp->declBit  (c+311,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures valid_in",-1);
+	vcdp->declBus  (c+1185,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures state",-1,3,0);
+	vcdp->declBus  (c+309,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures addr",-1,4,0);
+	vcdp->declBus  (c+459,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures we",-1,15,0);
+	vcdp->declBit  (c+443,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures evict",-1);
+	vcdp->declBus  (c+1156,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures way_to_update",-1,0,0);
+	vcdp->declArray(c+460,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+307,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+440,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+436,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+441,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures valid_use",-1);
+	vcdp->declBit  (c+434,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures dirty_use",-1);
+	vcdp->declQuad (c+464,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures tag_use_per_way",-1,41,0);
+	vcdp->declArray(c+466,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures data_use_per_way",-1,255,0);
+	vcdp->declBus  (c+474,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures valid_use_per_way",-1,1,0);
+	vcdp->declBus  (c+475,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures dirty_use_per_way",-1,1,0);
+	vcdp->declBus  (c+476,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures hit_per_way",-1,1,0);
+	vcdp->declBus  (c+477,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures we_per_way",-1,31,0);
+	vcdp->declArray(c+478,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures data_write_per_way",-1,255,0);
+	vcdp->declBus  (c+486,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures write_from_mem_per_way",-1,1,0);
+	vcdp->declBit  (c+487,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures invalid_found",-1);
+	vcdp->declBus  (c+488,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures way_index",-1,0,0);
+	vcdp->declBus  (c+489,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures invalid_index",-1,0,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+490,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures way_use_Qual",-1,0,0);
+	// Tracing: cache_simX dmem_controller icache genblk3[1] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures genblk1 valid_index N",-1,31,0);
+	vcdp->declBus  (c+491,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
+	vcdp->declBus  (c+489,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures genblk1 valid_index index",-1,0,0);
+	vcdp->declBit  (c+487,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures genblk1 valid_index found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures genblk1 valid_index i",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
+	vcdp->declBus  (c+476,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
+	vcdp->declBus  (c+488,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
+	vcdp->declBit  (c+492,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures genblk1 way_indexing found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures rst",-1);
+	vcdp->declBus  (c+309,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+493,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
+	vcdp->declBit  (c+494,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures evict",-1);
+	vcdp->declArray(c+495,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+307,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1071,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1072,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1076,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures valid_use",-1);
+	vcdp->declBit  (c+499,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
+	vcdp->declBit  (c+500,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
+	vcdp->declBit  (c+501,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
+	vcdp->declBit  (c+502,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
+	vcdp->declArray(c+1640,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+1644,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+1648,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+1652,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+1656,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+1660,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+1664,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+1668,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+1672,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+1676,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+1680,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+1684,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+1688,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+1692,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+1696,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+1700,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+1704,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+1708,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+1712,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+1716,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+1720,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+1724,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+1728,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+1732,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+1736,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+1740,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+1744,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+1748,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+1752,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+1756,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+1760,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+1764,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBus  (c+1768+i*1,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+1800+i*1,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+1832+i*1,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+1864,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
+	vcdp->declBus  (c+1865,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures rst",-1);
+	vcdp->declBus  (c+309,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+503,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
+	vcdp->declBit  (c+504,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures evict",-1);
+	vcdp->declArray(c+505,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+307,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1077,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1078,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1082,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures valid_use",-1);
+	vcdp->declBit  (c+509,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
+	vcdp->declBit  (c+510,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
+	vcdp->declBit  (c+511,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
+	vcdp->declBit  (c+512,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
+	vcdp->declArray(c+1866,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+1870,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+1874,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+1878,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+1882,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+1886,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+1890,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+1894,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+1898,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+1902,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+1906,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+1910,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+1914,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+1918,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+1922,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+1926,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+1930,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+1934,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+1938,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+1942,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+1946,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+1950,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+1954,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+1958,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+1962,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+1966,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+1970,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+1974,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+1978,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+1982,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+1986,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+1990,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBus  (c+1994+i*1,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+2026+i*1,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+2058+i*1,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+2090,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
+	vcdp->declBus  (c+2091,"cache_simX dmem_controller icache genblk3[1] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller icache genblk3[2] bank_structure CACHE_SIZE",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[2] bank_structure CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4840,"cache_simX dmem_controller icache genblk3[2] bank_structure CACHE_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[2] bank_structure CACHE_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[2] bank_structure LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[2] bank_structure NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[2] bank_structure LOG_NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[2] bank_structure NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[2] bank_structure CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[2] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[2] bank_structure OFFSET_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[2] bank_structure OFFSET_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[2] bank_structure TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[2] bank_structure TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[2] bank_structure IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[2] bank_structure IND_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4844,"cache_simX dmem_controller icache genblk3[2] bank_structure ADDR_TAG_START",-1,31,0);
+	vcdp->declBus  (c+4845,"cache_simX dmem_controller icache genblk3[2] bank_structure ADDR_TAG_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[2] bank_structure ADDR_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4834,"cache_simX dmem_controller icache genblk3[2] bank_structure ADDR_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller icache genblk3[2] bank_structure ADDR_IND_START",-1,31,0);
+	vcdp->declBus  (c+4846,"cache_simX dmem_controller icache genblk3[2] bank_structure ADDR_IND_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[2] bank_structure CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[2] bank_structure SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[2] bank_structure RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller icache genblk3[2] bank_structure BLOCK_NUM_BITS",-1,31,0);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[2] bank_structure rst",-1);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[2] bank_structure clk",-1);
+	vcdp->declBus  (c+1185,"cache_simX dmem_controller icache genblk3[2] bank_structure state",-1,3,0);
+	vcdp->declBus  (c+316,"cache_simX dmem_controller icache genblk3[2] bank_structure actual_index",-1,4,0);
+	vcdp->declBus  (c+314,"cache_simX dmem_controller icache genblk3[2] bank_structure o_tag",-1,20,0);
+	vcdp->declBus  (c+315,"cache_simX dmem_controller icache genblk3[2] bank_structure block_offset",-1,1,0);
+	vcdp->declBus  (c+513,"cache_simX dmem_controller icache genblk3[2] bank_structure writedata",-1,31,0);
+	vcdp->declBit  (c+318,"cache_simX dmem_controller icache genblk3[2] bank_structure valid_in",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[2] bank_structure read_or_write",-1);
+	vcdp->declArray(c+4893,"cache_simX dmem_controller icache genblk3[2] bank_structure fetched_writedata",-1,127,0);
+	vcdp->declBus  (c+23,"cache_simX dmem_controller icache genblk3[2] bank_structure i_p_mem_read",-1,2,0);
+	vcdp->declBus  (c+4825,"cache_simX dmem_controller icache genblk3[2] bank_structure i_p_mem_write",-1,2,0);
+	vcdp->declBus  (c+313,"cache_simX dmem_controller icache genblk3[2] bank_structure byte_select",-1,1,0);
+	vcdp->declBus  (c+1184,"cache_simX dmem_controller icache genblk3[2] bank_structure evicted_way",-1,0,0);
+	vcdp->declBus  (c+514,"cache_simX dmem_controller icache genblk3[2] bank_structure readdata",-1,31,0);
+	vcdp->declBit  (c+515,"cache_simX dmem_controller icache genblk3[2] bank_structure hit",-1);
+	vcdp->declBit  (c+516,"cache_simX dmem_controller icache genblk3[2] bank_structure eviction_wb",-1);
+	vcdp->declBus  (c+517,"cache_simX dmem_controller icache genblk3[2] bank_structure eviction_addr",-1,31,0);
+	vcdp->declArray(c+518,"cache_simX dmem_controller icache genblk3[2] bank_structure data_evicted",-1,127,0);
+	vcdp->declArray(c+518,"cache_simX dmem_controller icache genblk3[2] bank_structure data_use",-1,127,0);
+	vcdp->declBus  (c+522,"cache_simX dmem_controller icache genblk3[2] bank_structure tag_use",-1,20,0);
+	vcdp->declBus  (c+522,"cache_simX dmem_controller icache genblk3[2] bank_structure eviction_tag",-1,20,0);
+	vcdp->declBit  (c+523,"cache_simX dmem_controller icache genblk3[2] bank_structure valid_use",-1);
+	vcdp->declBit  (c+516,"cache_simX dmem_controller icache genblk3[2] bank_structure dirty_use",-1);
+	vcdp->declBit  (c+524,"cache_simX dmem_controller icache genblk3[2] bank_structure access",-1);
+	vcdp->declBit  (c+525,"cache_simX dmem_controller icache genblk3[2] bank_structure write_from_mem",-1);
+	vcdp->declBit  (c+526,"cache_simX dmem_controller icache genblk3[2] bank_structure miss",-1);
+	vcdp->declBus  (c+1157,"cache_simX dmem_controller icache genblk3[2] bank_structure way_to_update",-1,0,0);
+	vcdp->declBit  (c+358,"cache_simX dmem_controller icache genblk3[2] bank_structure lw",-1);
+	vcdp->declBit  (c+359,"cache_simX dmem_controller icache genblk3[2] bank_structure lb",-1);
+	vcdp->declBit  (c+360,"cache_simX dmem_controller icache genblk3[2] bank_structure lh",-1);
+	vcdp->declBit  (c+361,"cache_simX dmem_controller icache genblk3[2] bank_structure lhu",-1);
+	vcdp->declBit  (c+362,"cache_simX dmem_controller icache genblk3[2] bank_structure lbu",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[2] bank_structure sw",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[2] bank_structure sb",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[2] bank_structure sh",-1);
+	vcdp->declBit  (c+527,"cache_simX dmem_controller icache genblk3[2] bank_structure b0",-1);
+	vcdp->declBit  (c+528,"cache_simX dmem_controller icache genblk3[2] bank_structure b1",-1);
+	vcdp->declBit  (c+529,"cache_simX dmem_controller icache genblk3[2] bank_structure b2",-1);
+	vcdp->declBit  (c+530,"cache_simX dmem_controller icache genblk3[2] bank_structure b3",-1);
+	vcdp->declBus  (c+531,"cache_simX dmem_controller icache genblk3[2] bank_structure data_unQual",-1,31,0);
+	vcdp->declBus  (c+532,"cache_simX dmem_controller icache genblk3[2] bank_structure lb_data",-1,31,0);
+	vcdp->declBus  (c+533,"cache_simX dmem_controller icache genblk3[2] bank_structure lh_data",-1,31,0);
+	vcdp->declBus  (c+534,"cache_simX dmem_controller icache genblk3[2] bank_structure lbu_data",-1,31,0);
+	vcdp->declBus  (c+535,"cache_simX dmem_controller icache genblk3[2] bank_structure lhu_data",-1,31,0);
+	vcdp->declBus  (c+531,"cache_simX dmem_controller icache genblk3[2] bank_structure lw_data",-1,31,0);
+	vcdp->declBus  (c+513,"cache_simX dmem_controller icache genblk3[2] bank_structure sw_data",-1,31,0);
+	vcdp->declBus  (c+536,"cache_simX dmem_controller icache genblk3[2] bank_structure sb_data",-1,31,0);
+	vcdp->declBus  (c+537,"cache_simX dmem_controller icache genblk3[2] bank_structure sh_data",-1,31,0);
+	vcdp->declBus  (c+513,"cache_simX dmem_controller icache genblk3[2] bank_structure use_write_data",-1,31,0);
+	vcdp->declBus  (c+538,"cache_simX dmem_controller icache genblk3[2] bank_structure data_Qual",-1,31,0);
+	vcdp->declBus  (c+539,"cache_simX dmem_controller icache genblk3[2] bank_structure sb_mask",-1,3,0);
+	vcdp->declBus  (c+540,"cache_simX dmem_controller icache genblk3[2] bank_structure sh_mask",-1,3,0);
+	vcdp->declBus  (c+541,"cache_simX dmem_controller icache genblk3[2] bank_structure we",-1,15,0);
+	vcdp->declArray(c+542,"cache_simX dmem_controller icache genblk3[2] bank_structure data_write",-1,127,0);
+	// Tracing: cache_simX dmem_controller icache genblk3[2] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[2] bank_structure genblk1[0] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[2] bank_structure genblk1[1] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[2] bank_structure genblk1[2] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[2] bank_structure genblk1[3] normal_write",-1);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures rst",-1);
+	vcdp->declBit  (c+318,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures valid_in",-1);
+	vcdp->declBus  (c+1185,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures state",-1,3,0);
+	vcdp->declBus  (c+316,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures addr",-1,4,0);
+	vcdp->declBus  (c+541,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures we",-1,15,0);
+	vcdp->declBit  (c+525,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures evict",-1);
+	vcdp->declBus  (c+1157,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures way_to_update",-1,0,0);
+	vcdp->declArray(c+542,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+314,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+522,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+518,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+523,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures valid_use",-1);
+	vcdp->declBit  (c+516,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures dirty_use",-1);
+	vcdp->declQuad (c+546,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures tag_use_per_way",-1,41,0);
+	vcdp->declArray(c+548,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures data_use_per_way",-1,255,0);
+	vcdp->declBus  (c+556,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures valid_use_per_way",-1,1,0);
+	vcdp->declBus  (c+557,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures dirty_use_per_way",-1,1,0);
+	vcdp->declBus  (c+558,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures hit_per_way",-1,1,0);
+	vcdp->declBus  (c+559,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures we_per_way",-1,31,0);
+	vcdp->declArray(c+560,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures data_write_per_way",-1,255,0);
+	vcdp->declBus  (c+568,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures write_from_mem_per_way",-1,1,0);
+	vcdp->declBit  (c+569,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures invalid_found",-1);
+	vcdp->declBus  (c+570,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures way_index",-1,0,0);
+	vcdp->declBus  (c+571,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures invalid_index",-1,0,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+572,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures way_use_Qual",-1,0,0);
+	// Tracing: cache_simX dmem_controller icache genblk3[2] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures genblk1 valid_index N",-1,31,0);
+	vcdp->declBus  (c+573,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
+	vcdp->declBus  (c+571,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures genblk1 valid_index index",-1,0,0);
+	vcdp->declBit  (c+569,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures genblk1 valid_index found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures genblk1 valid_index i",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
+	vcdp->declBus  (c+558,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
+	vcdp->declBus  (c+570,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
+	vcdp->declBit  (c+574,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures genblk1 way_indexing found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures rst",-1);
+	vcdp->declBus  (c+316,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+575,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
+	vcdp->declBit  (c+576,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures evict",-1);
+	vcdp->declArray(c+577,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+314,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1083,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1084,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1088,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures valid_use",-1);
+	vcdp->declBit  (c+581,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
+	vcdp->declBit  (c+582,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
+	vcdp->declBit  (c+583,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
+	vcdp->declBit  (c+584,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
+	vcdp->declArray(c+2092,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+2096,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+2100,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+2104,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+2108,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+2112,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+2116,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+2120,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+2124,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+2128,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+2132,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+2136,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+2140,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+2144,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+2148,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+2152,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+2156,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+2160,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+2164,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+2168,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+2172,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+2176,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+2180,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+2184,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+2188,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+2192,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+2196,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+2200,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+2204,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+2208,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+2212,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+2216,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBus  (c+2220+i*1,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+2252+i*1,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+2284+i*1,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+2316,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
+	vcdp->declBus  (c+2317,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures rst",-1);
+	vcdp->declBus  (c+316,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+585,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
+	vcdp->declBit  (c+586,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures evict",-1);
+	vcdp->declArray(c+587,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+314,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1089,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1090,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1094,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures valid_use",-1);
+	vcdp->declBit  (c+591,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
+	vcdp->declBit  (c+592,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
+	vcdp->declBit  (c+593,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
+	vcdp->declBit  (c+594,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
+	vcdp->declArray(c+2318,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+2322,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+2326,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+2330,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+2334,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+2338,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+2342,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+2346,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+2350,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+2354,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+2358,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+2362,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+2366,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+2370,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+2374,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+2378,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+2382,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+2386,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+2390,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+2394,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+2398,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+2402,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+2406,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+2410,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+2414,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+2418,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+2422,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+2426,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+2430,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+2434,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+2438,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+2442,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBus  (c+2446+i*1,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+2478+i*1,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+2510+i*1,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+2542,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
+	vcdp->declBus  (c+2543,"cache_simX dmem_controller icache genblk3[2] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller icache genblk3[3] bank_structure CACHE_SIZE",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[3] bank_structure CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4840,"cache_simX dmem_controller icache genblk3[3] bank_structure CACHE_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[3] bank_structure CACHE_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[3] bank_structure LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[3] bank_structure NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[3] bank_structure LOG_NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[3] bank_structure NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[3] bank_structure CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[3] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[3] bank_structure OFFSET_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[3] bank_structure OFFSET_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[3] bank_structure TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[3] bank_structure TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[3] bank_structure IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[3] bank_structure IND_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4844,"cache_simX dmem_controller icache genblk3[3] bank_structure ADDR_TAG_START",-1,31,0);
+	vcdp->declBus  (c+4845,"cache_simX dmem_controller icache genblk3[3] bank_structure ADDR_TAG_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[3] bank_structure ADDR_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4834,"cache_simX dmem_controller icache genblk3[3] bank_structure ADDR_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller icache genblk3[3] bank_structure ADDR_IND_START",-1,31,0);
+	vcdp->declBus  (c+4846,"cache_simX dmem_controller icache genblk3[3] bank_structure ADDR_IND_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[3] bank_structure CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[3] bank_structure SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[3] bank_structure RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller icache genblk3[3] bank_structure BLOCK_NUM_BITS",-1,31,0);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[3] bank_structure rst",-1);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[3] bank_structure clk",-1);
+	vcdp->declBus  (c+1185,"cache_simX dmem_controller icache genblk3[3] bank_structure state",-1,3,0);
+	vcdp->declBus  (c+323,"cache_simX dmem_controller icache genblk3[3] bank_structure actual_index",-1,4,0);
+	vcdp->declBus  (c+321,"cache_simX dmem_controller icache genblk3[3] bank_structure o_tag",-1,20,0);
+	vcdp->declBus  (c+322,"cache_simX dmem_controller icache genblk3[3] bank_structure block_offset",-1,1,0);
+	vcdp->declBus  (c+595,"cache_simX dmem_controller icache genblk3[3] bank_structure writedata",-1,31,0);
+	vcdp->declBit  (c+325,"cache_simX dmem_controller icache genblk3[3] bank_structure valid_in",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[3] bank_structure read_or_write",-1);
+	vcdp->declArray(c+4897,"cache_simX dmem_controller icache genblk3[3] bank_structure fetched_writedata",-1,127,0);
+	vcdp->declBus  (c+23,"cache_simX dmem_controller icache genblk3[3] bank_structure i_p_mem_read",-1,2,0);
+	vcdp->declBus  (c+4825,"cache_simX dmem_controller icache genblk3[3] bank_structure i_p_mem_write",-1,2,0);
+	vcdp->declBus  (c+320,"cache_simX dmem_controller icache genblk3[3] bank_structure byte_select",-1,1,0);
+	vcdp->declBus  (c+1184,"cache_simX dmem_controller icache genblk3[3] bank_structure evicted_way",-1,0,0);
+	vcdp->declBus  (c+596,"cache_simX dmem_controller icache genblk3[3] bank_structure readdata",-1,31,0);
+	vcdp->declBit  (c+597,"cache_simX dmem_controller icache genblk3[3] bank_structure hit",-1);
+	vcdp->declBit  (c+598,"cache_simX dmem_controller icache genblk3[3] bank_structure eviction_wb",-1);
+	vcdp->declBus  (c+599,"cache_simX dmem_controller icache genblk3[3] bank_structure eviction_addr",-1,31,0);
+	vcdp->declArray(c+600,"cache_simX dmem_controller icache genblk3[3] bank_structure data_evicted",-1,127,0);
+	vcdp->declArray(c+600,"cache_simX dmem_controller icache genblk3[3] bank_structure data_use",-1,127,0);
+	vcdp->declBus  (c+604,"cache_simX dmem_controller icache genblk3[3] bank_structure tag_use",-1,20,0);
+	vcdp->declBus  (c+604,"cache_simX dmem_controller icache genblk3[3] bank_structure eviction_tag",-1,20,0);
+	vcdp->declBit  (c+605,"cache_simX dmem_controller icache genblk3[3] bank_structure valid_use",-1);
+	vcdp->declBit  (c+598,"cache_simX dmem_controller icache genblk3[3] bank_structure dirty_use",-1);
+	vcdp->declBit  (c+606,"cache_simX dmem_controller icache genblk3[3] bank_structure access",-1);
+	vcdp->declBit  (c+607,"cache_simX dmem_controller icache genblk3[3] bank_structure write_from_mem",-1);
+	vcdp->declBit  (c+608,"cache_simX dmem_controller icache genblk3[3] bank_structure miss",-1);
+	vcdp->declBus  (c+1158,"cache_simX dmem_controller icache genblk3[3] bank_structure way_to_update",-1,0,0);
+	vcdp->declBit  (c+358,"cache_simX dmem_controller icache genblk3[3] bank_structure lw",-1);
+	vcdp->declBit  (c+359,"cache_simX dmem_controller icache genblk3[3] bank_structure lb",-1);
+	vcdp->declBit  (c+360,"cache_simX dmem_controller icache genblk3[3] bank_structure lh",-1);
+	vcdp->declBit  (c+361,"cache_simX dmem_controller icache genblk3[3] bank_structure lhu",-1);
+	vcdp->declBit  (c+362,"cache_simX dmem_controller icache genblk3[3] bank_structure lbu",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[3] bank_structure sw",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[3] bank_structure sb",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[3] bank_structure sh",-1);
+	vcdp->declBit  (c+609,"cache_simX dmem_controller icache genblk3[3] bank_structure b0",-1);
+	vcdp->declBit  (c+610,"cache_simX dmem_controller icache genblk3[3] bank_structure b1",-1);
+	vcdp->declBit  (c+611,"cache_simX dmem_controller icache genblk3[3] bank_structure b2",-1);
+	vcdp->declBit  (c+612,"cache_simX dmem_controller icache genblk3[3] bank_structure b3",-1);
+	vcdp->declBus  (c+613,"cache_simX dmem_controller icache genblk3[3] bank_structure data_unQual",-1,31,0);
+	vcdp->declBus  (c+614,"cache_simX dmem_controller icache genblk3[3] bank_structure lb_data",-1,31,0);
+	vcdp->declBus  (c+615,"cache_simX dmem_controller icache genblk3[3] bank_structure lh_data",-1,31,0);
+	vcdp->declBus  (c+616,"cache_simX dmem_controller icache genblk3[3] bank_structure lbu_data",-1,31,0);
+	vcdp->declBus  (c+617,"cache_simX dmem_controller icache genblk3[3] bank_structure lhu_data",-1,31,0);
+	vcdp->declBus  (c+613,"cache_simX dmem_controller icache genblk3[3] bank_structure lw_data",-1,31,0);
+	vcdp->declBus  (c+595,"cache_simX dmem_controller icache genblk3[3] bank_structure sw_data",-1,31,0);
+	vcdp->declBus  (c+618,"cache_simX dmem_controller icache genblk3[3] bank_structure sb_data",-1,31,0);
+	vcdp->declBus  (c+619,"cache_simX dmem_controller icache genblk3[3] bank_structure sh_data",-1,31,0);
+	vcdp->declBus  (c+595,"cache_simX dmem_controller icache genblk3[3] bank_structure use_write_data",-1,31,0);
+	vcdp->declBus  (c+620,"cache_simX dmem_controller icache genblk3[3] bank_structure data_Qual",-1,31,0);
+	vcdp->declBus  (c+621,"cache_simX dmem_controller icache genblk3[3] bank_structure sb_mask",-1,3,0);
+	vcdp->declBus  (c+622,"cache_simX dmem_controller icache genblk3[3] bank_structure sh_mask",-1,3,0);
+	vcdp->declBus  (c+623,"cache_simX dmem_controller icache genblk3[3] bank_structure we",-1,15,0);
+	vcdp->declArray(c+624,"cache_simX dmem_controller icache genblk3[3] bank_structure data_write",-1,127,0);
+	// Tracing: cache_simX dmem_controller icache genblk3[3] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[3] bank_structure genblk1[0] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[3] bank_structure genblk1[1] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[3] bank_structure genblk1[2] normal_write",-1);
+	vcdp->declBit  (c+4827,"cache_simX dmem_controller icache genblk3[3] bank_structure genblk1[3] normal_write",-1);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures rst",-1);
+	vcdp->declBit  (c+325,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures valid_in",-1);
+	vcdp->declBus  (c+1185,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures state",-1,3,0);
+	vcdp->declBus  (c+323,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures addr",-1,4,0);
+	vcdp->declBus  (c+623,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures we",-1,15,0);
+	vcdp->declBit  (c+607,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures evict",-1);
+	vcdp->declBus  (c+1158,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures way_to_update",-1,0,0);
+	vcdp->declArray(c+624,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+321,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+604,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+600,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+605,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures valid_use",-1);
+	vcdp->declBit  (c+598,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures dirty_use",-1);
+	vcdp->declQuad (c+628,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures tag_use_per_way",-1,41,0);
+	vcdp->declArray(c+630,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures data_use_per_way",-1,255,0);
+	vcdp->declBus  (c+638,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures valid_use_per_way",-1,1,0);
+	vcdp->declBus  (c+639,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures dirty_use_per_way",-1,1,0);
+	vcdp->declBus  (c+640,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures hit_per_way",-1,1,0);
+	vcdp->declBus  (c+641,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures we_per_way",-1,31,0);
+	vcdp->declArray(c+642,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures data_write_per_way",-1,255,0);
+	vcdp->declBus  (c+650,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures write_from_mem_per_way",-1,1,0);
+	vcdp->declBit  (c+651,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures invalid_found",-1);
+	vcdp->declBus  (c+652,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures way_index",-1,0,0);
+	vcdp->declBus  (c+653,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures invalid_index",-1,0,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+654,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures way_use_Qual",-1,0,0);
+	// Tracing: cache_simX dmem_controller icache genblk3[3] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures genblk1 valid_index N",-1,31,0);
+	vcdp->declBus  (c+655,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
+	vcdp->declBus  (c+653,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures genblk1 valid_index index",-1,0,0);
+	vcdp->declBit  (c+651,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures genblk1 valid_index found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures genblk1 valid_index i",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
+	vcdp->declBus  (c+640,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
+	vcdp->declBus  (c+652,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
+	vcdp->declBit  (c+656,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures genblk1 way_indexing found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures rst",-1);
+	vcdp->declBus  (c+323,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+657,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
+	vcdp->declBit  (c+658,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures evict",-1);
+	vcdp->declArray(c+659,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+321,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1095,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1096,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1100,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures valid_use",-1);
+	vcdp->declBit  (c+663,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
+	vcdp->declBit  (c+664,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
+	vcdp->declBit  (c+665,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
+	vcdp->declBit  (c+666,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
+	vcdp->declArray(c+2544,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+2548,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+2552,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+2556,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+2560,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+2564,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+2568,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+2572,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+2576,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+2580,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+2584,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+2588,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+2592,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+2596,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+2600,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+2604,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+2608,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+2612,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+2616,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+2620,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+2624,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+2628,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+2632,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+2636,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+2640,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+2644,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+2648,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+2652,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+2656,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+2660,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+2664,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+2668,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBus  (c+2672+i*1,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+2704+i*1,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+2736+i*1,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+2768,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
+	vcdp->declBus  (c+2769,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures rst",-1);
+	vcdp->declBus  (c+323,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+667,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
+	vcdp->declBit  (c+668,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures evict",-1);
+	vcdp->declArray(c+669,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+321,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1101,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1102,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1106,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures valid_use",-1);
+	vcdp->declBit  (c+673,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
+	vcdp->declBit  (c+674,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
+	vcdp->declBit  (c+675,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
+	vcdp->declBit  (c+676,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
+	vcdp->declArray(c+2770,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+2774,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+2778,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+2782,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+2786,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+2790,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+2794,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+2798,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+2802,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+2806,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+2810,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+2814,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+2818,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+2822,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+2826,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+2830,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+2834,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+2838,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+2842,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+2846,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+2850,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+2854,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+2858,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+2862,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+2866,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+2870,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+2874,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+2878,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+2882,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+2886,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+2890,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+2894,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBus  (c+2898+i*1,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+2930+i*1,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
+	{int i; for (i=0; i<32; i++) {
+		vcdp->declBit  (c+2962+i*1,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+2994,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
+	vcdp->declBus  (c+2995,"cache_simX dmem_controller icache genblk3[3] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_SIZE",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4840,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[0] bank_structure LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[0] bank_structure LOG_NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[0] bank_structure OFFSET_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[0] bank_structure OFFSET_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[0] bank_structure TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[0] bank_structure TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[0] bank_structure IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[0] bank_structure IND_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4844,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_TAG_START",-1,31,0);
+	vcdp->declBus  (c+4845,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_TAG_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4834,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_IND_START",-1,31,0);
+	vcdp->declBus  (c+4846,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_IND_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[0] bank_structure SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[0] bank_structure RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller dcache genblk3[0] bank_structure BLOCK_NUM_BITS",-1,31,0);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[0] bank_structure rst",-1);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[0] bank_structure clk",-1);
+	vcdp->declBus  (c+1178,"cache_simX dmem_controller dcache genblk3[0] bank_structure state",-1,3,0);
+	vcdp->declBus  (c+197,"cache_simX dmem_controller dcache genblk3[0] bank_structure actual_index",-1,4,0);
 	vcdp->declBus  (c+195,"cache_simX dmem_controller dcache genblk3[0] bank_structure o_tag",-1,20,0);
-	vcdp->declBus  (c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure block_offset",-1,1,0);
-	vcdp->declBus  (c+319,"cache_simX dmem_controller dcache genblk3[0] bank_structure writedata",-1,31,0);
-	vcdp->declBit  (c+197,"cache_simX dmem_controller dcache genblk3[0] bank_structure valid_in",-1);
+	vcdp->declBus  (c+196,"cache_simX dmem_controller dcache genblk3[0] bank_structure block_offset",-1,1,0);
+	vcdp->declBus  (c+677,"cache_simX dmem_controller dcache genblk3[0] bank_structure writedata",-1,31,0);
+	vcdp->declBit  (c+199,"cache_simX dmem_controller dcache genblk3[0] bank_structure valid_in",-1);
 	vcdp->declBit  (c+4,"cache_simX dmem_controller dcache genblk3[0] bank_structure read_or_write",-1);
-	vcdp->declArray(c+3139,"cache_simX dmem_controller dcache genblk3[0] bank_structure fetched_writedata",-1,127,0);
+	vcdp->declArray(c+4901,"cache_simX dmem_controller dcache genblk3[0] bank_structure fetched_writedata",-1,127,0);
 	vcdp->declBus  (c+9,"cache_simX dmem_controller dcache genblk3[0] bank_structure i_p_mem_read",-1,2,0);
 	vcdp->declBus  (c+10,"cache_simX dmem_controller dcache genblk3[0] bank_structure i_p_mem_write",-1,2,0);
 	vcdp->declBus  (c+194,"cache_simX dmem_controller dcache genblk3[0] bank_structure byte_select",-1,1,0);
-	vcdp->declBus  (c+722,"cache_simX dmem_controller dcache genblk3[0] bank_structure evicted_way",-1,0,0);
-	vcdp->declBus  (c+320,"cache_simX dmem_controller dcache genblk3[0] bank_structure readdata",-1,31,0);
-	vcdp->declBit  (c+321,"cache_simX dmem_controller dcache genblk3[0] bank_structure hit",-1);
-	vcdp->declBit  (c+616,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_wb",-1);
-	vcdp->declBus  (c+322,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_addr",-1,31,0);
-	vcdp->declArray(c+323,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_evicted",-1,127,0);
-	vcdp->declArray(c+323,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_use",-1,127,0);
-	vcdp->declBus  (c+327,"cache_simX dmem_controller dcache genblk3[0] bank_structure tag_use",-1,20,0);
-	vcdp->declBus  (c+327,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_tag",-1,20,0);
-	vcdp->declBit  (c+328,"cache_simX dmem_controller dcache genblk3[0] bank_structure valid_use",-1);
-	vcdp->declBit  (c+616,"cache_simX dmem_controller dcache genblk3[0] bank_structure dirty_use",-1);
-	vcdp->declBit  (c+329,"cache_simX dmem_controller dcache genblk3[0] bank_structure access",-1);
-	vcdp->declBit  (c+330,"cache_simX dmem_controller dcache genblk3[0] bank_structure write_from_mem",-1);
-	vcdp->declBit  (c+331,"cache_simX dmem_controller dcache genblk3[0] bank_structure miss",-1);
-	vcdp->declBus  (c+644,"cache_simX dmem_controller dcache genblk3[0] bank_structure way_to_update",-1,0,0);
-	vcdp->declBit  (c+332,"cache_simX dmem_controller dcache genblk3[0] bank_structure lw",-1);
-	vcdp->declBit  (c+333,"cache_simX dmem_controller dcache genblk3[0] bank_structure lb",-1);
-	vcdp->declBit  (c+334,"cache_simX dmem_controller dcache genblk3[0] bank_structure lh",-1);
-	vcdp->declBit  (c+335,"cache_simX dmem_controller dcache genblk3[0] bank_structure lhu",-1);
-	vcdp->declBit  (c+336,"cache_simX dmem_controller dcache genblk3[0] bank_structure lbu",-1);
-	vcdp->declBit  (c+337,"cache_simX dmem_controller dcache genblk3[0] bank_structure sw",-1);
-	vcdp->declBit  (c+338,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb",-1);
-	vcdp->declBit  (c+339,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh",-1);
-	vcdp->declBit  (c+340,"cache_simX dmem_controller dcache genblk3[0] bank_structure b0",-1);
-	vcdp->declBit  (c+341,"cache_simX dmem_controller dcache genblk3[0] bank_structure b1",-1);
-	vcdp->declBit  (c+342,"cache_simX dmem_controller dcache genblk3[0] bank_structure b2",-1);
-	vcdp->declBit  (c+343,"cache_simX dmem_controller dcache genblk3[0] bank_structure b3",-1);
-	vcdp->declBus  (c+344,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_unQual",-1,31,0);
-	vcdp->declBus  (c+345,"cache_simX dmem_controller dcache genblk3[0] bank_structure lb_data",-1,31,0);
-	vcdp->declBus  (c+346,"cache_simX dmem_controller dcache genblk3[0] bank_structure lh_data",-1,31,0);
-	vcdp->declBus  (c+347,"cache_simX dmem_controller dcache genblk3[0] bank_structure lbu_data",-1,31,0);
-	vcdp->declBus  (c+348,"cache_simX dmem_controller dcache genblk3[0] bank_structure lhu_data",-1,31,0);
-	vcdp->declBus  (c+344,"cache_simX dmem_controller dcache genblk3[0] bank_structure lw_data",-1,31,0);
-	vcdp->declBus  (c+319,"cache_simX dmem_controller dcache genblk3[0] bank_structure sw_data",-1,31,0);
-	vcdp->declBus  (c+349,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb_data",-1,31,0);
-	vcdp->declBus  (c+350,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh_data",-1,31,0);
-	vcdp->declBus  (c+351,"cache_simX dmem_controller dcache genblk3[0] bank_structure use_write_data",-1,31,0);
-	vcdp->declBus  (c+352,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_Qual",-1,31,0);
-	vcdp->declBus  (c+353,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb_mask",-1,3,0);
-	vcdp->declBus  (c+354,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh_mask",-1,3,0);
-	vcdp->declBus  (c+355,"cache_simX dmem_controller dcache genblk3[0] bank_structure we",-1,15,0);
-	vcdp->declArray(c+356,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_write",-1,127,0);
+	vcdp->declBus  (c+1177,"cache_simX dmem_controller dcache genblk3[0] bank_structure evicted_way",-1,0,0);
+	vcdp->declBus  (c+678,"cache_simX dmem_controller dcache genblk3[0] bank_structure readdata",-1,31,0);
+	vcdp->declBit  (c+679,"cache_simX dmem_controller dcache genblk3[0] bank_structure hit",-1);
+	vcdp->declBit  (c+680,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_wb",-1);
+	vcdp->declBus  (c+681,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_addr",-1,31,0);
+	vcdp->declArray(c+682,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_evicted",-1,127,0);
+	vcdp->declArray(c+682,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_use",-1,127,0);
+	vcdp->declBus  (c+686,"cache_simX dmem_controller dcache genblk3[0] bank_structure tag_use",-1,20,0);
+	vcdp->declBus  (c+686,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_tag",-1,20,0);
+	vcdp->declBit  (c+687,"cache_simX dmem_controller dcache genblk3[0] bank_structure valid_use",-1);
+	vcdp->declBit  (c+680,"cache_simX dmem_controller dcache genblk3[0] bank_structure dirty_use",-1);
+	vcdp->declBit  (c+688,"cache_simX dmem_controller dcache genblk3[0] bank_structure access",-1);
+	vcdp->declBit  (c+689,"cache_simX dmem_controller dcache genblk3[0] bank_structure write_from_mem",-1);
+	vcdp->declBit  (c+690,"cache_simX dmem_controller dcache genblk3[0] bank_structure miss",-1);
+	vcdp->declBus  (c+1159,"cache_simX dmem_controller dcache genblk3[0] bank_structure way_to_update",-1,0,0);
+	vcdp->declBit  (c+691,"cache_simX dmem_controller dcache genblk3[0] bank_structure lw",-1);
+	vcdp->declBit  (c+692,"cache_simX dmem_controller dcache genblk3[0] bank_structure lb",-1);
+	vcdp->declBit  (c+693,"cache_simX dmem_controller dcache genblk3[0] bank_structure lh",-1);
+	vcdp->declBit  (c+694,"cache_simX dmem_controller dcache genblk3[0] bank_structure lhu",-1);
+	vcdp->declBit  (c+695,"cache_simX dmem_controller dcache genblk3[0] bank_structure lbu",-1);
+	vcdp->declBit  (c+696,"cache_simX dmem_controller dcache genblk3[0] bank_structure sw",-1);
+	vcdp->declBit  (c+697,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb",-1);
+	vcdp->declBit  (c+698,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh",-1);
+	vcdp->declBit  (c+699,"cache_simX dmem_controller dcache genblk3[0] bank_structure b0",-1);
+	vcdp->declBit  (c+700,"cache_simX dmem_controller dcache genblk3[0] bank_structure b1",-1);
+	vcdp->declBit  (c+701,"cache_simX dmem_controller dcache genblk3[0] bank_structure b2",-1);
+	vcdp->declBit  (c+702,"cache_simX dmem_controller dcache genblk3[0] bank_structure b3",-1);
+	vcdp->declBus  (c+703,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_unQual",-1,31,0);
+	vcdp->declBus  (c+704,"cache_simX dmem_controller dcache genblk3[0] bank_structure lb_data",-1,31,0);
+	vcdp->declBus  (c+705,"cache_simX dmem_controller dcache genblk3[0] bank_structure lh_data",-1,31,0);
+	vcdp->declBus  (c+706,"cache_simX dmem_controller dcache genblk3[0] bank_structure lbu_data",-1,31,0);
+	vcdp->declBus  (c+707,"cache_simX dmem_controller dcache genblk3[0] bank_structure lhu_data",-1,31,0);
+	vcdp->declBus  (c+703,"cache_simX dmem_controller dcache genblk3[0] bank_structure lw_data",-1,31,0);
+	vcdp->declBus  (c+677,"cache_simX dmem_controller dcache genblk3[0] bank_structure sw_data",-1,31,0);
+	vcdp->declBus  (c+708,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb_data",-1,31,0);
+	vcdp->declBus  (c+709,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh_data",-1,31,0);
+	vcdp->declBus  (c+710,"cache_simX dmem_controller dcache genblk3[0] bank_structure use_write_data",-1,31,0);
+	vcdp->declBus  (c+711,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_Qual",-1,31,0);
+	vcdp->declBus  (c+712,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb_mask",-1,3,0);
+	vcdp->declBus  (c+713,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh_mask",-1,3,0);
+	vcdp->declBus  (c+714,"cache_simX dmem_controller dcache genblk3[0] bank_structure we",-1,15,0);
+	vcdp->declArray(c+715,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_write",-1,127,0);
 	// Tracing: cache_simX dmem_controller dcache genblk3[0] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203
-	vcdp->declBit  (c+360,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[0] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[1] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[2] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[3] normal_write",-1);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures rst",-1);
-	vcdp->declBit  (c+197,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_in",-1);
-	vcdp->declBus  (c+723,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures state",-1,3,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures addr",-1,4,0);
-	vcdp->declBus  (c+355,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures we",-1,15,0);
-	vcdp->declBit  (c+330,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures evict",-1);
-	vcdp->declBus  (c+644,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_to_update",-1,0,0);
-	vcdp->declArray(c+356,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_write",-1,127,0);
+	vcdp->declBit  (c+719,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[0] normal_write",-1);
+	vcdp->declBit  (c+720,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[1] normal_write",-1);
+	vcdp->declBit  (c+721,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[2] normal_write",-1);
+	vcdp->declBit  (c+722,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[3] normal_write",-1);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures rst",-1);
+	vcdp->declBit  (c+199,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_in",-1);
+	vcdp->declBus  (c+1178,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures state",-1,3,0);
+	vcdp->declBus  (c+197,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures addr",-1,4,0);
+	vcdp->declBus  (c+714,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures we",-1,15,0);
+	vcdp->declBit  (c+689,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures evict",-1);
+	vcdp->declBus  (c+1159,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_to_update",-1,0,0);
+	vcdp->declArray(c+715,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_write",-1,127,0);
 	vcdp->declBus  (c+195,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+327,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+323,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+328,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_use",-1);
-	vcdp->declBit  (c+616,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures dirty_use",-1);
-	vcdp->declQuad (c+645,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures tag_use_per_way",-1,41,0);
-	vcdp->declArray(c+647,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_use_per_way",-1,255,0);
-	vcdp->declBus  (c+655,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_use_per_way",-1,1,0);
-	vcdp->declBus  (c+656,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures dirty_use_per_way",-1,1,0);
-	vcdp->declBus  (c+361,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures hit_per_way",-1,1,0);
-	vcdp->declBus  (c+362,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures we_per_way",-1,31,0);
-	vcdp->declArray(c+363,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_write_per_way",-1,255,0);
-	vcdp->declBus  (c+371,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures write_from_mem_per_way",-1,1,0);
-	vcdp->declBit  (c+657,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures invalid_found",-1);
-	vcdp->declBus  (c+372,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_index",-1,0,0);
-	vcdp->declBus  (c+658,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures invalid_index",-1,0,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBus  (c+373,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_use_Qual",-1,0,0);
+	vcdp->declBus  (c+686,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+682,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+687,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_use",-1);
+	vcdp->declBit  (c+680,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures dirty_use",-1);
+	vcdp->declQuad (c+723,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures tag_use_per_way",-1,41,0);
+	vcdp->declArray(c+725,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_use_per_way",-1,255,0);
+	vcdp->declBus  (c+733,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_use_per_way",-1,1,0);
+	vcdp->declBus  (c+734,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures dirty_use_per_way",-1,1,0);
+	vcdp->declBus  (c+735,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures hit_per_way",-1,1,0);
+	vcdp->declBus  (c+736,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures we_per_way",-1,31,0);
+	vcdp->declArray(c+737,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_write_per_way",-1,255,0);
+	vcdp->declBus  (c+745,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures write_from_mem_per_way",-1,1,0);
+	vcdp->declBit  (c+746,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures invalid_found",-1);
+	vcdp->declBus  (c+747,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_index",-1,0,0);
+	vcdp->declBus  (c+748,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures invalid_index",-1,0,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+749,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_use_Qual",-1,0,0);
 	// Tracing: cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index N",-1,31,0);
-	vcdp->declBus  (c+659,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
-	vcdp->declBus  (c+658,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index index",-1,0,0);
-	vcdp->declBit  (c+657,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index found",-1);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index i",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
-	vcdp->declBus  (c+361,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
-	vcdp->declBus  (c+372,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
-	vcdp->declBit  (c+374,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing found",-1);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures rst",-1);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
-	vcdp->declBus  (c+375,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
-	vcdp->declBit  (c+376,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures evict",-1);
-	vcdp->declArray(c+377,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index N",-1,31,0);
+	vcdp->declBus  (c+750,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
+	vcdp->declBus  (c+748,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index index",-1,0,0);
+	vcdp->declBit  (c+746,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index i",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
+	vcdp->declBus  (c+735,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
+	vcdp->declBus  (c+747,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
+	vcdp->declBit  (c+751,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures rst",-1);
+	vcdp->declBus  (c+197,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+752,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
+	vcdp->declBit  (c+753,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures evict",-1);
+	vcdp->declArray(c+754,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
 	vcdp->declBus  (c+195,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+1199,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+1200,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+1204,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures valid_use",-1);
-	vcdp->declBit  (c+1205,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
-	vcdp->declBit  (c+381,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
-	vcdp->declBit  (c+617,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
-	vcdp->declBit  (c+382,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
-	vcdp->declArray(c+1206,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
-	vcdp->declArray(c+1210,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
-	vcdp->declArray(c+1214,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
-	vcdp->declArray(c+1218,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
-	vcdp->declArray(c+1222,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
-	vcdp->declArray(c+1226,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
-	vcdp->declArray(c+1230,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
-	vcdp->declArray(c+1234,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
-	vcdp->declArray(c+1238,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
-	vcdp->declArray(c+1242,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
-	vcdp->declArray(c+1246,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
-	vcdp->declArray(c+1250,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
-	vcdp->declArray(c+1254,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
-	vcdp->declArray(c+1258,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
-	vcdp->declArray(c+1262,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
-	vcdp->declArray(c+1266,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
-	vcdp->declArray(c+1270,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
-	vcdp->declArray(c+1274,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
-	vcdp->declArray(c+1278,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
-	vcdp->declArray(c+1282,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
-	vcdp->declArray(c+1286,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
-	vcdp->declArray(c+1290,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
-	vcdp->declArray(c+1294,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
-	vcdp->declArray(c+1298,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
-	vcdp->declArray(c+1302,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
-	vcdp->declArray(c+1306,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
-	vcdp->declArray(c+1310,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
-	vcdp->declArray(c+1314,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
-	vcdp->declArray(c+1318,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
-	vcdp->declArray(c+1322,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
-	vcdp->declArray(c+1326,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
-	vcdp->declArray(c+1330,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
+	vcdp->declBus  (c+1107,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1108,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1112,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures valid_use",-1);
+	vcdp->declBit  (c+758,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
+	vcdp->declBit  (c+759,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
+	vcdp->declBit  (c+760,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
+	vcdp->declBit  (c+761,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
+	vcdp->declArray(c+2996,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+3000,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+3004,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+3008,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+3012,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+3016,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+3020,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+3024,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+3028,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+3032,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+3036,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+3040,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+3044,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+3048,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+3052,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+3056,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+3060,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+3064,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+3068,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+3072,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+3076,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+3080,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+3084,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+3092,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+3096,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+3100,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+3104,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+3108,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+3112,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+3116,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+3120,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBus  (c+1334+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
+		vcdp->declBus  (c+3124+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+1366+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
+		vcdp->declBit  (c+3156+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+1398+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
-	vcdp->declBus  (c+1430,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
-	vcdp->declBus  (c+1431,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures rst",-1);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
-	vcdp->declBus  (c+383,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
-	vcdp->declBit  (c+384,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures evict",-1);
-	vcdp->declArray(c+385,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
+		vcdp->declBit  (c+3188+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+3220,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
+	vcdp->declBus  (c+3221,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures rst",-1);
+	vcdp->declBus  (c+197,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+762,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
+	vcdp->declBit  (c+763,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures evict",-1);
+	vcdp->declArray(c+764,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
 	vcdp->declBus  (c+195,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+1432,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+1433,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+1437,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures valid_use",-1);
-	vcdp->declBit  (c+1438,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
-	vcdp->declBit  (c+389,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
-	vcdp->declBit  (c+618,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
-	vcdp->declBit  (c+390,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
-	vcdp->declArray(c+1439,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
-	vcdp->declArray(c+1443,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
-	vcdp->declArray(c+1447,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
-	vcdp->declArray(c+1451,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
-	vcdp->declArray(c+1455,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
-	vcdp->declArray(c+1459,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
-	vcdp->declArray(c+1463,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
-	vcdp->declArray(c+1467,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
-	vcdp->declArray(c+1471,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
-	vcdp->declArray(c+1475,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
-	vcdp->declArray(c+1479,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
-	vcdp->declArray(c+1483,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
-	vcdp->declArray(c+1487,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
-	vcdp->declArray(c+1491,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
-	vcdp->declArray(c+1495,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
-	vcdp->declArray(c+1499,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
-	vcdp->declArray(c+1503,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
-	vcdp->declArray(c+1507,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
-	vcdp->declArray(c+1511,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
-	vcdp->declArray(c+1515,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
-	vcdp->declArray(c+1519,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
-	vcdp->declArray(c+1523,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
-	vcdp->declArray(c+1527,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
-	vcdp->declArray(c+1531,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
-	vcdp->declArray(c+1535,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
-	vcdp->declArray(c+1539,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
-	vcdp->declArray(c+1543,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
-	vcdp->declArray(c+1547,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
-	vcdp->declArray(c+1551,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
-	vcdp->declArray(c+1555,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
-	vcdp->declArray(c+1559,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
-	vcdp->declArray(c+1563,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
+	vcdp->declBus  (c+1113,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1114,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1118,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures valid_use",-1);
+	vcdp->declBit  (c+768,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
+	vcdp->declBit  (c+769,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
+	vcdp->declBit  (c+770,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
+	vcdp->declBit  (c+771,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
+	vcdp->declArray(c+3222,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+3226,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+3230,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+3234,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+3238,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+3242,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+3246,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+3250,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+3254,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+3258,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+3262,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+3266,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+3270,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+3274,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+3278,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+3282,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+3286,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+3290,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+3294,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+3298,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+3302,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+3306,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+3310,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+3314,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+3318,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+3322,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+3326,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+3330,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+3334,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+3338,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+3342,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+3346,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBus  (c+1567+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
+		vcdp->declBus  (c+3350+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+1599+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
+		vcdp->declBit  (c+3382+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+1631+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
-	vcdp->declBus  (c+1663,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
-	vcdp->declBus  (c+1664,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
-	vcdp->declBus  (c+3098,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_SIZE",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3099,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_BANKS",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure LOG_NUM_BANKS",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure LOG_NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure OFFSET_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[1] bank_structure OFFSET_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure IND_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3103,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_TAG_START",-1,31,0);
-	vcdp->declBus  (c+3104,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_TAG_END",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_OFFSET_START",-1,31,0);
-	vcdp->declBus  (c+3093,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_OFFSET_END",-1,31,0);
-	vcdp->declBus  (c+3094,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_IND_START",-1,31,0);
-	vcdp->declBus  (c+3105,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_IND_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[1] bank_structure SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBus  (c+3094,"cache_simX dmem_controller dcache genblk3[1] bank_structure BLOCK_NUM_BITS",-1,31,0);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[1] bank_structure rst",-1);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[1] bank_structure clk",-1);
-	vcdp->declBus  (c+723,"cache_simX dmem_controller dcache genblk3[1] bank_structure state",-1,3,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[1] bank_structure actual_index",-1,4,0);
-	vcdp->declBus  (c+200,"cache_simX dmem_controller dcache genblk3[1] bank_structure o_tag",-1,20,0);
-	vcdp->declBus  (c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure block_offset",-1,1,0);
-	vcdp->declBus  (c+391,"cache_simX dmem_controller dcache genblk3[1] bank_structure writedata",-1,31,0);
-	vcdp->declBit  (c+202,"cache_simX dmem_controller dcache genblk3[1] bank_structure valid_in",-1);
+		vcdp->declBit  (c+3414+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+3446,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
+	vcdp->declBus  (c+3447,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_SIZE",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4840,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[1] bank_structure LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[1] bank_structure LOG_NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[1] bank_structure OFFSET_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[1] bank_structure OFFSET_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[1] bank_structure TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[1] bank_structure TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[1] bank_structure IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[1] bank_structure IND_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4844,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_TAG_START",-1,31,0);
+	vcdp->declBus  (c+4845,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_TAG_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4834,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_IND_START",-1,31,0);
+	vcdp->declBus  (c+4846,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_IND_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[1] bank_structure SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[1] bank_structure RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller dcache genblk3[1] bank_structure BLOCK_NUM_BITS",-1,31,0);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[1] bank_structure rst",-1);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[1] bank_structure clk",-1);
+	vcdp->declBus  (c+1178,"cache_simX dmem_controller dcache genblk3[1] bank_structure state",-1,3,0);
+	vcdp->declBus  (c+204,"cache_simX dmem_controller dcache genblk3[1] bank_structure actual_index",-1,4,0);
+	vcdp->declBus  (c+202,"cache_simX dmem_controller dcache genblk3[1] bank_structure o_tag",-1,20,0);
+	vcdp->declBus  (c+203,"cache_simX dmem_controller dcache genblk3[1] bank_structure block_offset",-1,1,0);
+	vcdp->declBus  (c+772,"cache_simX dmem_controller dcache genblk3[1] bank_structure writedata",-1,31,0);
+	vcdp->declBit  (c+206,"cache_simX dmem_controller dcache genblk3[1] bank_structure valid_in",-1);
 	vcdp->declBit  (c+4,"cache_simX dmem_controller dcache genblk3[1] bank_structure read_or_write",-1);
-	vcdp->declArray(c+3143,"cache_simX dmem_controller dcache genblk3[1] bank_structure fetched_writedata",-1,127,0);
+	vcdp->declArray(c+4905,"cache_simX dmem_controller dcache genblk3[1] bank_structure fetched_writedata",-1,127,0);
 	vcdp->declBus  (c+9,"cache_simX dmem_controller dcache genblk3[1] bank_structure i_p_mem_read",-1,2,0);
 	vcdp->declBus  (c+10,"cache_simX dmem_controller dcache genblk3[1] bank_structure i_p_mem_write",-1,2,0);
-	vcdp->declBus  (c+199,"cache_simX dmem_controller dcache genblk3[1] bank_structure byte_select",-1,1,0);
-	vcdp->declBus  (c+722,"cache_simX dmem_controller dcache genblk3[1] bank_structure evicted_way",-1,0,0);
-	vcdp->declBus  (c+392,"cache_simX dmem_controller dcache genblk3[1] bank_structure readdata",-1,31,0);
-	vcdp->declBit  (c+393,"cache_simX dmem_controller dcache genblk3[1] bank_structure hit",-1);
-	vcdp->declBit  (c+619,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_wb",-1);
-	vcdp->declBus  (c+394,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_addr",-1,31,0);
-	vcdp->declArray(c+395,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_evicted",-1,127,0);
-	vcdp->declArray(c+395,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_use",-1,127,0);
-	vcdp->declBus  (c+399,"cache_simX dmem_controller dcache genblk3[1] bank_structure tag_use",-1,20,0);
-	vcdp->declBus  (c+399,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_tag",-1,20,0);
-	vcdp->declBit  (c+400,"cache_simX dmem_controller dcache genblk3[1] bank_structure valid_use",-1);
-	vcdp->declBit  (c+619,"cache_simX dmem_controller dcache genblk3[1] bank_structure dirty_use",-1);
-	vcdp->declBit  (c+401,"cache_simX dmem_controller dcache genblk3[1] bank_structure access",-1);
-	vcdp->declBit  (c+402,"cache_simX dmem_controller dcache genblk3[1] bank_structure write_from_mem",-1);
-	vcdp->declBit  (c+403,"cache_simX dmem_controller dcache genblk3[1] bank_structure miss",-1);
-	vcdp->declBus  (c+660,"cache_simX dmem_controller dcache genblk3[1] bank_structure way_to_update",-1,0,0);
-	vcdp->declBit  (c+332,"cache_simX dmem_controller dcache genblk3[1] bank_structure lw",-1);
-	vcdp->declBit  (c+333,"cache_simX dmem_controller dcache genblk3[1] bank_structure lb",-1);
-	vcdp->declBit  (c+334,"cache_simX dmem_controller dcache genblk3[1] bank_structure lh",-1);
-	vcdp->declBit  (c+335,"cache_simX dmem_controller dcache genblk3[1] bank_structure lhu",-1);
-	vcdp->declBit  (c+336,"cache_simX dmem_controller dcache genblk3[1] bank_structure lbu",-1);
-	vcdp->declBit  (c+337,"cache_simX dmem_controller dcache genblk3[1] bank_structure sw",-1);
-	vcdp->declBit  (c+338,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb",-1);
-	vcdp->declBit  (c+339,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh",-1);
-	vcdp->declBit  (c+404,"cache_simX dmem_controller dcache genblk3[1] bank_structure b0",-1);
-	vcdp->declBit  (c+405,"cache_simX dmem_controller dcache genblk3[1] bank_structure b1",-1);
-	vcdp->declBit  (c+406,"cache_simX dmem_controller dcache genblk3[1] bank_structure b2",-1);
-	vcdp->declBit  (c+407,"cache_simX dmem_controller dcache genblk3[1] bank_structure b3",-1);
-	vcdp->declBus  (c+408,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_unQual",-1,31,0);
-	vcdp->declBus  (c+409,"cache_simX dmem_controller dcache genblk3[1] bank_structure lb_data",-1,31,0);
-	vcdp->declBus  (c+410,"cache_simX dmem_controller dcache genblk3[1] bank_structure lh_data",-1,31,0);
-	vcdp->declBus  (c+411,"cache_simX dmem_controller dcache genblk3[1] bank_structure lbu_data",-1,31,0);
-	vcdp->declBus  (c+412,"cache_simX dmem_controller dcache genblk3[1] bank_structure lhu_data",-1,31,0);
-	vcdp->declBus  (c+408,"cache_simX dmem_controller dcache genblk3[1] bank_structure lw_data",-1,31,0);
-	vcdp->declBus  (c+391,"cache_simX dmem_controller dcache genblk3[1] bank_structure sw_data",-1,31,0);
-	vcdp->declBus  (c+413,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb_data",-1,31,0);
-	vcdp->declBus  (c+414,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh_data",-1,31,0);
-	vcdp->declBus  (c+415,"cache_simX dmem_controller dcache genblk3[1] bank_structure use_write_data",-1,31,0);
-	vcdp->declBus  (c+416,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_Qual",-1,31,0);
-	vcdp->declBus  (c+417,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb_mask",-1,3,0);
-	vcdp->declBus  (c+418,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh_mask",-1,3,0);
-	vcdp->declBus  (c+419,"cache_simX dmem_controller dcache genblk3[1] bank_structure we",-1,15,0);
-	vcdp->declArray(c+420,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_write",-1,127,0);
+	vcdp->declBus  (c+201,"cache_simX dmem_controller dcache genblk3[1] bank_structure byte_select",-1,1,0);
+	vcdp->declBus  (c+1177,"cache_simX dmem_controller dcache genblk3[1] bank_structure evicted_way",-1,0,0);
+	vcdp->declBus  (c+773,"cache_simX dmem_controller dcache genblk3[1] bank_structure readdata",-1,31,0);
+	vcdp->declBit  (c+774,"cache_simX dmem_controller dcache genblk3[1] bank_structure hit",-1);
+	vcdp->declBit  (c+775,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_wb",-1);
+	vcdp->declBus  (c+776,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_addr",-1,31,0);
+	vcdp->declArray(c+777,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_evicted",-1,127,0);
+	vcdp->declArray(c+777,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_use",-1,127,0);
+	vcdp->declBus  (c+781,"cache_simX dmem_controller dcache genblk3[1] bank_structure tag_use",-1,20,0);
+	vcdp->declBus  (c+781,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_tag",-1,20,0);
+	vcdp->declBit  (c+782,"cache_simX dmem_controller dcache genblk3[1] bank_structure valid_use",-1);
+	vcdp->declBit  (c+775,"cache_simX dmem_controller dcache genblk3[1] bank_structure dirty_use",-1);
+	vcdp->declBit  (c+783,"cache_simX dmem_controller dcache genblk3[1] bank_structure access",-1);
+	vcdp->declBit  (c+784,"cache_simX dmem_controller dcache genblk3[1] bank_structure write_from_mem",-1);
+	vcdp->declBit  (c+785,"cache_simX dmem_controller dcache genblk3[1] bank_structure miss",-1);
+	vcdp->declBus  (c+1160,"cache_simX dmem_controller dcache genblk3[1] bank_structure way_to_update",-1,0,0);
+	vcdp->declBit  (c+691,"cache_simX dmem_controller dcache genblk3[1] bank_structure lw",-1);
+	vcdp->declBit  (c+692,"cache_simX dmem_controller dcache genblk3[1] bank_structure lb",-1);
+	vcdp->declBit  (c+693,"cache_simX dmem_controller dcache genblk3[1] bank_structure lh",-1);
+	vcdp->declBit  (c+694,"cache_simX dmem_controller dcache genblk3[1] bank_structure lhu",-1);
+	vcdp->declBit  (c+695,"cache_simX dmem_controller dcache genblk3[1] bank_structure lbu",-1);
+	vcdp->declBit  (c+696,"cache_simX dmem_controller dcache genblk3[1] bank_structure sw",-1);
+	vcdp->declBit  (c+697,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb",-1);
+	vcdp->declBit  (c+698,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh",-1);
+	vcdp->declBit  (c+786,"cache_simX dmem_controller dcache genblk3[1] bank_structure b0",-1);
+	vcdp->declBit  (c+787,"cache_simX dmem_controller dcache genblk3[1] bank_structure b1",-1);
+	vcdp->declBit  (c+788,"cache_simX dmem_controller dcache genblk3[1] bank_structure b2",-1);
+	vcdp->declBit  (c+789,"cache_simX dmem_controller dcache genblk3[1] bank_structure b3",-1);
+	vcdp->declBus  (c+790,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_unQual",-1,31,0);
+	vcdp->declBus  (c+791,"cache_simX dmem_controller dcache genblk3[1] bank_structure lb_data",-1,31,0);
+	vcdp->declBus  (c+792,"cache_simX dmem_controller dcache genblk3[1] bank_structure lh_data",-1,31,0);
+	vcdp->declBus  (c+793,"cache_simX dmem_controller dcache genblk3[1] bank_structure lbu_data",-1,31,0);
+	vcdp->declBus  (c+794,"cache_simX dmem_controller dcache genblk3[1] bank_structure lhu_data",-1,31,0);
+	vcdp->declBus  (c+790,"cache_simX dmem_controller dcache genblk3[1] bank_structure lw_data",-1,31,0);
+	vcdp->declBus  (c+772,"cache_simX dmem_controller dcache genblk3[1] bank_structure sw_data",-1,31,0);
+	vcdp->declBus  (c+795,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb_data",-1,31,0);
+	vcdp->declBus  (c+796,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh_data",-1,31,0);
+	vcdp->declBus  (c+797,"cache_simX dmem_controller dcache genblk3[1] bank_structure use_write_data",-1,31,0);
+	vcdp->declBus  (c+798,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_Qual",-1,31,0);
+	vcdp->declBus  (c+799,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb_mask",-1,3,0);
+	vcdp->declBus  (c+800,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh_mask",-1,3,0);
+	vcdp->declBus  (c+801,"cache_simX dmem_controller dcache genblk3[1] bank_structure we",-1,15,0);
+	vcdp->declArray(c+802,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_write",-1,127,0);
 	// Tracing: cache_simX dmem_controller dcache genblk3[1] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203
-	vcdp->declBit  (c+424,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[0] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[1] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[2] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[3] normal_write",-1);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures rst",-1);
-	vcdp->declBit  (c+202,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_in",-1);
-	vcdp->declBus  (c+723,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures state",-1,3,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures addr",-1,4,0);
-	vcdp->declBus  (c+419,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures we",-1,15,0);
-	vcdp->declBit  (c+402,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures evict",-1);
-	vcdp->declBus  (c+660,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_to_update",-1,0,0);
-	vcdp->declArray(c+420,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+200,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+399,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+395,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+400,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_use",-1);
-	vcdp->declBit  (c+619,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures dirty_use",-1);
-	vcdp->declQuad (c+661,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_use_per_way",-1,41,0);
-	vcdp->declArray(c+663,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_use_per_way",-1,255,0);
-	vcdp->declBus  (c+671,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_use_per_way",-1,1,0);
-	vcdp->declBus  (c+672,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures dirty_use_per_way",-1,1,0);
-	vcdp->declBus  (c+425,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures hit_per_way",-1,1,0);
-	vcdp->declBus  (c+426,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures we_per_way",-1,31,0);
-	vcdp->declArray(c+427,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_write_per_way",-1,255,0);
-	vcdp->declBus  (c+435,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures write_from_mem_per_way",-1,1,0);
-	vcdp->declBit  (c+673,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures invalid_found",-1);
-	vcdp->declBus  (c+436,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_index",-1,0,0);
-	vcdp->declBus  (c+674,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures invalid_index",-1,0,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBus  (c+437,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_use_Qual",-1,0,0);
+	vcdp->declBit  (c+806,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[0] normal_write",-1);
+	vcdp->declBit  (c+807,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[1] normal_write",-1);
+	vcdp->declBit  (c+808,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[2] normal_write",-1);
+	vcdp->declBit  (c+809,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[3] normal_write",-1);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures rst",-1);
+	vcdp->declBit  (c+206,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_in",-1);
+	vcdp->declBus  (c+1178,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures state",-1,3,0);
+	vcdp->declBus  (c+204,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures addr",-1,4,0);
+	vcdp->declBus  (c+801,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures we",-1,15,0);
+	vcdp->declBit  (c+784,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures evict",-1);
+	vcdp->declBus  (c+1160,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_to_update",-1,0,0);
+	vcdp->declArray(c+802,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+202,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+781,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+777,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+782,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_use",-1);
+	vcdp->declBit  (c+775,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures dirty_use",-1);
+	vcdp->declQuad (c+810,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_use_per_way",-1,41,0);
+	vcdp->declArray(c+812,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_use_per_way",-1,255,0);
+	vcdp->declBus  (c+820,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_use_per_way",-1,1,0);
+	vcdp->declBus  (c+821,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures dirty_use_per_way",-1,1,0);
+	vcdp->declBus  (c+822,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures hit_per_way",-1,1,0);
+	vcdp->declBus  (c+823,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures we_per_way",-1,31,0);
+	vcdp->declArray(c+824,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_write_per_way",-1,255,0);
+	vcdp->declBus  (c+832,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures write_from_mem_per_way",-1,1,0);
+	vcdp->declBit  (c+833,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures invalid_found",-1);
+	vcdp->declBus  (c+834,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_index",-1,0,0);
+	vcdp->declBus  (c+835,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures invalid_index",-1,0,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+836,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_use_Qual",-1,0,0);
 	// Tracing: cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index N",-1,31,0);
-	vcdp->declBus  (c+675,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
-	vcdp->declBus  (c+674,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index index",-1,0,0);
-	vcdp->declBit  (c+673,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index found",-1);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index i",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
-	vcdp->declBus  (c+425,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
-	vcdp->declBus  (c+436,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
-	vcdp->declBit  (c+438,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing found",-1);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures rst",-1);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
-	vcdp->declBus  (c+439,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
-	vcdp->declBit  (c+440,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures evict",-1);
-	vcdp->declArray(c+441,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+200,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+1665,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+1666,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+1670,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures valid_use",-1);
-	vcdp->declBit  (c+1671,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
-	vcdp->declBit  (c+445,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
-	vcdp->declBit  (c+620,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
-	vcdp->declBit  (c+446,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
-	vcdp->declArray(c+1672,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
-	vcdp->declArray(c+1676,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
-	vcdp->declArray(c+1680,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
-	vcdp->declArray(c+1684,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
-	vcdp->declArray(c+1688,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
-	vcdp->declArray(c+1692,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
-	vcdp->declArray(c+1696,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
-	vcdp->declArray(c+1700,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
-	vcdp->declArray(c+1704,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
-	vcdp->declArray(c+1708,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
-	vcdp->declArray(c+1712,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
-	vcdp->declArray(c+1716,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
-	vcdp->declArray(c+1720,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
-	vcdp->declArray(c+1724,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
-	vcdp->declArray(c+1728,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
-	vcdp->declArray(c+1732,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
-	vcdp->declArray(c+1736,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
-	vcdp->declArray(c+1740,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
-	vcdp->declArray(c+1744,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
-	vcdp->declArray(c+1748,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
-	vcdp->declArray(c+1752,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
-	vcdp->declArray(c+1756,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
-	vcdp->declArray(c+1760,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
-	vcdp->declArray(c+1764,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
-	vcdp->declArray(c+1768,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
-	vcdp->declArray(c+1772,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
-	vcdp->declArray(c+1776,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
-	vcdp->declArray(c+1780,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
-	vcdp->declArray(c+1784,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
-	vcdp->declArray(c+1788,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
-	vcdp->declArray(c+1792,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
-	vcdp->declArray(c+1796,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index N",-1,31,0);
+	vcdp->declBus  (c+837,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
+	vcdp->declBus  (c+835,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index index",-1,0,0);
+	vcdp->declBit  (c+833,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index i",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
+	vcdp->declBus  (c+822,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
+	vcdp->declBus  (c+834,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
+	vcdp->declBit  (c+838,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures rst",-1);
+	vcdp->declBus  (c+204,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+839,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
+	vcdp->declBit  (c+840,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures evict",-1);
+	vcdp->declArray(c+841,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+202,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1119,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1120,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1124,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures valid_use",-1);
+	vcdp->declBit  (c+845,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
+	vcdp->declBit  (c+846,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
+	vcdp->declBit  (c+847,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
+	vcdp->declBit  (c+848,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
+	vcdp->declArray(c+3448,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+3452,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+3456,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+3460,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+3464,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+3468,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+3472,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+3476,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+3480,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+3484,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+3488,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+3492,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+3496,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+3500,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+3504,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+3508,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+3512,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+3516,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+3520,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+3524,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+3528,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+3532,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+3536,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+3540,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+3544,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+3548,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+3552,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+3556,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+3560,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+3564,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+3568,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+3572,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBus  (c+1800+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
+		vcdp->declBus  (c+3576+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+1832+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
+		vcdp->declBit  (c+3608+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+1864+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
-	vcdp->declBus  (c+1896,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
-	vcdp->declBus  (c+1897,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures rst",-1);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
-	vcdp->declBus  (c+447,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
-	vcdp->declBit  (c+448,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures evict",-1);
-	vcdp->declArray(c+449,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+200,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+1898,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+1899,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+1903,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures valid_use",-1);
-	vcdp->declBit  (c+1904,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
-	vcdp->declBit  (c+453,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
-	vcdp->declBit  (c+621,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
-	vcdp->declBit  (c+454,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
-	vcdp->declArray(c+1905,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
-	vcdp->declArray(c+1909,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
-	vcdp->declArray(c+1913,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
-	vcdp->declArray(c+1917,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
-	vcdp->declArray(c+1921,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
-	vcdp->declArray(c+1925,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
-	vcdp->declArray(c+1929,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
-	vcdp->declArray(c+1933,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
-	vcdp->declArray(c+1937,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
-	vcdp->declArray(c+1941,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
-	vcdp->declArray(c+1945,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
-	vcdp->declArray(c+1949,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
-	vcdp->declArray(c+1953,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
-	vcdp->declArray(c+1957,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
-	vcdp->declArray(c+1961,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
-	vcdp->declArray(c+1965,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
-	vcdp->declArray(c+1969,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
-	vcdp->declArray(c+1973,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
-	vcdp->declArray(c+1977,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
-	vcdp->declArray(c+1981,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
-	vcdp->declArray(c+1985,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
-	vcdp->declArray(c+1989,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
-	vcdp->declArray(c+1993,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
-	vcdp->declArray(c+1997,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
-	vcdp->declArray(c+2001,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
-	vcdp->declArray(c+2005,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
-	vcdp->declArray(c+2009,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
-	vcdp->declArray(c+2013,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
-	vcdp->declArray(c+2017,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
-	vcdp->declArray(c+2021,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
-	vcdp->declArray(c+2025,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
-	vcdp->declArray(c+2029,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
+		vcdp->declBit  (c+3640+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+3672,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
+	vcdp->declBus  (c+3673,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures rst",-1);
+	vcdp->declBus  (c+204,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+849,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
+	vcdp->declBit  (c+850,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures evict",-1);
+	vcdp->declArray(c+851,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+202,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1125,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1126,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1130,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures valid_use",-1);
+	vcdp->declBit  (c+855,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
+	vcdp->declBit  (c+856,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
+	vcdp->declBit  (c+857,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
+	vcdp->declBit  (c+858,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
+	vcdp->declArray(c+3674,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+3678,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+3682,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+3686,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+3690,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+3694,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+3698,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+3702,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+3706,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+3710,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+3714,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+3718,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+3722,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+3726,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+3730,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+3734,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+3738,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+3742,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+3746,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+3750,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+3754,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+3758,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+3762,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+3766,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+3770,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+3774,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+3778,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+3782,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+3786,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+3790,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+3794,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+3798,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBus  (c+2033+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
+		vcdp->declBus  (c+3802+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+2065+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
+		vcdp->declBit  (c+3834+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+2097+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
-	vcdp->declBus  (c+2129,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
-	vcdp->declBus  (c+2130,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
-	vcdp->declBus  (c+3098,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_SIZE",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3099,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_BANKS",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure LOG_NUM_BANKS",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure LOG_NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure OFFSET_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[2] bank_structure OFFSET_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure IND_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3103,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_TAG_START",-1,31,0);
-	vcdp->declBus  (c+3104,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_TAG_END",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_OFFSET_START",-1,31,0);
-	vcdp->declBus  (c+3093,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_OFFSET_END",-1,31,0);
-	vcdp->declBus  (c+3094,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_IND_START",-1,31,0);
-	vcdp->declBus  (c+3105,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_IND_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[2] bank_structure SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBus  (c+3094,"cache_simX dmem_controller dcache genblk3[2] bank_structure BLOCK_NUM_BITS",-1,31,0);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[2] bank_structure rst",-1);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[2] bank_structure clk",-1);
-	vcdp->declBus  (c+723,"cache_simX dmem_controller dcache genblk3[2] bank_structure state",-1,3,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[2] bank_structure actual_index",-1,4,0);
-	vcdp->declBus  (c+205,"cache_simX dmem_controller dcache genblk3[2] bank_structure o_tag",-1,20,0);
-	vcdp->declBus  (c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure block_offset",-1,1,0);
-	vcdp->declBus  (c+455,"cache_simX dmem_controller dcache genblk3[2] bank_structure writedata",-1,31,0);
-	vcdp->declBit  (c+207,"cache_simX dmem_controller dcache genblk3[2] bank_structure valid_in",-1);
+		vcdp->declBit  (c+3866+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+3898,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
+	vcdp->declBus  (c+3899,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_SIZE",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4840,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[2] bank_structure LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[2] bank_structure LOG_NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[2] bank_structure OFFSET_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[2] bank_structure OFFSET_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[2] bank_structure TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[2] bank_structure TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[2] bank_structure IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[2] bank_structure IND_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4844,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_TAG_START",-1,31,0);
+	vcdp->declBus  (c+4845,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_TAG_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4834,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_IND_START",-1,31,0);
+	vcdp->declBus  (c+4846,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_IND_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[2] bank_structure SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[2] bank_structure RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller dcache genblk3[2] bank_structure BLOCK_NUM_BITS",-1,31,0);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[2] bank_structure rst",-1);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[2] bank_structure clk",-1);
+	vcdp->declBus  (c+1178,"cache_simX dmem_controller dcache genblk3[2] bank_structure state",-1,3,0);
+	vcdp->declBus  (c+211,"cache_simX dmem_controller dcache genblk3[2] bank_structure actual_index",-1,4,0);
+	vcdp->declBus  (c+209,"cache_simX dmem_controller dcache genblk3[2] bank_structure o_tag",-1,20,0);
+	vcdp->declBus  (c+210,"cache_simX dmem_controller dcache genblk3[2] bank_structure block_offset",-1,1,0);
+	vcdp->declBus  (c+859,"cache_simX dmem_controller dcache genblk3[2] bank_structure writedata",-1,31,0);
+	vcdp->declBit  (c+213,"cache_simX dmem_controller dcache genblk3[2] bank_structure valid_in",-1);
 	vcdp->declBit  (c+4,"cache_simX dmem_controller dcache genblk3[2] bank_structure read_or_write",-1);
-	vcdp->declArray(c+3147,"cache_simX dmem_controller dcache genblk3[2] bank_structure fetched_writedata",-1,127,0);
+	vcdp->declArray(c+4909,"cache_simX dmem_controller dcache genblk3[2] bank_structure fetched_writedata",-1,127,0);
 	vcdp->declBus  (c+9,"cache_simX dmem_controller dcache genblk3[2] bank_structure i_p_mem_read",-1,2,0);
 	vcdp->declBus  (c+10,"cache_simX dmem_controller dcache genblk3[2] bank_structure i_p_mem_write",-1,2,0);
-	vcdp->declBus  (c+204,"cache_simX dmem_controller dcache genblk3[2] bank_structure byte_select",-1,1,0);
-	vcdp->declBus  (c+722,"cache_simX dmem_controller dcache genblk3[2] bank_structure evicted_way",-1,0,0);
-	vcdp->declBus  (c+456,"cache_simX dmem_controller dcache genblk3[2] bank_structure readdata",-1,31,0);
-	vcdp->declBit  (c+457,"cache_simX dmem_controller dcache genblk3[2] bank_structure hit",-1);
-	vcdp->declBit  (c+622,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_wb",-1);
-	vcdp->declBus  (c+458,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_addr",-1,31,0);
-	vcdp->declArray(c+459,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_evicted",-1,127,0);
-	vcdp->declArray(c+459,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_use",-1,127,0);
-	vcdp->declBus  (c+463,"cache_simX dmem_controller dcache genblk3[2] bank_structure tag_use",-1,20,0);
-	vcdp->declBus  (c+463,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_tag",-1,20,0);
-	vcdp->declBit  (c+464,"cache_simX dmem_controller dcache genblk3[2] bank_structure valid_use",-1);
-	vcdp->declBit  (c+622,"cache_simX dmem_controller dcache genblk3[2] bank_structure dirty_use",-1);
-	vcdp->declBit  (c+465,"cache_simX dmem_controller dcache genblk3[2] bank_structure access",-1);
-	vcdp->declBit  (c+466,"cache_simX dmem_controller dcache genblk3[2] bank_structure write_from_mem",-1);
-	vcdp->declBit  (c+467,"cache_simX dmem_controller dcache genblk3[2] bank_structure miss",-1);
-	vcdp->declBus  (c+676,"cache_simX dmem_controller dcache genblk3[2] bank_structure way_to_update",-1,0,0);
-	vcdp->declBit  (c+332,"cache_simX dmem_controller dcache genblk3[2] bank_structure lw",-1);
-	vcdp->declBit  (c+333,"cache_simX dmem_controller dcache genblk3[2] bank_structure lb",-1);
-	vcdp->declBit  (c+334,"cache_simX dmem_controller dcache genblk3[2] bank_structure lh",-1);
-	vcdp->declBit  (c+335,"cache_simX dmem_controller dcache genblk3[2] bank_structure lhu",-1);
-	vcdp->declBit  (c+336,"cache_simX dmem_controller dcache genblk3[2] bank_structure lbu",-1);
-	vcdp->declBit  (c+337,"cache_simX dmem_controller dcache genblk3[2] bank_structure sw",-1);
-	vcdp->declBit  (c+338,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb",-1);
-	vcdp->declBit  (c+339,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh",-1);
-	vcdp->declBit  (c+468,"cache_simX dmem_controller dcache genblk3[2] bank_structure b0",-1);
-	vcdp->declBit  (c+469,"cache_simX dmem_controller dcache genblk3[2] bank_structure b1",-1);
-	vcdp->declBit  (c+470,"cache_simX dmem_controller dcache genblk3[2] bank_structure b2",-1);
-	vcdp->declBit  (c+471,"cache_simX dmem_controller dcache genblk3[2] bank_structure b3",-1);
-	vcdp->declBus  (c+472,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_unQual",-1,31,0);
-	vcdp->declBus  (c+473,"cache_simX dmem_controller dcache genblk3[2] bank_structure lb_data",-1,31,0);
-	vcdp->declBus  (c+474,"cache_simX dmem_controller dcache genblk3[2] bank_structure lh_data",-1,31,0);
-	vcdp->declBus  (c+475,"cache_simX dmem_controller dcache genblk3[2] bank_structure lbu_data",-1,31,0);
-	vcdp->declBus  (c+476,"cache_simX dmem_controller dcache genblk3[2] bank_structure lhu_data",-1,31,0);
-	vcdp->declBus  (c+472,"cache_simX dmem_controller dcache genblk3[2] bank_structure lw_data",-1,31,0);
-	vcdp->declBus  (c+455,"cache_simX dmem_controller dcache genblk3[2] bank_structure sw_data",-1,31,0);
-	vcdp->declBus  (c+477,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb_data",-1,31,0);
-	vcdp->declBus  (c+478,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh_data",-1,31,0);
-	vcdp->declBus  (c+479,"cache_simX dmem_controller dcache genblk3[2] bank_structure use_write_data",-1,31,0);
-	vcdp->declBus  (c+480,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_Qual",-1,31,0);
-	vcdp->declBus  (c+481,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb_mask",-1,3,0);
-	vcdp->declBus  (c+482,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh_mask",-1,3,0);
-	vcdp->declBus  (c+483,"cache_simX dmem_controller dcache genblk3[2] bank_structure we",-1,15,0);
-	vcdp->declArray(c+484,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_write",-1,127,0);
+	vcdp->declBus  (c+208,"cache_simX dmem_controller dcache genblk3[2] bank_structure byte_select",-1,1,0);
+	vcdp->declBus  (c+1177,"cache_simX dmem_controller dcache genblk3[2] bank_structure evicted_way",-1,0,0);
+	vcdp->declBus  (c+860,"cache_simX dmem_controller dcache genblk3[2] bank_structure readdata",-1,31,0);
+	vcdp->declBit  (c+861,"cache_simX dmem_controller dcache genblk3[2] bank_structure hit",-1);
+	vcdp->declBit  (c+862,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_wb",-1);
+	vcdp->declBus  (c+863,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_addr",-1,31,0);
+	vcdp->declArray(c+864,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_evicted",-1,127,0);
+	vcdp->declArray(c+864,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_use",-1,127,0);
+	vcdp->declBus  (c+868,"cache_simX dmem_controller dcache genblk3[2] bank_structure tag_use",-1,20,0);
+	vcdp->declBus  (c+868,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_tag",-1,20,0);
+	vcdp->declBit  (c+869,"cache_simX dmem_controller dcache genblk3[2] bank_structure valid_use",-1);
+	vcdp->declBit  (c+862,"cache_simX dmem_controller dcache genblk3[2] bank_structure dirty_use",-1);
+	vcdp->declBit  (c+870,"cache_simX dmem_controller dcache genblk3[2] bank_structure access",-1);
+	vcdp->declBit  (c+871,"cache_simX dmem_controller dcache genblk3[2] bank_structure write_from_mem",-1);
+	vcdp->declBit  (c+872,"cache_simX dmem_controller dcache genblk3[2] bank_structure miss",-1);
+	vcdp->declBus  (c+1161,"cache_simX dmem_controller dcache genblk3[2] bank_structure way_to_update",-1,0,0);
+	vcdp->declBit  (c+691,"cache_simX dmem_controller dcache genblk3[2] bank_structure lw",-1);
+	vcdp->declBit  (c+692,"cache_simX dmem_controller dcache genblk3[2] bank_structure lb",-1);
+	vcdp->declBit  (c+693,"cache_simX dmem_controller dcache genblk3[2] bank_structure lh",-1);
+	vcdp->declBit  (c+694,"cache_simX dmem_controller dcache genblk3[2] bank_structure lhu",-1);
+	vcdp->declBit  (c+695,"cache_simX dmem_controller dcache genblk3[2] bank_structure lbu",-1);
+	vcdp->declBit  (c+696,"cache_simX dmem_controller dcache genblk3[2] bank_structure sw",-1);
+	vcdp->declBit  (c+697,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb",-1);
+	vcdp->declBit  (c+698,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh",-1);
+	vcdp->declBit  (c+873,"cache_simX dmem_controller dcache genblk3[2] bank_structure b0",-1);
+	vcdp->declBit  (c+874,"cache_simX dmem_controller dcache genblk3[2] bank_structure b1",-1);
+	vcdp->declBit  (c+875,"cache_simX dmem_controller dcache genblk3[2] bank_structure b2",-1);
+	vcdp->declBit  (c+876,"cache_simX dmem_controller dcache genblk3[2] bank_structure b3",-1);
+	vcdp->declBus  (c+877,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_unQual",-1,31,0);
+	vcdp->declBus  (c+878,"cache_simX dmem_controller dcache genblk3[2] bank_structure lb_data",-1,31,0);
+	vcdp->declBus  (c+879,"cache_simX dmem_controller dcache genblk3[2] bank_structure lh_data",-1,31,0);
+	vcdp->declBus  (c+880,"cache_simX dmem_controller dcache genblk3[2] bank_structure lbu_data",-1,31,0);
+	vcdp->declBus  (c+881,"cache_simX dmem_controller dcache genblk3[2] bank_structure lhu_data",-1,31,0);
+	vcdp->declBus  (c+877,"cache_simX dmem_controller dcache genblk3[2] bank_structure lw_data",-1,31,0);
+	vcdp->declBus  (c+859,"cache_simX dmem_controller dcache genblk3[2] bank_structure sw_data",-1,31,0);
+	vcdp->declBus  (c+882,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb_data",-1,31,0);
+	vcdp->declBus  (c+883,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh_data",-1,31,0);
+	vcdp->declBus  (c+884,"cache_simX dmem_controller dcache genblk3[2] bank_structure use_write_data",-1,31,0);
+	vcdp->declBus  (c+885,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_Qual",-1,31,0);
+	vcdp->declBus  (c+886,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb_mask",-1,3,0);
+	vcdp->declBus  (c+887,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh_mask",-1,3,0);
+	vcdp->declBus  (c+888,"cache_simX dmem_controller dcache genblk3[2] bank_structure we",-1,15,0);
+	vcdp->declArray(c+889,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_write",-1,127,0);
 	// Tracing: cache_simX dmem_controller dcache genblk3[2] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203
-	vcdp->declBit  (c+488,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[0] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[1] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[2] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[3] normal_write",-1);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures rst",-1);
-	vcdp->declBit  (c+207,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_in",-1);
-	vcdp->declBus  (c+723,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures state",-1,3,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures addr",-1,4,0);
-	vcdp->declBus  (c+483,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures we",-1,15,0);
-	vcdp->declBit  (c+466,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures evict",-1);
-	vcdp->declBus  (c+676,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_to_update",-1,0,0);
-	vcdp->declArray(c+484,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+205,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+463,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+459,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+464,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_use",-1);
-	vcdp->declBit  (c+622,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures dirty_use",-1);
-	vcdp->declQuad (c+677,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_use_per_way",-1,41,0);
-	vcdp->declArray(c+679,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_use_per_way",-1,255,0);
-	vcdp->declBus  (c+687,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_use_per_way",-1,1,0);
-	vcdp->declBus  (c+688,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures dirty_use_per_way",-1,1,0);
-	vcdp->declBus  (c+489,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures hit_per_way",-1,1,0);
-	vcdp->declBus  (c+490,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures we_per_way",-1,31,0);
-	vcdp->declArray(c+491,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_write_per_way",-1,255,0);
-	vcdp->declBus  (c+499,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures write_from_mem_per_way",-1,1,0);
-	vcdp->declBit  (c+689,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures invalid_found",-1);
-	vcdp->declBus  (c+500,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_index",-1,0,0);
-	vcdp->declBus  (c+690,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures invalid_index",-1,0,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBus  (c+501,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_use_Qual",-1,0,0);
+	vcdp->declBit  (c+893,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[0] normal_write",-1);
+	vcdp->declBit  (c+894,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[1] normal_write",-1);
+	vcdp->declBit  (c+895,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[2] normal_write",-1);
+	vcdp->declBit  (c+896,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[3] normal_write",-1);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures rst",-1);
+	vcdp->declBit  (c+213,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_in",-1);
+	vcdp->declBus  (c+1178,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures state",-1,3,0);
+	vcdp->declBus  (c+211,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures addr",-1,4,0);
+	vcdp->declBus  (c+888,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures we",-1,15,0);
+	vcdp->declBit  (c+871,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures evict",-1);
+	vcdp->declBus  (c+1161,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_to_update",-1,0,0);
+	vcdp->declArray(c+889,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+209,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+868,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+864,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+869,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_use",-1);
+	vcdp->declBit  (c+862,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures dirty_use",-1);
+	vcdp->declQuad (c+897,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_use_per_way",-1,41,0);
+	vcdp->declArray(c+899,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_use_per_way",-1,255,0);
+	vcdp->declBus  (c+907,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_use_per_way",-1,1,0);
+	vcdp->declBus  (c+908,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures dirty_use_per_way",-1,1,0);
+	vcdp->declBus  (c+909,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures hit_per_way",-1,1,0);
+	vcdp->declBus  (c+910,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures we_per_way",-1,31,0);
+	vcdp->declArray(c+911,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_write_per_way",-1,255,0);
+	vcdp->declBus  (c+919,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures write_from_mem_per_way",-1,1,0);
+	vcdp->declBit  (c+920,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures invalid_found",-1);
+	vcdp->declBus  (c+921,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_index",-1,0,0);
+	vcdp->declBus  (c+922,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures invalid_index",-1,0,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+923,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_use_Qual",-1,0,0);
 	// Tracing: cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index N",-1,31,0);
-	vcdp->declBus  (c+691,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
-	vcdp->declBus  (c+690,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index index",-1,0,0);
-	vcdp->declBit  (c+689,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index found",-1);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index i",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
-	vcdp->declBus  (c+489,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
-	vcdp->declBus  (c+500,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
-	vcdp->declBit  (c+502,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing found",-1);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures rst",-1);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
-	vcdp->declBus  (c+503,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
-	vcdp->declBit  (c+504,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures evict",-1);
-	vcdp->declArray(c+505,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+205,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+2131,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+2132,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+2136,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures valid_use",-1);
-	vcdp->declBit  (c+2137,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
-	vcdp->declBit  (c+509,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
-	vcdp->declBit  (c+623,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
-	vcdp->declBit  (c+510,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
-	vcdp->declArray(c+2138,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
-	vcdp->declArray(c+2142,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
-	vcdp->declArray(c+2146,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
-	vcdp->declArray(c+2150,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
-	vcdp->declArray(c+2154,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
-	vcdp->declArray(c+2158,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
-	vcdp->declArray(c+2162,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
-	vcdp->declArray(c+2166,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
-	vcdp->declArray(c+2170,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
-	vcdp->declArray(c+2174,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
-	vcdp->declArray(c+2178,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
-	vcdp->declArray(c+2182,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
-	vcdp->declArray(c+2186,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
-	vcdp->declArray(c+2190,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
-	vcdp->declArray(c+2194,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
-	vcdp->declArray(c+2198,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
-	vcdp->declArray(c+2202,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
-	vcdp->declArray(c+2206,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
-	vcdp->declArray(c+2210,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
-	vcdp->declArray(c+2214,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
-	vcdp->declArray(c+2218,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
-	vcdp->declArray(c+2222,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
-	vcdp->declArray(c+2226,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
-	vcdp->declArray(c+2230,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
-	vcdp->declArray(c+2234,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
-	vcdp->declArray(c+2238,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
-	vcdp->declArray(c+2242,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
-	vcdp->declArray(c+2246,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
-	vcdp->declArray(c+2250,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
-	vcdp->declArray(c+2254,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
-	vcdp->declArray(c+2258,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
-	vcdp->declArray(c+2262,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index N",-1,31,0);
+	vcdp->declBus  (c+924,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
+	vcdp->declBus  (c+922,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index index",-1,0,0);
+	vcdp->declBit  (c+920,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index i",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
+	vcdp->declBus  (c+909,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
+	vcdp->declBus  (c+921,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
+	vcdp->declBit  (c+925,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures rst",-1);
+	vcdp->declBus  (c+211,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+926,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
+	vcdp->declBit  (c+927,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures evict",-1);
+	vcdp->declArray(c+928,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+209,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1131,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1132,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1136,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures valid_use",-1);
+	vcdp->declBit  (c+932,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
+	vcdp->declBit  (c+933,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
+	vcdp->declBit  (c+934,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
+	vcdp->declBit  (c+935,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
+	vcdp->declArray(c+3900,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+3904,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+3908,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+3912,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+3916,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+3920,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+3924,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+3928,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+3932,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+3936,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+3940,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+3944,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+3948,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+3952,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+3956,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+3960,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+3964,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+3968,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+3972,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+3976,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+3980,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+3984,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+3988,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+3992,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+3996,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+4000,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+4004,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+4008,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+4012,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+4016,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+4020,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+4024,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBus  (c+2266+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
+		vcdp->declBus  (c+4028+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+2298+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
+		vcdp->declBit  (c+4060+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+2330+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
-	vcdp->declBus  (c+2362,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
-	vcdp->declBus  (c+2363,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures rst",-1);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
-	vcdp->declBus  (c+511,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
-	vcdp->declBit  (c+512,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures evict",-1);
-	vcdp->declArray(c+513,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+205,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+2364,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+2365,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+2369,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures valid_use",-1);
-	vcdp->declBit  (c+2370,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
-	vcdp->declBit  (c+517,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
-	vcdp->declBit  (c+624,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
-	vcdp->declBit  (c+518,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
-	vcdp->declArray(c+2371,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
-	vcdp->declArray(c+2375,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
-	vcdp->declArray(c+2379,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
-	vcdp->declArray(c+2383,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
-	vcdp->declArray(c+2387,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
-	vcdp->declArray(c+2391,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
-	vcdp->declArray(c+2395,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
-	vcdp->declArray(c+2399,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
-	vcdp->declArray(c+2403,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
-	vcdp->declArray(c+2407,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
-	vcdp->declArray(c+2411,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
-	vcdp->declArray(c+2415,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
-	vcdp->declArray(c+2419,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
-	vcdp->declArray(c+2423,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
-	vcdp->declArray(c+2427,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
-	vcdp->declArray(c+2431,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
-	vcdp->declArray(c+2435,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
-	vcdp->declArray(c+2439,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
-	vcdp->declArray(c+2443,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
-	vcdp->declArray(c+2447,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
-	vcdp->declArray(c+2451,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
-	vcdp->declArray(c+2455,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
-	vcdp->declArray(c+2459,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
-	vcdp->declArray(c+2463,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
-	vcdp->declArray(c+2467,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
-	vcdp->declArray(c+2471,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
-	vcdp->declArray(c+2475,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
-	vcdp->declArray(c+2479,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
-	vcdp->declArray(c+2483,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
-	vcdp->declArray(c+2487,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
-	vcdp->declArray(c+2491,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
-	vcdp->declArray(c+2495,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
+		vcdp->declBit  (c+4092+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+4124,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
+	vcdp->declBus  (c+4125,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures rst",-1);
+	vcdp->declBus  (c+211,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+936,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
+	vcdp->declBit  (c+937,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures evict",-1);
+	vcdp->declArray(c+938,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+209,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1137,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1138,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1142,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures valid_use",-1);
+	vcdp->declBit  (c+942,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
+	vcdp->declBit  (c+943,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
+	vcdp->declBit  (c+944,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
+	vcdp->declBit  (c+945,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
+	vcdp->declArray(c+4126,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+4130,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+4134,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+4138,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+4142,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+4146,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+4150,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+4154,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+4158,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+4162,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+4166,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+4170,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+4174,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+4178,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+4182,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+4186,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+4190,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+4194,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+4198,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+4202,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+4206,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+4210,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+4214,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+4218,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+4222,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+4226,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+4230,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+4234,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+4238,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+4242,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+4246,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+4250,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBus  (c+2499+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
+		vcdp->declBus  (c+4254+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+2531+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
+		vcdp->declBit  (c+4286+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+2563+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
-	vcdp->declBus  (c+2595,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
-	vcdp->declBus  (c+2596,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
-	vcdp->declBus  (c+3098,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_SIZE",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3099,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_BANKS",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure LOG_NUM_BANKS",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure LOG_NUM_REQ",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure OFFSET_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[3] bank_structure OFFSET_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure IND_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3103,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_TAG_START",-1,31,0);
-	vcdp->declBus  (c+3104,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_TAG_END",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_OFFSET_START",-1,31,0);
-	vcdp->declBus  (c+3093,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_OFFSET_END",-1,31,0);
-	vcdp->declBus  (c+3094,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_IND_START",-1,31,0);
-	vcdp->declBus  (c+3105,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_IND_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[3] bank_structure SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBus  (c+3094,"cache_simX dmem_controller dcache genblk3[3] bank_structure BLOCK_NUM_BITS",-1,31,0);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[3] bank_structure rst",-1);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[3] bank_structure clk",-1);
-	vcdp->declBus  (c+723,"cache_simX dmem_controller dcache genblk3[3] bank_structure state",-1,3,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[3] bank_structure actual_index",-1,4,0);
-	vcdp->declBus  (c+210,"cache_simX dmem_controller dcache genblk3[3] bank_structure o_tag",-1,20,0);
-	vcdp->declBus  (c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure block_offset",-1,1,0);
-	vcdp->declBus  (c+519,"cache_simX dmem_controller dcache genblk3[3] bank_structure writedata",-1,31,0);
-	vcdp->declBit  (c+212,"cache_simX dmem_controller dcache genblk3[3] bank_structure valid_in",-1);
+		vcdp->declBit  (c+4318+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+4350,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
+	vcdp->declBus  (c+4351,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4839,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_SIZE",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4840,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_BANKS",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[3] bank_structure LOG_NUM_BANKS",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[3] bank_structure LOG_NUM_REQ",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[3] bank_structure OFFSET_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[3] bank_structure OFFSET_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[3] bank_structure TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[3] bank_structure TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[3] bank_structure IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[3] bank_structure IND_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4844,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_TAG_START",-1,31,0);
+	vcdp->declBus  (c+4845,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_TAG_END",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_OFFSET_START",-1,31,0);
+	vcdp->declBus  (c+4834,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_OFFSET_END",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_IND_START",-1,31,0);
+	vcdp->declBus  (c+4846,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_IND_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[3] bank_structure SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[3] bank_structure RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+4835,"cache_simX dmem_controller dcache genblk3[3] bank_structure BLOCK_NUM_BITS",-1,31,0);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[3] bank_structure rst",-1);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[3] bank_structure clk",-1);
+	vcdp->declBus  (c+1178,"cache_simX dmem_controller dcache genblk3[3] bank_structure state",-1,3,0);
+	vcdp->declBus  (c+218,"cache_simX dmem_controller dcache genblk3[3] bank_structure actual_index",-1,4,0);
+	vcdp->declBus  (c+216,"cache_simX dmem_controller dcache genblk3[3] bank_structure o_tag",-1,20,0);
+	vcdp->declBus  (c+217,"cache_simX dmem_controller dcache genblk3[3] bank_structure block_offset",-1,1,0);
+	vcdp->declBus  (c+946,"cache_simX dmem_controller dcache genblk3[3] bank_structure writedata",-1,31,0);
+	vcdp->declBit  (c+220,"cache_simX dmem_controller dcache genblk3[3] bank_structure valid_in",-1);
 	vcdp->declBit  (c+4,"cache_simX dmem_controller dcache genblk3[3] bank_structure read_or_write",-1);
-	vcdp->declArray(c+3151,"cache_simX dmem_controller dcache genblk3[3] bank_structure fetched_writedata",-1,127,0);
+	vcdp->declArray(c+4913,"cache_simX dmem_controller dcache genblk3[3] bank_structure fetched_writedata",-1,127,0);
 	vcdp->declBus  (c+9,"cache_simX dmem_controller dcache genblk3[3] bank_structure i_p_mem_read",-1,2,0);
 	vcdp->declBus  (c+10,"cache_simX dmem_controller dcache genblk3[3] bank_structure i_p_mem_write",-1,2,0);
-	vcdp->declBus  (c+209,"cache_simX dmem_controller dcache genblk3[3] bank_structure byte_select",-1,1,0);
-	vcdp->declBus  (c+722,"cache_simX dmem_controller dcache genblk3[3] bank_structure evicted_way",-1,0,0);
-	vcdp->declBus  (c+520,"cache_simX dmem_controller dcache genblk3[3] bank_structure readdata",-1,31,0);
-	vcdp->declBit  (c+521,"cache_simX dmem_controller dcache genblk3[3] bank_structure hit",-1);
-	vcdp->declBit  (c+625,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_wb",-1);
-	vcdp->declBus  (c+522,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_addr",-1,31,0);
-	vcdp->declArray(c+523,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_evicted",-1,127,0);
-	vcdp->declArray(c+523,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_use",-1,127,0);
-	vcdp->declBus  (c+527,"cache_simX dmem_controller dcache genblk3[3] bank_structure tag_use",-1,20,0);
-	vcdp->declBus  (c+527,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_tag",-1,20,0);
-	vcdp->declBit  (c+528,"cache_simX dmem_controller dcache genblk3[3] bank_structure valid_use",-1);
-	vcdp->declBit  (c+625,"cache_simX dmem_controller dcache genblk3[3] bank_structure dirty_use",-1);
-	vcdp->declBit  (c+529,"cache_simX dmem_controller dcache genblk3[3] bank_structure access",-1);
-	vcdp->declBit  (c+530,"cache_simX dmem_controller dcache genblk3[3] bank_structure write_from_mem",-1);
-	vcdp->declBit  (c+531,"cache_simX dmem_controller dcache genblk3[3] bank_structure miss",-1);
-	vcdp->declBus  (c+692,"cache_simX dmem_controller dcache genblk3[3] bank_structure way_to_update",-1,0,0);
-	vcdp->declBit  (c+332,"cache_simX dmem_controller dcache genblk3[3] bank_structure lw",-1);
-	vcdp->declBit  (c+333,"cache_simX dmem_controller dcache genblk3[3] bank_structure lb",-1);
-	vcdp->declBit  (c+334,"cache_simX dmem_controller dcache genblk3[3] bank_structure lh",-1);
-	vcdp->declBit  (c+335,"cache_simX dmem_controller dcache genblk3[3] bank_structure lhu",-1);
-	vcdp->declBit  (c+336,"cache_simX dmem_controller dcache genblk3[3] bank_structure lbu",-1);
-	vcdp->declBit  (c+337,"cache_simX dmem_controller dcache genblk3[3] bank_structure sw",-1);
-	vcdp->declBit  (c+338,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb",-1);
-	vcdp->declBit  (c+339,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh",-1);
-	vcdp->declBit  (c+532,"cache_simX dmem_controller dcache genblk3[3] bank_structure b0",-1);
-	vcdp->declBit  (c+533,"cache_simX dmem_controller dcache genblk3[3] bank_structure b1",-1);
-	vcdp->declBit  (c+534,"cache_simX dmem_controller dcache genblk3[3] bank_structure b2",-1);
-	vcdp->declBit  (c+535,"cache_simX dmem_controller dcache genblk3[3] bank_structure b3",-1);
-	vcdp->declBus  (c+536,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_unQual",-1,31,0);
-	vcdp->declBus  (c+537,"cache_simX dmem_controller dcache genblk3[3] bank_structure lb_data",-1,31,0);
-	vcdp->declBus  (c+538,"cache_simX dmem_controller dcache genblk3[3] bank_structure lh_data",-1,31,0);
-	vcdp->declBus  (c+539,"cache_simX dmem_controller dcache genblk3[3] bank_structure lbu_data",-1,31,0);
-	vcdp->declBus  (c+540,"cache_simX dmem_controller dcache genblk3[3] bank_structure lhu_data",-1,31,0);
-	vcdp->declBus  (c+536,"cache_simX dmem_controller dcache genblk3[3] bank_structure lw_data",-1,31,0);
-	vcdp->declBus  (c+519,"cache_simX dmem_controller dcache genblk3[3] bank_structure sw_data",-1,31,0);
-	vcdp->declBus  (c+541,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb_data",-1,31,0);
-	vcdp->declBus  (c+542,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh_data",-1,31,0);
-	vcdp->declBus  (c+543,"cache_simX dmem_controller dcache genblk3[3] bank_structure use_write_data",-1,31,0);
-	vcdp->declBus  (c+544,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_Qual",-1,31,0);
-	vcdp->declBus  (c+545,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb_mask",-1,3,0);
-	vcdp->declBus  (c+546,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh_mask",-1,3,0);
-	vcdp->declBus  (c+547,"cache_simX dmem_controller dcache genblk3[3] bank_structure we",-1,15,0);
-	vcdp->declArray(c+548,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_write",-1,127,0);
+	vcdp->declBus  (c+215,"cache_simX dmem_controller dcache genblk3[3] bank_structure byte_select",-1,1,0);
+	vcdp->declBus  (c+1177,"cache_simX dmem_controller dcache genblk3[3] bank_structure evicted_way",-1,0,0);
+	vcdp->declBus  (c+947,"cache_simX dmem_controller dcache genblk3[3] bank_structure readdata",-1,31,0);
+	vcdp->declBit  (c+948,"cache_simX dmem_controller dcache genblk3[3] bank_structure hit",-1);
+	vcdp->declBit  (c+949,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_wb",-1);
+	vcdp->declBus  (c+950,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_addr",-1,31,0);
+	vcdp->declArray(c+951,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_evicted",-1,127,0);
+	vcdp->declArray(c+951,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_use",-1,127,0);
+	vcdp->declBus  (c+955,"cache_simX dmem_controller dcache genblk3[3] bank_structure tag_use",-1,20,0);
+	vcdp->declBus  (c+955,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_tag",-1,20,0);
+	vcdp->declBit  (c+956,"cache_simX dmem_controller dcache genblk3[3] bank_structure valid_use",-1);
+	vcdp->declBit  (c+949,"cache_simX dmem_controller dcache genblk3[3] bank_structure dirty_use",-1);
+	vcdp->declBit  (c+957,"cache_simX dmem_controller dcache genblk3[3] bank_structure access",-1);
+	vcdp->declBit  (c+958,"cache_simX dmem_controller dcache genblk3[3] bank_structure write_from_mem",-1);
+	vcdp->declBit  (c+959,"cache_simX dmem_controller dcache genblk3[3] bank_structure miss",-1);
+	vcdp->declBus  (c+1162,"cache_simX dmem_controller dcache genblk3[3] bank_structure way_to_update",-1,0,0);
+	vcdp->declBit  (c+691,"cache_simX dmem_controller dcache genblk3[3] bank_structure lw",-1);
+	vcdp->declBit  (c+692,"cache_simX dmem_controller dcache genblk3[3] bank_structure lb",-1);
+	vcdp->declBit  (c+693,"cache_simX dmem_controller dcache genblk3[3] bank_structure lh",-1);
+	vcdp->declBit  (c+694,"cache_simX dmem_controller dcache genblk3[3] bank_structure lhu",-1);
+	vcdp->declBit  (c+695,"cache_simX dmem_controller dcache genblk3[3] bank_structure lbu",-1);
+	vcdp->declBit  (c+696,"cache_simX dmem_controller dcache genblk3[3] bank_structure sw",-1);
+	vcdp->declBit  (c+697,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb",-1);
+	vcdp->declBit  (c+698,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh",-1);
+	vcdp->declBit  (c+960,"cache_simX dmem_controller dcache genblk3[3] bank_structure b0",-1);
+	vcdp->declBit  (c+961,"cache_simX dmem_controller dcache genblk3[3] bank_structure b1",-1);
+	vcdp->declBit  (c+962,"cache_simX dmem_controller dcache genblk3[3] bank_structure b2",-1);
+	vcdp->declBit  (c+963,"cache_simX dmem_controller dcache genblk3[3] bank_structure b3",-1);
+	vcdp->declBus  (c+964,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_unQual",-1,31,0);
+	vcdp->declBus  (c+965,"cache_simX dmem_controller dcache genblk3[3] bank_structure lb_data",-1,31,0);
+	vcdp->declBus  (c+966,"cache_simX dmem_controller dcache genblk3[3] bank_structure lh_data",-1,31,0);
+	vcdp->declBus  (c+967,"cache_simX dmem_controller dcache genblk3[3] bank_structure lbu_data",-1,31,0);
+	vcdp->declBus  (c+968,"cache_simX dmem_controller dcache genblk3[3] bank_structure lhu_data",-1,31,0);
+	vcdp->declBus  (c+964,"cache_simX dmem_controller dcache genblk3[3] bank_structure lw_data",-1,31,0);
+	vcdp->declBus  (c+946,"cache_simX dmem_controller dcache genblk3[3] bank_structure sw_data",-1,31,0);
+	vcdp->declBus  (c+969,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb_data",-1,31,0);
+	vcdp->declBus  (c+970,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh_data",-1,31,0);
+	vcdp->declBus  (c+971,"cache_simX dmem_controller dcache genblk3[3] bank_structure use_write_data",-1,31,0);
+	vcdp->declBus  (c+972,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_Qual",-1,31,0);
+	vcdp->declBus  (c+973,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb_mask",-1,3,0);
+	vcdp->declBus  (c+974,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh_mask",-1,3,0);
+	vcdp->declBus  (c+975,"cache_simX dmem_controller dcache genblk3[3] bank_structure we",-1,15,0);
+	vcdp->declArray(c+976,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_write",-1,127,0);
 	// Tracing: cache_simX dmem_controller dcache genblk3[3] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203
-	vcdp->declBit  (c+552,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[0] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[1] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[2] normal_write",-1);
-	vcdp->declBit  (c+3086,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[3] normal_write",-1);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_WAYS",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures rst",-1);
-	vcdp->declBit  (c+212,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_in",-1);
-	vcdp->declBus  (c+723,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures state",-1,3,0);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures addr",-1,4,0);
-	vcdp->declBus  (c+547,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures we",-1,15,0);
-	vcdp->declBit  (c+530,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures evict",-1);
-	vcdp->declBus  (c+692,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_to_update",-1,0,0);
-	vcdp->declArray(c+548,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+210,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+527,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+523,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+528,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_use",-1);
-	vcdp->declBit  (c+625,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures dirty_use",-1);
-	vcdp->declQuad (c+693,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_use_per_way",-1,41,0);
-	vcdp->declArray(c+695,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_use_per_way",-1,255,0);
-	vcdp->declBus  (c+703,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_use_per_way",-1,1,0);
-	vcdp->declBus  (c+704,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures dirty_use_per_way",-1,1,0);
-	vcdp->declBus  (c+553,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures hit_per_way",-1,1,0);
-	vcdp->declBus  (c+554,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures we_per_way",-1,31,0);
-	vcdp->declArray(c+555,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_write_per_way",-1,255,0);
-	vcdp->declBus  (c+563,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures write_from_mem_per_way",-1,1,0);
-	vcdp->declBit  (c+705,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures invalid_found",-1);
-	vcdp->declBus  (c+564,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_index",-1,0,0);
-	vcdp->declBus  (c+706,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures invalid_index",-1,0,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_IDLE",-1,31,0);
-	vcdp->declBus  (c+3101,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
-	vcdp->declBus  (c+565,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_use_Qual",-1,0,0);
+	vcdp->declBit  (c+980,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[0] normal_write",-1);
+	vcdp->declBit  (c+981,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[1] normal_write",-1);
+	vcdp->declBit  (c+982,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[2] normal_write",-1);
+	vcdp->declBit  (c+983,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[3] normal_write",-1);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_WAYS",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures rst",-1);
+	vcdp->declBit  (c+220,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_in",-1);
+	vcdp->declBus  (c+1178,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures state",-1,3,0);
+	vcdp->declBus  (c+218,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures addr",-1,4,0);
+	vcdp->declBus  (c+975,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures we",-1,15,0);
+	vcdp->declBit  (c+958,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures evict",-1);
+	vcdp->declBus  (c+1162,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_to_update",-1,0,0);
+	vcdp->declArray(c+976,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+216,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+955,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+951,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+956,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_use",-1);
+	vcdp->declBit  (c+949,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures dirty_use",-1);
+	vcdp->declQuad (c+984,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_use_per_way",-1,41,0);
+	vcdp->declArray(c+986,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_use_per_way",-1,255,0);
+	vcdp->declBus  (c+994,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_use_per_way",-1,1,0);
+	vcdp->declBus  (c+995,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures dirty_use_per_way",-1,1,0);
+	vcdp->declBus  (c+996,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures hit_per_way",-1,1,0);
+	vcdp->declBus  (c+997,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures we_per_way",-1,31,0);
+	vcdp->declArray(c+998,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_write_per_way",-1,255,0);
+	vcdp->declBus  (c+1006,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures write_from_mem_per_way",-1,1,0);
+	vcdp->declBit  (c+1007,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures invalid_found",-1);
+	vcdp->declBus  (c+1008,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_index",-1,0,0);
+	vcdp->declBus  (c+1009,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures invalid_index",-1,0,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_IDLE",-1,31,0);
+	vcdp->declBus  (c+4842,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures SEND_MEM_REQ",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures RECIV_MEM_RSP",-1,31,0);
+	vcdp->declBus  (c+1010,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_use_Qual",-1,0,0);
 	// Tracing: cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index N",-1,31,0);
-	vcdp->declBus  (c+707,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
-	vcdp->declBus  (c+706,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index index",-1,0,0);
-	vcdp->declBit  (c+705,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index found",-1);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index i",-1,31,0);
-	vcdp->declBus  (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
-	vcdp->declBus  (c+553,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
-	vcdp->declBus  (c+564,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
-	vcdp->declBit  (c+566,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing found",-1);
-	vcdp->declBus  (c+3097,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures rst",-1);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
-	vcdp->declBus  (c+567,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
-	vcdp->declBit  (c+568,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures evict",-1);
-	vcdp->declArray(c+569,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+210,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+2597,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+2598,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+2602,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures valid_use",-1);
-	vcdp->declBit  (c+2603,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
-	vcdp->declBit  (c+573,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
-	vcdp->declBit  (c+626,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
-	vcdp->declBit  (c+574,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
-	vcdp->declArray(c+2604,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
-	vcdp->declArray(c+2608,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
-	vcdp->declArray(c+2612,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
-	vcdp->declArray(c+2616,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
-	vcdp->declArray(c+2620,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
-	vcdp->declArray(c+2624,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
-	vcdp->declArray(c+2628,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
-	vcdp->declArray(c+2632,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
-	vcdp->declArray(c+2636,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
-	vcdp->declArray(c+2640,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
-	vcdp->declArray(c+2644,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
-	vcdp->declArray(c+2648,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
-	vcdp->declArray(c+2652,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
-	vcdp->declArray(c+2656,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
-	vcdp->declArray(c+2660,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
-	vcdp->declArray(c+2664,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
-	vcdp->declArray(c+2668,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
-	vcdp->declArray(c+2672,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
-	vcdp->declArray(c+2676,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
-	vcdp->declArray(c+2680,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
-	vcdp->declArray(c+2684,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
-	vcdp->declArray(c+2688,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
-	vcdp->declArray(c+2692,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
-	vcdp->declArray(c+2696,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
-	vcdp->declArray(c+2700,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
-	vcdp->declArray(c+2704,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
-	vcdp->declArray(c+2708,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
-	vcdp->declArray(c+2712,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
-	vcdp->declArray(c+2716,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
-	vcdp->declArray(c+2720,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
-	vcdp->declArray(c+2724,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
-	vcdp->declArray(c+2728,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index N",-1,31,0);
+	vcdp->declBus  (c+1011,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index valids",-1,1,0);
+	vcdp->declBus  (c+1009,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index index",-1,0,0);
+	vcdp->declBit  (c+1007,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index i",-1,31,0);
+	vcdp->declBus  (c+4831,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing N",-1,31,0);
+	vcdp->declBus  (c+996,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing valids",-1,1,0);
+	vcdp->declBus  (c+1008,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing index",-1,0,0);
+	vcdp->declBit  (c+1012,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing found",-1);
+	vcdp->declBus  (c+4838,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing i",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures rst",-1);
+	vcdp->declBus  (c+218,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+1013,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures we",-1,15,0);
+	vcdp->declBit  (c+1014,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures evict",-1);
+	vcdp->declArray(c+1015,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+216,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1143,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1144,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1148,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures valid_use",-1);
+	vcdp->declBit  (c+1019,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirty_use",-1);
+	vcdp->declBit  (c+1020,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures currently_writing",-1);
+	vcdp->declBit  (c+1021,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures update_dirty",-1);
+	vcdp->declBit  (c+1022,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirt_new",-1);
+	vcdp->declArray(c+4352,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+4356,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+4360,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+4364,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+4368,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+4372,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+4376,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+4380,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+4384,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+4388,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+4392,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+4396,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+4400,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+4404,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+4408,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+4412,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+4416,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+4420,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+4424,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+4428,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+4432,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+4436,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+4440,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+4444,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+4448,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+4452,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+4456,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+4460,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+4464,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+4468,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+4472,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+4476,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0);
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBus  (c+2732+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
+		vcdp->declBus  (c+4480+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+2764+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
+		vcdp->declBit  (c+4512+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures valid",(i+0));}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+2796+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
-	vcdp->declBus  (c+2828,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
-	vcdp->declBus  (c+2829,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
-	vcdp->declBus  (c+3100,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
-	vcdp->declBus  (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
-	vcdp->declBus  (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
-	vcdp->declBit  (c+3063,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures clk",-1);
-	vcdp->declBit  (c+3064,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures rst",-1);
-	vcdp->declBus  (c+3126,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
-	vcdp->declBus  (c+575,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
-	vcdp->declBit  (c+576,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures evict",-1);
-	vcdp->declArray(c+577,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
-	vcdp->declBus  (c+210,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0);
-	vcdp->declBus  (c+2830,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
-	vcdp->declArray(c+2831,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
-	vcdp->declBit  (c+2835,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures valid_use",-1);
-	vcdp->declBit  (c+2836,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
-	vcdp->declBit  (c+581,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
-	vcdp->declBit  (c+627,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
-	vcdp->declBit  (c+582,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
-	vcdp->declArray(c+2837,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
-	vcdp->declArray(c+2841,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
-	vcdp->declArray(c+2845,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
-	vcdp->declArray(c+2849,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
-	vcdp->declArray(c+2853,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
-	vcdp->declArray(c+2857,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
-	vcdp->declArray(c+2861,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
-	vcdp->declArray(c+2865,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
-	vcdp->declArray(c+2869,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
-	vcdp->declArray(c+2873,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
-	vcdp->declArray(c+2877,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
-	vcdp->declArray(c+2881,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
-	vcdp->declArray(c+2885,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
-	vcdp->declArray(c+2889,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
-	vcdp->declArray(c+2893,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
-	vcdp->declArray(c+2897,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
-	vcdp->declArray(c+2901,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
-	vcdp->declArray(c+2905,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
-	vcdp->declArray(c+2909,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
-	vcdp->declArray(c+2913,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
-	vcdp->declArray(c+2917,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
-	vcdp->declArray(c+2921,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
-	vcdp->declArray(c+2925,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
-	vcdp->declArray(c+2929,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
-	vcdp->declArray(c+2933,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
-	vcdp->declArray(c+2937,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
-	vcdp->declArray(c+2941,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
-	vcdp->declArray(c+2945,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
-	vcdp->declArray(c+2949,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
-	vcdp->declArray(c+2953,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
-	vcdp->declArray(c+2957,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
-	vcdp->declArray(c+2961,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
+		vcdp->declBit  (c+4544+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+4576,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures f",-1,31,0);
+	vcdp->declBus  (c+4577,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0);
+	vcdp->declBus  (c+4841,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4843,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0);
+	vcdp->declBus  (c+4826,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0);
+	vcdp->declBus  (c+4829,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0);
+	vcdp->declBit  (c+4804,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures clk",-1);
+	vcdp->declBit  (c+4805,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures rst",-1);
+	vcdp->declBus  (c+218,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures addr",-1,4,0);
+	vcdp->declBus  (c+1023,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures we",-1,15,0);
+	vcdp->declBit  (c+1024,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures evict",-1);
+	vcdp->declArray(c+1025,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0);
+	vcdp->declBus  (c+216,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0);
+	vcdp->declBus  (c+1149,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0);
+	vcdp->declArray(c+1150,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0);
+	vcdp->declBit  (c+1154,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures valid_use",-1);
+	vcdp->declBit  (c+1029,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirty_use",-1);
+	vcdp->declBit  (c+1030,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures currently_writing",-1);
+	vcdp->declBit  (c+1031,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures update_dirty",-1);
+	vcdp->declBit  (c+1032,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirt_new",-1);
+	vcdp->declArray(c+4578,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0);
+	vcdp->declArray(c+4582,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0);
+	vcdp->declArray(c+4586,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0);
+	vcdp->declArray(c+4590,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0);
+	vcdp->declArray(c+4594,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0);
+	vcdp->declArray(c+4598,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0);
+	vcdp->declArray(c+4602,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0);
+	vcdp->declArray(c+4606,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0);
+	vcdp->declArray(c+4610,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0);
+	vcdp->declArray(c+4614,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0);
+	vcdp->declArray(c+4618,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0);
+	vcdp->declArray(c+4622,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0);
+	vcdp->declArray(c+4626,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0);
+	vcdp->declArray(c+4630,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0);
+	vcdp->declArray(c+4634,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0);
+	vcdp->declArray(c+4638,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0);
+	vcdp->declArray(c+4642,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0);
+	vcdp->declArray(c+4646,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0);
+	vcdp->declArray(c+4650,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0);
+	vcdp->declArray(c+4654,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0);
+	vcdp->declArray(c+4658,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0);
+	vcdp->declArray(c+4662,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0);
+	vcdp->declArray(c+4666,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0);
+	vcdp->declArray(c+4670,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0);
+	vcdp->declArray(c+4674,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0);
+	vcdp->declArray(c+4678,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0);
+	vcdp->declArray(c+4682,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0);
+	vcdp->declArray(c+4686,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0);
+	vcdp->declArray(c+4690,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0);
+	vcdp->declArray(c+4694,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0);
+	vcdp->declArray(c+4698,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0);
+	vcdp->declArray(c+4702,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0);
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBus  (c+2965+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
+		vcdp->declBus  (c+4706+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+2997+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
+		vcdp->declBit  (c+4738+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures valid",(i+0));}}
 	{int i; for (i=0; i<32; i++) {
-		vcdp->declBit  (c+3029+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
-	vcdp->declBus  (c+3061,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
-	vcdp->declBus  (c+3062,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
+		vcdp->declBit  (c+4770+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}}
+	vcdp->declBus  (c+4802,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures f",-1,31,0);
+	vcdp->declBus  (c+4803,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0);
     }
 }
 
@@ -1878,6 +2691,66 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
     int c=code;
     if (0 && vcdp && c) {}  // Prevent unused
     // Variables
+    VL_SIGW(__Vtemp147,127,0,4);
+    VL_SIGW(__Vtemp148,127,0,4);
+    VL_SIGW(__Vtemp149,127,0,4);
+    VL_SIGW(__Vtemp150,127,0,4);
+    VL_SIGW(__Vtemp151,127,0,4);
+    VL_SIGW(__Vtemp152,127,0,4);
+    VL_SIGW(__Vtemp153,127,0,4);
+    VL_SIGW(__Vtemp154,127,0,4);
+    VL_SIGW(__Vtemp155,127,0,4);
+    VL_SIGW(__Vtemp156,127,0,4);
+    VL_SIGW(__Vtemp157,127,0,4);
+    VL_SIGW(__Vtemp158,127,0,4);
+    VL_SIGW(__Vtemp159,127,0,4);
+    VL_SIGW(__Vtemp160,127,0,4);
+    VL_SIGW(__Vtemp161,127,0,4);
+    VL_SIGW(__Vtemp162,127,0,4);
+    VL_SIGW(__Vtemp163,127,0,4);
+    VL_SIGW(__Vtemp164,127,0,4);
+    VL_SIGW(__Vtemp165,127,0,4);
+    VL_SIGW(__Vtemp166,127,0,4);
+    VL_SIGW(__Vtemp167,127,0,4);
+    VL_SIGW(__Vtemp168,127,0,4);
+    VL_SIGW(__Vtemp169,127,0,4);
+    VL_SIGW(__Vtemp170,127,0,4);
+    VL_SIGW(__Vtemp171,127,0,4);
+    VL_SIGW(__Vtemp172,127,0,4);
+    VL_SIGW(__Vtemp173,127,0,4);
+    VL_SIGW(__Vtemp174,127,0,4);
+    VL_SIGW(__Vtemp175,127,0,4);
+    VL_SIGW(__Vtemp176,127,0,4);
+    VL_SIGW(__Vtemp177,127,0,4);
+    VL_SIGW(__Vtemp178,127,0,4);
+    VL_SIGW(__Vtemp179,127,0,4);
+    VL_SIGW(__Vtemp180,127,0,4);
+    VL_SIGW(__Vtemp181,127,0,4);
+    VL_SIGW(__Vtemp182,127,0,4);
+    VL_SIGW(__Vtemp183,127,0,4);
+    VL_SIGW(__Vtemp184,127,0,4);
+    VL_SIGW(__Vtemp185,127,0,4);
+    VL_SIGW(__Vtemp186,127,0,4);
+    VL_SIGW(__Vtemp187,127,0,4);
+    VL_SIGW(__Vtemp188,127,0,4);
+    VL_SIGW(__Vtemp189,127,0,4);
+    VL_SIGW(__Vtemp190,127,0,4);
+    VL_SIGW(__Vtemp191,127,0,4);
+    VL_SIGW(__Vtemp192,127,0,4);
+    VL_SIGW(__Vtemp193,127,0,4);
+    VL_SIGW(__Vtemp194,127,0,4);
+    VL_SIGW(__Vtemp195,127,0,4);
+    VL_SIGW(__Vtemp196,127,0,4);
+    VL_SIGW(__Vtemp197,127,0,4);
+    VL_SIGW(__Vtemp198,127,0,4);
+    VL_SIGW(__Vtemp199,127,0,4);
+    VL_SIGW(__Vtemp200,127,0,4);
+    VL_SIGW(__Vtemp201,127,0,4);
+    VL_SIGW(__Vtemp202,127,0,4);
+    VL_SIGW(__Vtemp203,127,0,4);
+    VL_SIGW(__Vtemp204,127,0,4);
+    VL_SIGW(__Vtemp205,127,0,4);
+    VL_SIGW(__Vtemp206,127,0,4);
     VL_SIGW(__Vtemp207,127,0,4);
     VL_SIGW(__Vtemp208,127,0,4);
     VL_SIGW(__Vtemp209,127,0,4);
@@ -2208,60 +3081,207 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
     VL_SIGW(__Vtemp534,127,0,4);
     VL_SIGW(__Vtemp535,127,0,4);
     VL_SIGW(__Vtemp536,127,0,4);
-    VL_SIGW(__Vtemp146,127,0,4);
-    VL_SIGW(__Vtemp147,127,0,4);
-    VL_SIGW(__Vtemp148,127,0,4);
-    VL_SIGW(__Vtemp149,127,0,4);
-    VL_SIGW(__Vtemp150,127,0,4);
-    VL_SIGW(__Vtemp151,127,0,4);
-    VL_SIGW(__Vtemp152,127,0,4);
-    VL_SIGW(__Vtemp157,127,0,4);
-    VL_SIGW(__Vtemp158,127,0,4);
-    VL_SIGW(__Vtemp159,127,0,4);
-    VL_SIGW(__Vtemp160,127,0,4);
-    VL_SIGW(__Vtemp161,127,0,4);
-    VL_SIGW(__Vtemp162,127,0,4);
-    VL_SIGW(__Vtemp163,127,0,4);
-    VL_SIGW(__Vtemp164,127,0,4);
-    VL_SIGW(__Vtemp165,127,0,4);
-    VL_SIGW(__Vtemp166,127,0,4);
-    VL_SIGW(__Vtemp167,127,0,4);
-    VL_SIGW(__Vtemp168,127,0,4);
-    VL_SIGW(__Vtemp169,127,0,4);
-    VL_SIGW(__Vtemp170,127,0,4);
-    VL_SIGW(__Vtemp171,127,0,4);
-    VL_SIGW(__Vtemp172,127,0,4);
-    VL_SIGW(__Vtemp173,127,0,4);
-    VL_SIGW(__Vtemp174,127,0,4);
-    VL_SIGW(__Vtemp175,127,0,4);
-    VL_SIGW(__Vtemp176,127,0,4);
-    VL_SIGW(__Vtemp177,127,0,4);
-    VL_SIGW(__Vtemp178,127,0,4);
-    VL_SIGW(__Vtemp179,127,0,4);
-    VL_SIGW(__Vtemp180,127,0,4);
-    VL_SIGW(__Vtemp181,127,0,4);
-    VL_SIGW(__Vtemp182,127,0,4);
-    VL_SIGW(__Vtemp183,127,0,4);
-    VL_SIGW(__Vtemp184,127,0,4);
-    VL_SIGW(__Vtemp185,127,0,4);
-    VL_SIGW(__Vtemp186,127,0,4);
-    VL_SIGW(__Vtemp187,127,0,4);
-    VL_SIGW(__Vtemp188,127,0,4);
-    VL_SIGW(__Vtemp189,127,0,4);
-    VL_SIGW(__Vtemp190,127,0,4);
-    VL_SIGW(__Vtemp191,127,0,4);
-    VL_SIGW(__Vtemp192,127,0,4);
-    VL_SIGW(__Vtemp193,127,0,4);
-    VL_SIGW(__Vtemp196,127,0,4);
-    VL_SIGW(__Vtemp199,127,0,4);
-    VL_SIGW(__Vtemp202,127,0,4);
-    VL_SIGW(__Vtemp205,127,0,4);
-    VL_SIGW(__Vtemp206,127,0,4);
     VL_SIGW(__Vtemp537,127,0,4);
     VL_SIGW(__Vtemp538,127,0,4);
     VL_SIGW(__Vtemp539,127,0,4);
     VL_SIGW(__Vtemp540,127,0,4);
     VL_SIGW(__Vtemp541,127,0,4);
+    VL_SIGW(__Vtemp542,127,0,4);
+    VL_SIGW(__Vtemp543,127,0,4);
+    VL_SIGW(__Vtemp544,127,0,4);
+    VL_SIGW(__Vtemp545,127,0,4);
+    VL_SIGW(__Vtemp546,127,0,4);
+    VL_SIGW(__Vtemp547,127,0,4);
+    VL_SIGW(__Vtemp548,127,0,4);
+    VL_SIGW(__Vtemp549,127,0,4);
+    VL_SIGW(__Vtemp550,127,0,4);
+    VL_SIGW(__Vtemp551,127,0,4);
+    VL_SIGW(__Vtemp552,127,0,4);
+    VL_SIGW(__Vtemp553,127,0,4);
+    VL_SIGW(__Vtemp554,127,0,4);
+    VL_SIGW(__Vtemp555,127,0,4);
+    VL_SIGW(__Vtemp556,127,0,4);
+    VL_SIGW(__Vtemp557,127,0,4);
+    VL_SIGW(__Vtemp558,127,0,4);
+    VL_SIGW(__Vtemp559,127,0,4);
+    VL_SIGW(__Vtemp560,127,0,4);
+    VL_SIGW(__Vtemp561,127,0,4);
+    VL_SIGW(__Vtemp562,127,0,4);
+    VL_SIGW(__Vtemp563,127,0,4);
+    VL_SIGW(__Vtemp564,127,0,4);
+    VL_SIGW(__Vtemp565,127,0,4);
+    VL_SIGW(__Vtemp566,127,0,4);
+    VL_SIGW(__Vtemp567,127,0,4);
+    VL_SIGW(__Vtemp568,127,0,4);
+    VL_SIGW(__Vtemp569,127,0,4);
+    VL_SIGW(__Vtemp570,127,0,4);
+    VL_SIGW(__Vtemp571,127,0,4);
+    VL_SIGW(__Vtemp572,127,0,4);
+    VL_SIGW(__Vtemp573,127,0,4);
+    VL_SIGW(__Vtemp574,127,0,4);
+    VL_SIGW(__Vtemp575,127,0,4);
+    VL_SIGW(__Vtemp576,127,0,4);
+    VL_SIGW(__Vtemp577,127,0,4);
+    VL_SIGW(__Vtemp578,127,0,4);
+    VL_SIGW(__Vtemp579,127,0,4);
+    VL_SIGW(__Vtemp580,127,0,4);
+    VL_SIGW(__Vtemp581,127,0,4);
+    VL_SIGW(__Vtemp582,127,0,4);
+    VL_SIGW(__Vtemp583,127,0,4);
+    VL_SIGW(__Vtemp584,127,0,4);
+    VL_SIGW(__Vtemp585,127,0,4);
+    VL_SIGW(__Vtemp586,127,0,4);
+    VL_SIGW(__Vtemp587,127,0,4);
+    VL_SIGW(__Vtemp588,127,0,4);
+    VL_SIGW(__Vtemp589,127,0,4);
+    VL_SIGW(__Vtemp590,127,0,4);
+    VL_SIGW(__Vtemp591,127,0,4);
+    VL_SIGW(__Vtemp592,127,0,4);
+    VL_SIGW(__Vtemp593,127,0,4);
+    VL_SIGW(__Vtemp594,127,0,4);
+    VL_SIGW(__Vtemp595,127,0,4);
+    VL_SIGW(__Vtemp596,127,0,4);
+    VL_SIGW(__Vtemp597,127,0,4);
+    VL_SIGW(__Vtemp598,127,0,4);
+    VL_SIGW(__Vtemp599,127,0,4);
+    VL_SIGW(__Vtemp600,127,0,4);
+    VL_SIGW(__Vtemp601,127,0,4);
+    VL_SIGW(__Vtemp602,127,0,4);
+    VL_SIGW(__Vtemp603,127,0,4);
+    VL_SIGW(__Vtemp604,127,0,4);
+    VL_SIGW(__Vtemp605,127,0,4);
+    VL_SIGW(__Vtemp606,127,0,4);
+    VL_SIGW(__Vtemp607,127,0,4);
+    VL_SIGW(__Vtemp608,127,0,4);
+    VL_SIGW(__Vtemp609,127,0,4);
+    VL_SIGW(__Vtemp610,127,0,4);
+    VL_SIGW(__Vtemp611,127,0,4);
+    VL_SIGW(__Vtemp612,127,0,4);
+    VL_SIGW(__Vtemp613,127,0,4);
+    VL_SIGW(__Vtemp614,127,0,4);
+    VL_SIGW(__Vtemp615,127,0,4);
+    VL_SIGW(__Vtemp616,127,0,4);
+    VL_SIGW(__Vtemp617,127,0,4);
+    VL_SIGW(__Vtemp618,127,0,4);
+    VL_SIGW(__Vtemp619,127,0,4);
+    VL_SIGW(__Vtemp620,127,0,4);
+    VL_SIGW(__Vtemp621,127,0,4);
+    VL_SIGW(__Vtemp622,127,0,4);
+    VL_SIGW(__Vtemp623,127,0,4);
+    VL_SIGW(__Vtemp624,127,0,4);
+    VL_SIGW(__Vtemp625,127,0,4);
+    VL_SIGW(__Vtemp626,127,0,4);
+    VL_SIGW(__Vtemp627,127,0,4);
+    VL_SIGW(__Vtemp628,127,0,4);
+    VL_SIGW(__Vtemp629,127,0,4);
+    VL_SIGW(__Vtemp630,127,0,4);
+    VL_SIGW(__Vtemp631,127,0,4);
+    VL_SIGW(__Vtemp632,127,0,4);
+    VL_SIGW(__Vtemp633,127,0,4);
+    VL_SIGW(__Vtemp634,127,0,4);
+    VL_SIGW(__Vtemp635,127,0,4);
+    VL_SIGW(__Vtemp636,127,0,4);
+    VL_SIGW(__Vtemp637,127,0,4);
+    VL_SIGW(__Vtemp638,127,0,4);
+    VL_SIGW(__Vtemp639,127,0,4);
+    VL_SIGW(__Vtemp640,127,0,4);
+    VL_SIGW(__Vtemp641,127,0,4);
+    VL_SIGW(__Vtemp642,127,0,4);
+    VL_SIGW(__Vtemp643,127,0,4);
+    VL_SIGW(__Vtemp644,127,0,4);
+    VL_SIGW(__Vtemp645,127,0,4);
+    VL_SIGW(__Vtemp646,127,0,4);
+    VL_SIGW(__Vtemp647,127,0,4);
+    VL_SIGW(__Vtemp648,127,0,4);
+    VL_SIGW(__Vtemp649,127,0,4);
+    VL_SIGW(__Vtemp650,127,0,4);
+    VL_SIGW(__Vtemp651,127,0,4);
+    VL_SIGW(__Vtemp652,127,0,4);
+    VL_SIGW(__Vtemp653,127,0,4);
+    VL_SIGW(__Vtemp654,127,0,4);
+    VL_SIGW(__Vtemp655,127,0,4);
+    VL_SIGW(__Vtemp656,127,0,4);
+    VL_SIGW(__Vtemp657,127,0,4);
+    VL_SIGW(__Vtemp658,127,0,4);
+    VL_SIGW(__Vtemp659,127,0,4);
+    VL_SIGW(__Vtemp660,127,0,4);
+    VL_SIGW(__Vtemp661,127,0,4);
+    VL_SIGW(__Vtemp662,127,0,4);
+    VL_SIGW(__Vtemp663,127,0,4);
+    VL_SIGW(__Vtemp664,127,0,4);
+    VL_SIGW(__Vtemp665,127,0,4);
+    VL_SIGW(__Vtemp666,127,0,4);
+    VL_SIGW(__Vtemp667,127,0,4);
+    VL_SIGW(__Vtemp668,127,0,4);
+    VL_SIGW(__Vtemp669,127,0,4);
+    VL_SIGW(__Vtemp670,127,0,4);
+    VL_SIGW(__Vtemp671,127,0,4);
+    VL_SIGW(__Vtemp672,127,0,4);
+    VL_SIGW(__Vtemp673,127,0,4);
+    VL_SIGW(__Vtemp674,127,0,4);
+    VL_SIGW(__Vtemp81,127,0,4);
+    VL_SIGW(__Vtemp82,127,0,4);
+    VL_SIGW(__Vtemp83,127,0,4);
+    VL_SIGW(__Vtemp84,127,0,4);
+    VL_SIGW(__Vtemp85,127,0,4);
+    VL_SIGW(__Vtemp90,127,0,4);
+    VL_SIGW(__Vtemp91,127,0,4);
+    VL_SIGW(__Vtemp92,127,0,4);
+    VL_SIGW(__Vtemp93,127,0,4);
+    VL_SIGW(__Vtemp94,127,0,4);
+    VL_SIGW(__Vtemp95,127,0,4);
+    VL_SIGW(__Vtemp96,127,0,4);
+    VL_SIGW(__Vtemp97,127,0,4);
+    VL_SIGW(__Vtemp98,127,0,4);
+    VL_SIGW(__Vtemp99,127,0,4);
+    VL_SIGW(__Vtemp100,127,0,4);
+    VL_SIGW(__Vtemp101,127,0,4);
+    VL_SIGW(__Vtemp102,127,0,4);
+    VL_SIGW(__Vtemp103,127,0,4);
+    VL_SIGW(__Vtemp104,127,0,4);
+    VL_SIGW(__Vtemp105,127,0,4);
+    VL_SIGW(__Vtemp106,127,0,4);
+    VL_SIGW(__Vtemp107,127,0,4);
+    VL_SIGW(__Vtemp108,127,0,4);
+    VL_SIGW(__Vtemp109,127,0,4);
+    VL_SIGW(__Vtemp110,127,0,4);
+    VL_SIGW(__Vtemp111,127,0,4);
+    VL_SIGW(__Vtemp112,127,0,4);
+    VL_SIGW(__Vtemp113,127,0,4);
+    VL_SIGW(__Vtemp114,127,0,4);
+    VL_SIGW(__Vtemp115,127,0,4);
+    VL_SIGW(__Vtemp116,127,0,4);
+    VL_SIGW(__Vtemp117,127,0,4);
+    VL_SIGW(__Vtemp118,127,0,4);
+    VL_SIGW(__Vtemp119,127,0,4);
+    VL_SIGW(__Vtemp120,127,0,4);
+    VL_SIGW(__Vtemp121,127,0,4);
+    VL_SIGW(__Vtemp122,127,0,4);
+    VL_SIGW(__Vtemp123,127,0,4);
+    VL_SIGW(__Vtemp124,127,0,4);
+    VL_SIGW(__Vtemp125,127,0,4);
+    VL_SIGW(__Vtemp126,127,0,4);
+    VL_SIGW(__Vtemp127,127,0,4);
+    VL_SIGW(__Vtemp128,127,0,4);
+    VL_SIGW(__Vtemp129,127,0,4);
+    VL_SIGW(__Vtemp130,127,0,4);
+    VL_SIGW(__Vtemp131,127,0,4);
+    VL_SIGW(__Vtemp132,127,0,4);
+    VL_SIGW(__Vtemp133,127,0,4);
+    VL_SIGW(__Vtemp134,127,0,4);
+    VL_SIGW(__Vtemp137,127,0,4);
+    VL_SIGW(__Vtemp140,127,0,4);
+    VL_SIGW(__Vtemp143,127,0,4);
+    VL_SIGW(__Vtemp146,127,0,4);
+    VL_SIGW(__Vtemp675,127,0,4);
+    VL_SIGW(__Vtemp676,127,0,4);
+    VL_SIGW(__Vtemp677,127,0,4);
+    VL_SIGW(__Vtemp678,127,0,4);
+    VL_SIGW(__Vtemp679,127,0,4);
+    VL_SIGW(__Vtemp680,127,0,4);
+    VL_SIGW(__Vtemp681,127,0,4);
+    VL_SIGW(__Vtemp682,127,0,4);
+    VL_SIGW(__Vtemp683,127,0,4);
     // Body
     {
 	vcdp->fullBit  (c+1,((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
@@ -2277,23 +3297,23 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 	vcdp->fullBus  (c+11,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read),3);
 	vcdp->fullBus  (c+12,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write),3);
 	vcdp->fullArray(c+13,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual),128);
-	__Vtemp146[0U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
-			   & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
-			   ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U]
-			   : 0U);
-	__Vtemp146[1U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
-			   & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
-			   ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U]
-			   : 0U);
-	__Vtemp146[2U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
-			   & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
-			   ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U]
-			   : 0U);
-	__Vtemp146[3U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
-			   & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
-			   ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U]
-			   : 0U);
-	vcdp->fullArray(c+17,(__Vtemp146),128);
+	__Vtemp81[0U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+			  & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
+			  ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U]
+			  : 0U);
+	__Vtemp81[1U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+			  & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
+			  ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U]
+			  : 0U);
+	__Vtemp81[2U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+			  & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
+			  ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U]
+			  : 0U);
+	__Vtemp81[3U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+			  & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
+			  ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U]
+			  : 0U);
+	vcdp->fullArray(c+17,(__Vtemp81),128);
 	vcdp->fullBus  (c+21,((0xfU & (((~ (IData)(
 						   (0U 
 						    != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
@@ -2349,37 +3369,37 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 	vcdp->fullBit  (c+103,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found));
 	vcdp->fullBus  (c+104,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i),32);
 	vcdp->fullBus  (c+105,((0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)),7);
-	__Vtemp147[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U];
-	__Vtemp147[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U];
-	__Vtemp147[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U];
-	__Vtemp147[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U];
-	vcdp->fullArray(c+106,(__Vtemp147),128);
+	__Vtemp82[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U];
+	__Vtemp82[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U];
+	__Vtemp82[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U];
+	__Vtemp82[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U];
+	vcdp->fullArray(c+106,(__Vtemp82),128);
 	vcdp->fullBus  (c+110,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we))),2);
 	vcdp->fullBus  (c+111,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 					 >> 7U))),7);
-	__Vtemp148[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U];
-	__Vtemp148[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U];
-	__Vtemp148[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U];
-	__Vtemp148[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U];
-	vcdp->fullArray(c+112,(__Vtemp148),128);
+	__Vtemp83[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U];
+	__Vtemp83[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U];
+	__Vtemp83[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U];
+	__Vtemp83[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U];
+	vcdp->fullArray(c+112,(__Vtemp83),128);
 	vcdp->fullBus  (c+116,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
 				      >> 2U))),2);
 	vcdp->fullBus  (c+117,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 					 >> 0xeU))),7);
-	__Vtemp149[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U];
-	__Vtemp149[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U];
-	__Vtemp149[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU];
-	__Vtemp149[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU];
-	vcdp->fullArray(c+118,(__Vtemp149),128);
+	__Vtemp84[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U];
+	__Vtemp84[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U];
+	__Vtemp84[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU];
+	__Vtemp84[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU];
+	vcdp->fullArray(c+118,(__Vtemp84),128);
 	vcdp->fullBus  (c+122,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
 				      >> 4U))),2);
 	vcdp->fullBus  (c+123,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 					 >> 0x15U))),7);
-	__Vtemp150[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU];
-	__Vtemp150[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU];
-	__Vtemp150[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU];
-	__Vtemp150[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU];
-	vcdp->fullArray(c+124,(__Vtemp150),128);
+	__Vtemp85[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU];
+	__Vtemp85[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU];
+	__Vtemp85[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU];
+	__Vtemp85[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU];
+	vcdp->fullArray(c+124,(__Vtemp85),128);
 	vcdp->fullBus  (c+128,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) 
 				      >> 6U))),2);
 	vcdp->fullBus  (c+129,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[0U])),32);
@@ -2435,246 +3455,783 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 	vcdp->fullBus  (c+194,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2);
 	vcdp->fullBus  (c+195,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
 					     >> 0xbU))),21);
-	vcdp->fullBit  (c+196,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank))));
-	vcdp->fullBit  (c+197,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
-	vcdp->fullBus  (c+198,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32);
-	vcdp->fullBus  (c+199,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2);
-	vcdp->fullBus  (c+200,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+	vcdp->fullBus  (c+196,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+				      >> 4U))),2);
+	vcdp->fullBus  (c+197,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					 >> 6U))),5);
+	vcdp->fullBit  (c+198,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank))));
+	vcdp->fullBit  (c+199,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
+	vcdp->fullBus  (c+200,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32);
+	vcdp->fullBus  (c+201,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2);
+	vcdp->fullBus  (c+202,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
 					     >> 0xbU))),21);
-	vcdp->fullBit  (c+201,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
+	vcdp->fullBus  (c+203,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+				      >> 4U))),2);
+	vcdp->fullBus  (c+204,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					 >> 6U))),5);
+	vcdp->fullBit  (c+205,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
 				      >> 1U))));
-	vcdp->fullBit  (c+202,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
-	vcdp->fullBus  (c+203,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32);
-	vcdp->fullBus  (c+204,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2);
-	vcdp->fullBus  (c+205,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+	vcdp->fullBit  (c+206,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
+	vcdp->fullBus  (c+207,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32);
+	vcdp->fullBus  (c+208,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2);
+	vcdp->fullBus  (c+209,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
 					     >> 0xbU))),21);
-	vcdp->fullBit  (c+206,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
+	vcdp->fullBus  (c+210,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+				      >> 4U))),2);
+	vcdp->fullBus  (c+211,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					 >> 6U))),5);
+	vcdp->fullBit  (c+212,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
 				      >> 2U))));
-	vcdp->fullBit  (c+207,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
-	vcdp->fullBus  (c+208,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32);
-	vcdp->fullBus  (c+209,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2);
-	vcdp->fullBus  (c+210,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+	vcdp->fullBit  (c+213,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
+	vcdp->fullBus  (c+214,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32);
+	vcdp->fullBus  (c+215,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2);
+	vcdp->fullBus  (c+216,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
 					     >> 0xbU))),21);
-	vcdp->fullBit  (c+211,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
+	vcdp->fullBus  (c+217,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+				      >> 4U))),2);
+	vcdp->fullBus  (c+218,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					 >> 6U))),5);
+	vcdp->fullBit  (c+219,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) 
 				      >> 3U))));
-	vcdp->fullBit  (c+212,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
-	vcdp->fullBus  (c+213,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i),32);
-	vcdp->fullBus  (c+214,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)
+	vcdp->fullBit  (c+220,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
+	vcdp->fullBus  (c+221,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i),32);
+	vcdp->fullBus  (c+222,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)
 					 ? ((IData)(1U) 
 					    << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index))
 					 : 0U))),4);
-	vcdp->fullBus  (c+215,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),2);
-	vcdp->fullBit  (c+216,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found));
-	vcdp->fullBus  (c+217,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i),32);
-	vcdp->fullBus  (c+218,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)
+	vcdp->fullBus  (c+223,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),2);
+	vcdp->fullBit  (c+224,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->fullBus  (c+225,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i),32);
+	vcdp->fullBus  (c+226,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)
 					 ? ((IData)(1U) 
 					    << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index))
 					 : 0U))),4);
-	vcdp->fullBus  (c+219,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index),2);
-	vcdp->fullBit  (c+220,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found));
-	vcdp->fullBus  (c+221,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i),32);
-	vcdp->fullBus  (c+222,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)
+	vcdp->fullBus  (c+227,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index),2);
+	vcdp->fullBit  (c+228,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->fullBus  (c+229,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i),32);
+	vcdp->fullBus  (c+230,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)
 					 ? ((IData)(1U) 
 					    << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index))
 					 : 0U))),4);
-	vcdp->fullBus  (c+223,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index),2);
-	vcdp->fullBit  (c+224,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found));
-	vcdp->fullBus  (c+225,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i),32);
-	vcdp->fullBus  (c+226,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)
+	vcdp->fullBus  (c+231,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index),2);
+	vcdp->fullBit  (c+232,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->fullBus  (c+233,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i),32);
+	vcdp->fullBus  (c+234,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)
 					 ? ((IData)(1U) 
 					    << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index))
 					 : 0U))),4);
-	vcdp->fullBus  (c+227,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index),2);
-	vcdp->fullBit  (c+228,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found));
-	vcdp->fullBus  (c+229,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i),32);
-	vcdp->fullBus  (c+230,((0xfffffff0U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
-					       << 9U))),32);
-	vcdp->fullBus  (c+231,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read),32);
-	vcdp->fullBus  (c+232,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks),1);
-	vcdp->fullBus  (c+233,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),1);
-	vcdp->fullBus  (c+234,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)
+	vcdp->fullBus  (c+235,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index),2);
+	vcdp->fullBit  (c+236,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->fullBus  (c+237,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i),32);
+	vcdp->fullBus  (c+238,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank[0U])),32);
+	vcdp->fullArray(c+239,(vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata),512);
+	vcdp->fullBus  (c+255,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read),32);
+	vcdp->fullBus  (c+256,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks),4);
+	vcdp->fullBus  (c+257,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank),4);
+	vcdp->fullBus  (c+258,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank),4);
+	vcdp->fullBus  (c+259,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank),4);
+	vcdp->fullBus  (c+260,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank),4);
+	vcdp->fullArray(c+261,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank),128);
+	vcdp->fullBus  (c+265,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank),4);
+	vcdp->fullBus  (c+266,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb),4);
+	vcdp->fullBus  (c+267,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state),4);
+	vcdp->fullBus  (c+268,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid),1);
+	vcdp->fullBus  (c+269,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid),1);
+	vcdp->fullArray(c+270,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank),128);
+	vcdp->fullBus  (c+274,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual),1);
+	vcdp->fullBus  (c+275,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0]),1);
+	vcdp->fullBus  (c+276,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[1]),1);
+	vcdp->fullBus  (c+277,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[2]),1);
+	vcdp->fullBus  (c+278,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[3]),1);
+	vcdp->fullBus  (c+279,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss),4);
+	vcdp->fullBus  (c+280,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index),2);
+	vcdp->fullBit  (c+281,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found));
+	vcdp->fullBus  (c+282,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks))),1);
+	vcdp->fullBus  (c+283,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank))),1);
+	vcdp->fullBit  (c+284,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank))));
+	vcdp->fullBus  (c+285,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[0U]),32);
+	vcdp->fullBus  (c+286,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) 
+				      >> 1U))),1);
+	vcdp->fullBus  (c+287,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank) 
+				      >> 1U))),1);
+	vcdp->fullBit  (c+288,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) 
+				      >> 1U))));
+	vcdp->fullBus  (c+289,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[1U]),32);
+	vcdp->fullBus  (c+290,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) 
+				      >> 2U))),1);
+	vcdp->fullBus  (c+291,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank) 
+				      >> 2U))),1);
+	vcdp->fullBit  (c+292,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) 
+				      >> 2U))));
+	vcdp->fullBus  (c+293,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[2U]),32);
+	vcdp->fullBus  (c+294,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) 
+				      >> 3U))),1);
+	vcdp->fullBus  (c+295,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank) 
+				      >> 3U))),1);
+	vcdp->fullBit  (c+296,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) 
+				      >> 3U))));
+	vcdp->fullBus  (c+297,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank[3U]),32);
+	vcdp->fullBus  (c+298,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32);
+	vcdp->fullBus  (c+299,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2);
+	vcdp->fullBus  (c+300,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					     >> 0xbU))),21);
+	vcdp->fullBus  (c+301,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+				      >> 4U))),2);
+	vcdp->fullBus  (c+302,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					 >> 6U))),5);
+	vcdp->fullBit  (c+303,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank))));
+	vcdp->fullBit  (c+304,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
+	vcdp->fullBus  (c+305,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32);
+	vcdp->fullBus  (c+306,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2);
+	vcdp->fullBus  (c+307,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					     >> 0xbU))),21);
+	vcdp->fullBus  (c+308,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+				      >> 4U))),2);
+	vcdp->fullBus  (c+309,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					 >> 6U))),5);
+	vcdp->fullBit  (c+310,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+				      >> 1U))));
+	vcdp->fullBit  (c+311,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in));
+	vcdp->fullBus  (c+312,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32);
+	vcdp->fullBus  (c+313,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2);
+	vcdp->fullBus  (c+314,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					     >> 0xbU))),21);
+	vcdp->fullBus  (c+315,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+				      >> 4U))),2);
+	vcdp->fullBus  (c+316,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					 >> 6U))),5);
+	vcdp->fullBit  (c+317,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+				      >> 2U))));
+	vcdp->fullBit  (c+318,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in));
+	vcdp->fullBus  (c+319,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32);
+	vcdp->fullBus  (c+320,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2);
+	vcdp->fullBus  (c+321,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					     >> 0xbU))),21);
+	vcdp->fullBus  (c+322,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+				      >> 4U))),2);
+	vcdp->fullBus  (c+323,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					 >> 6U))),5);
+	vcdp->fullBit  (c+324,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) 
+				      >> 3U))));
+	vcdp->fullBit  (c+325,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in));
+	vcdp->fullBus  (c+326,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i),32);
+	vcdp->fullBus  (c+327,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)
 				       ? ((IData)(1U) 
 					  << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index))
 				       : 0U))),1);
-	vcdp->fullBus  (c+235,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank),1);
-	vcdp->fullBus  (c+236,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank),1);
-	vcdp->fullBus  (c+237,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)
+	vcdp->fullBus  (c+328,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),1);
+	vcdp->fullBit  (c+329,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->fullBus  (c+330,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)
+				       ? ((IData)(1U) 
+					  << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index))
+				       : 0U))),1);
+	vcdp->fullBus  (c+331,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index),1);
+	vcdp->fullBit  (c+332,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->fullBus  (c+333,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)
+				       ? ((IData)(1U) 
+					  << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index))
+				       : 0U))),1);
+	vcdp->fullBus  (c+334,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index),1);
+	vcdp->fullBit  (c+335,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->fullBus  (c+336,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)
+				       ? ((IData)(1U) 
+					  << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index))
+				       : 0U))),1);
+	vcdp->fullBus  (c+337,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index),1);
+	vcdp->fullBit  (c+338,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found));
+	vcdp->fullBus  (c+339,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid),4);
+	__Vtemp90[0U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
+					      << 8U) 
+					     | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
+						>> 0x18U))))
+			  ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+			      & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
+			      ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U]
+			      : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U]);
+	__Vtemp90[1U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
+					      << 8U) 
+					     | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
+						>> 0x18U))))
+			  ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+			      & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
+			      ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U]
+			      : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U]);
+	__Vtemp90[2U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
+					      << 8U) 
+					     | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
+						>> 0x18U))))
+			  ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+			      & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
+			      ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U]
+			      : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U]);
+	__Vtemp90[3U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
+					      << 8U) 
+					     | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
+						>> 0x18U))))
+			  ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
+			      & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
+			      ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U]
+			      : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U]);
+	vcdp->fullArray(c+340,(__Vtemp90),128);
+	vcdp->fullBus  (c+344,(0U),32);
+	vcdp->fullBus  (c+345,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
 				 ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-				     ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
+				     ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 					 ? (0xffffff00U 
-					    | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-					 : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
+					    | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+					 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
 				     : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
 					 ? ((0x8000U 
-					     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
+					     & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 					     ? (0xffff0000U 
-						| vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
+						| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 					     : (0xffffU 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
 					 : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
 					     ? (0xffffU 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 					     : ((4U 
 						 == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
 						 ? 
 						(0xffU 
-						 & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-						 : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+						 : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))
 				 : 0U)),32);
-	vcdp->fullBus  (c+238,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank),1);
-	vcdp->fullBus  (c+239,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state),4);
-	vcdp->fullBus  (c+240,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid),1);
-	vcdp->fullBus  (c+241,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid),1);
-	vcdp->fullBus  (c+242,((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
-				<< 9U)),32);
-	vcdp->fullBus  (c+243,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank),1);
-	vcdp->fullBus  (c+244,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0]),1);
-	vcdp->fullBus  (c+245,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss),1);
-	vcdp->fullBus  (c+246,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index),1);
-	vcdp->fullBit  (c+247,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found));
-	vcdp->fullBit  (c+248,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank));
-	vcdp->fullBus  (c+249,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32);
-	vcdp->fullBus  (c+250,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2);
-	vcdp->fullBus  (c+251,((0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-					     >> 9U))),23);
-	vcdp->fullBit  (c+252,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank));
-	vcdp->fullBit  (c+253,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in));
-	vcdp->fullBus  (c+254,(0U),32);
-	vcdp->fullBus  (c+255,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use),23);
-	vcdp->fullBit  (c+256,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use));
-	vcdp->fullBit  (c+257,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access));
-	vcdp->fullBit  (c+258,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem));
-	vcdp->fullBit  (c+259,((((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use 
-				  != (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-						   >> 9U))) 
-				 & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)) 
+	vcdp->fullBit  (c+346,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) 
+				 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
+				    == (0x1fffffU & 
+					(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					 >> 0xbU)))) 
+				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use))));
+	vcdp->fullBit  (c+347,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				      >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->fullBus  (c+348,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
+				 << 0xbU) | (0x7c0U 
+					     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))),32);
+	vcdp->fullArray(c+349,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->fullBus  (c+353,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->fullBit  (c+354,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->fullBit  (c+355,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access));
+	vcdp->fullBit  (c+356,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->fullBit  (c+357,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
+				  != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+						   >> 0xbU))) 
+				 & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)) 
 				& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in))));
-	vcdp->fullBit  (c+260,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
-	vcdp->fullBit  (c+261,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
-	vcdp->fullBit  (c+262,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
-	vcdp->fullBit  (c+263,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
-	vcdp->fullBit  (c+264,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
-	vcdp->fullBit  (c+265,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+266,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+267,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+268,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->fullBus  (c+269,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual),32);
-	vcdp->fullBus  (c+270,(((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				 ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				 : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32);
-	vcdp->fullBus  (c+271,(((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				 ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				 : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32);
-	vcdp->fullBus  (c+272,((0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32);
-	vcdp->fullBus  (c+273,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32);
-	vcdp->fullBus  (c+274,(0U),32);
-	vcdp->fullBus  (c+275,(0U),32);
-	vcdp->fullBus  (c+276,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-				 ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
+	vcdp->fullBit  (c+358,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
+	vcdp->fullBit  (c+359,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
+	vcdp->fullBit  (c+360,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
+	vcdp->fullBit  (c+361,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
+	vcdp->fullBit  (c+362,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))));
+	vcdp->fullBit  (c+363,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+364,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+365,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+366,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->fullBus  (c+367,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->fullBus  (c+368,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				 ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->fullBus  (c+369,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				 ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				 : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->fullBus  (c+370,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+371,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+372,(0U),32);
+	vcdp->fullBus  (c+373,(0U),32);
+	vcdp->fullBus  (c+374,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				 ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 				     ? (0xffffff00U 
-					| vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-				     : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
+					| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+				     : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
 				 : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
-				     ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
+				     ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 					 ? (0xffff0000U 
-					    | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
+					    | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 					 : (0xffffU 
-					    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))
 				     : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
 					 ? (0xffffU 
-					    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 					 : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
 					     ? (0xffU 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)
-					     : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))),32);
-	vcdp->fullBus  (c+277,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-				 ? 1U : ((1U == (3U 
-						 & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-					  ? 2U : ((2U 
-						   == 
-						   (3U 
-						    & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-						   ? 4U
-						   : 8U)))),4);
-	vcdp->fullBus  (c+278,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+					     : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
+	vcdp->fullBus  (c+375,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->fullBus  (c+376,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 				 ? 3U : 0xcU)),4);
-	vcdp->fullBus  (c+279,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we),16);
-	vcdp->fullArray(c+280,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write),128);
-	vcdp->fullBus  (c+284,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way),2);
-	vcdp->fullBus  (c+285,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way),32);
-	vcdp->fullArray(c+286,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way),256);
-	vcdp->fullBus  (c+294,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way),2);
-	vcdp->fullBus  (c+295,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index),1);
-	vcdp->fullBus  (c+296,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual),1);
-	vcdp->fullBit  (c+297,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
-	vcdp->fullBus  (c+298,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)),16);
-	vcdp->fullBit  (c+299,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))));
-	__Vtemp151[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U];
-	__Vtemp151[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U];
-	__Vtemp151[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U];
-	__Vtemp151[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U];
-	vcdp->fullArray(c+300,(__Vtemp151),128);
-	vcdp->fullBit  (c+304,((0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))));
-	vcdp->fullBit  (c+305,((1U & ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->fullBus  (c+377,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->fullArray(c+378,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->fullQuad (c+382,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->fullArray(c+384,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->fullBus  (c+392,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->fullBus  (c+393,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->fullBus  (c+394,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->fullBus  (c+395,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->fullArray(c+396,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->fullBus  (c+404,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->fullBit  (c+405,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->fullBus  (c+406,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->fullBus  (c+407,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->fullBus  (c+408,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->fullBus  (c+409,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->fullBit  (c+410,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->fullBus  (c+411,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->fullBit  (c+412,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp91[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp91[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp91[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp91[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->fullArray(c+413,(__Vtemp91),128);
+	vcdp->fullBit  (c+417,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+418,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->fullBit  (c+419,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				      | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->fullBit  (c+420,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				       ? 0U : (0U != 
 					       (0xffffU 
-						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))))));
-	vcdp->fullBus  (c+306,((0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
+	vcdp->fullBus  (c+421,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 					   >> 0x10U))),16);
-	vcdp->fullBit  (c+307,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) 
+	vcdp->fullBit  (c+422,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
 				      >> 1U))));
-	__Vtemp152[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U];
-	__Vtemp152[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U];
-	__Vtemp152[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U];
-	__Vtemp152[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U];
-	vcdp->fullArray(c+308,(__Vtemp152),128);
-	vcdp->fullBit  (c+312,((0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
+	__Vtemp92[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp92[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp92[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp92[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->fullArray(c+423,(__Vtemp92),128);
+	vcdp->fullBit  (c+427,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+428,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						  >> 0x10U)))));
-	vcdp->fullBit  (c+313,((1U & ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->fullBit  (c+429,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						    >> 0x10U)))) 
+				      | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					 >> 1U)))));
+	vcdp->fullBit  (c+430,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				       ? 0U : (0U != 
 					       (0xffffU 
-						& (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						   >> 0x10U)))))));
-	vcdp->fullBus  (c+314,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid),4);
-	__Vtemp157[0U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
-					       << 8U) 
-					      | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
-						 >> 0x18U))))
-			   ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
-			       & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
-			       ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U]
-			       : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U]);
-	__Vtemp157[1U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
-					       << 8U) 
-					      | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
-						 >> 0x18U))))
-			   ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
-			       & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
-			       ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U]
-			       : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U]);
-	__Vtemp157[2U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
-					       << 8U) 
-					      | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
-						 >> 0x18U))))
-			   ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
-			       & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
-			       ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U]
-			       : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U]);
-	__Vtemp157[3U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] 
-					       << 8U) 
-					      | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] 
-						 >> 0x18U))))
-			   ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) 
-			       & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)))
-			       ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U]
-			       : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U]);
-	vcdp->fullArray(c+315,(__Vtemp157),128);
-	__Vtemp158[0U] = 0U;
-	__Vtemp158[1U] = 0U;
-	__Vtemp158[2U] = 0U;
-	__Vtemp158[3U] = 0U;
-	vcdp->fullBus  (c+319,(__Vtemp158[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]),32);
-	vcdp->fullBus  (c+320,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
+	vcdp->fullBus  (c+431,(0U),32);
+	vcdp->fullBus  (c+432,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
+				 ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				     ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					 ? (0xffffff00U 
+					    | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
+				     : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					 ? ((0x8000U 
+					     & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					     ? (0xffff0000U 
+						| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					     : (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
+					 : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					     ? (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					     : ((4U 
+						 == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+						 ? 
+						(0xffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+						 : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))
+				 : 0U)),32);
+	vcdp->fullBit  (c+433,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) 
+				 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
+				    == (0x1fffffU & 
+					(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					 >> 0xbU)))) 
+				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use))));
+	vcdp->fullBit  (c+434,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				      >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->fullBus  (c+435,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
+				 << 0xbU) | (0x7c0U 
+					     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))),32);
+	vcdp->fullArray(c+436,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->fullBus  (c+440,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->fullBit  (c+441,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->fullBit  (c+442,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access));
+	vcdp->fullBit  (c+443,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->fullBit  (c+444,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
+				  != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+						   >> 0xbU))) 
+				 & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)) 
+				& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in))));
+	vcdp->fullBit  (c+445,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+446,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+447,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+448,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->fullBus  (c+449,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->fullBus  (c+450,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				 ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->fullBus  (c+451,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				 ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				 : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->fullBus  (c+452,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+453,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+454,(0U),32);
+	vcdp->fullBus  (c+455,(0U),32);
+	vcdp->fullBus  (c+456,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				 ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				     ? (0xffffff00U 
+					| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+				     : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
+				 : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				     ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					 ? (0xffff0000U 
+					    | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					 : (0xffffU 
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))
+				     : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					 ? (0xffffU 
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					 : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					     ? (0xffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+					     : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
+	vcdp->fullBus  (c+457,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->fullBus  (c+458,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+				 ? 3U : 0xcU)),4);
+	vcdp->fullBus  (c+459,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->fullArray(c+460,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->fullQuad (c+464,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->fullArray(c+466,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->fullBus  (c+474,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->fullBus  (c+475,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->fullBus  (c+476,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->fullBus  (c+477,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->fullArray(c+478,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->fullBus  (c+486,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->fullBit  (c+487,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->fullBus  (c+488,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->fullBus  (c+489,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->fullBus  (c+490,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->fullBus  (c+491,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->fullBit  (c+492,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->fullBus  (c+493,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->fullBit  (c+494,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp93[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp93[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp93[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp93[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->fullArray(c+495,(__Vtemp93),128);
+	vcdp->fullBit  (c+499,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+500,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->fullBit  (c+501,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				      | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->fullBit  (c+502,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				       ? 0U : (0U != 
+					       (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
+	vcdp->fullBus  (c+503,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+					   >> 0x10U))),16);
+	vcdp->fullBit  (c+504,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+				      >> 1U))));
+	__Vtemp94[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp94[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp94[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp94[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->fullArray(c+505,(__Vtemp94),128);
+	vcdp->fullBit  (c+509,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+510,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						  >> 0x10U)))));
+	vcdp->fullBit  (c+511,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						    >> 0x10U)))) 
+				      | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					 >> 1U)))));
+	vcdp->fullBit  (c+512,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				       ? 0U : (0U != 
+					       (0xffffU 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))))));
+	vcdp->fullBus  (c+513,(0U),32);
+	vcdp->fullBus  (c+514,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
+				 ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				     ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					 ? (0xffffff00U 
+					    | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
+				     : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					 ? ((0x8000U 
+					     & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					     ? (0xffff0000U 
+						| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					     : (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
+					 : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					     ? (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					     : ((4U 
+						 == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+						 ? 
+						(0xffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+						 : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))
+				 : 0U)),32);
+	vcdp->fullBit  (c+515,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) 
+				 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
+				    == (0x1fffffU & 
+					(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					 >> 0xbU)))) 
+				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use))));
+	vcdp->fullBit  (c+516,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				      >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->fullBus  (c+517,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
+				 << 0xbU) | (0x7c0U 
+					     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))),32);
+	vcdp->fullArray(c+518,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->fullBus  (c+522,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->fullBit  (c+523,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->fullBit  (c+524,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access));
+	vcdp->fullBit  (c+525,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->fullBit  (c+526,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
+				  != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+						   >> 0xbU))) 
+				 & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)) 
+				& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in))));
+	vcdp->fullBit  (c+527,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+528,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+529,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+530,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->fullBus  (c+531,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->fullBus  (c+532,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				 ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->fullBus  (c+533,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				 ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				 : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->fullBus  (c+534,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+535,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+536,(0U),32);
+	vcdp->fullBus  (c+537,(0U),32);
+	vcdp->fullBus  (c+538,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				 ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				     ? (0xffffff00U 
+					| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+				     : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
+				 : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				     ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					 ? (0xffff0000U 
+					    | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					 : (0xffffU 
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))
+				     : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					 ? (0xffffU 
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					 : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					     ? (0xffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+					     : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
+	vcdp->fullBus  (c+539,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->fullBus  (c+540,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+				 ? 3U : 0xcU)),4);
+	vcdp->fullBus  (c+541,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->fullArray(c+542,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->fullQuad (c+546,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->fullArray(c+548,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->fullBus  (c+556,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->fullBus  (c+557,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->fullBus  (c+558,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->fullBus  (c+559,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->fullArray(c+560,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->fullBus  (c+568,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->fullBit  (c+569,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->fullBus  (c+570,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->fullBus  (c+571,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->fullBus  (c+572,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->fullBus  (c+573,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->fullBit  (c+574,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->fullBus  (c+575,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->fullBit  (c+576,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp95[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp95[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp95[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp95[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->fullArray(c+577,(__Vtemp95),128);
+	vcdp->fullBit  (c+581,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+582,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->fullBit  (c+583,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				      | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->fullBit  (c+584,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				       ? 0U : (0U != 
+					       (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
+	vcdp->fullBus  (c+585,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+					   >> 0x10U))),16);
+	vcdp->fullBit  (c+586,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+				      >> 1U))));
+	__Vtemp96[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp96[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp96[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp96[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->fullArray(c+587,(__Vtemp96),128);
+	vcdp->fullBit  (c+591,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+592,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						  >> 0x10U)))));
+	vcdp->fullBit  (c+593,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						    >> 0x10U)))) 
+				      | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					 >> 1U)))));
+	vcdp->fullBit  (c+594,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				       ? 0U : (0U != 
+					       (0xffffU 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))))));
+	vcdp->fullBus  (c+595,(0U),32);
+	vcdp->fullBus  (c+596,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
+				 ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				     ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					 ? (0xffffff00U 
+					    | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
+				     : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					 ? ((0x8000U 
+					     & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					     ? (0xffff0000U 
+						| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					     : (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
+					 : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					     ? (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					     : ((4U 
+						 == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+						 ? 
+						(0xffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+						 : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))
+				 : 0U)),32);
+	vcdp->fullBit  (c+597,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) 
+				 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
+				    == (0x1fffffU & 
+					(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					 >> 0xbU)))) 
+				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use))));
+	vcdp->fullBit  (c+598,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				      >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->fullBus  (c+599,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
+				 << 0xbU) | (0x7c0U 
+					     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))),32);
+	vcdp->fullArray(c+600,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->fullBus  (c+604,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->fullBit  (c+605,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->fullBit  (c+606,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access));
+	vcdp->fullBit  (c+607,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->fullBit  (c+608,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
+				  != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+						   >> 0xbU))) 
+				 & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)) 
+				& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in))));
+	vcdp->fullBit  (c+609,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+610,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+611,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+612,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->fullBus  (c+613,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->fullBus  (c+614,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				 ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->fullBus  (c+615,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				 ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				 : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
+	vcdp->fullBus  (c+616,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+617,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+618,(0U),32);
+	vcdp->fullBus  (c+619,(0U),32);
+	vcdp->fullBus  (c+620,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				 ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				     ? (0xffffff00U 
+					| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+				     : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
+				 : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+				     ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					 ? (0xffff0000U 
+					    | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					 : (0xffffU 
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))
+				     : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					 ? (0xffffU 
+					    & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					 : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))
+					     ? (0xffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+					     : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
+	vcdp->fullBus  (c+621,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->fullBus  (c+622,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+				 ? 3U : 0xcU)),4);
+	vcdp->fullBus  (c+623,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->fullArray(c+624,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->fullQuad (c+628,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->fullArray(c+630,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->fullBus  (c+638,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->fullBus  (c+639,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->fullBus  (c+640,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->fullBus  (c+641,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->fullArray(c+642,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->fullBus  (c+650,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->fullBit  (c+651,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->fullBus  (c+652,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->fullBus  (c+653,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->fullBus  (c+654,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->fullBus  (c+655,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->fullBit  (c+656,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->fullBus  (c+657,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->fullBit  (c+658,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp97[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp97[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp97[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp97[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->fullArray(c+659,(__Vtemp97),128);
+	vcdp->fullBit  (c+663,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+664,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->fullBit  (c+665,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				      | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->fullBit  (c+666,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				       ? 0U : (0U != 
+					       (0xffffU 
+						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
+	vcdp->fullBus  (c+667,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+					   >> 0x10U))),16);
+	vcdp->fullBit  (c+668,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+				      >> 1U))));
+	__Vtemp98[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp98[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp98[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp98[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->fullArray(c+669,(__Vtemp98),128);
+	vcdp->fullBit  (c+673,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+674,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						  >> 0x10U)))));
+	vcdp->fullBit  (c+675,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						    >> 0x10U)))) 
+				      | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					 >> 1U)))));
+	vcdp->fullBit  (c+676,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				       ? 0U : (0U != 
+					       (0xffffU 
+						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))))));
+	__Vtemp99[0U] = 0U;
+	__Vtemp99[1U] = 0U;
+	__Vtemp99[2U] = 0U;
+	__Vtemp99[3U] = 0U;
+	vcdp->fullBus  (c+677,(__Vtemp99[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]),32);
+	vcdp->fullBus  (c+678,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)
 				 ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				     ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 					 ? (0xffffff00U 
@@ -2697,97 +4254,96 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 						 : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))
 				 : 0U)),32);
-	vcdp->fullBit  (c+321,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) 
+	vcdp->fullBit  (c+679,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) 
 				 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
 				    == (0x1fffffU & 
 					(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
 					 >> 0xbU)))) 
 				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use))));
-	vcdp->fullBus  (c+322,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
-				<< 0xbU)),32);
-	vcdp->fullArray(c+323,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
-	vcdp->fullBus  (c+327,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21);
-	vcdp->fullBit  (c+328,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use));
-	vcdp->fullBit  (c+329,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access));
-	vcdp->fullBit  (c+330,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem));
-	vcdp->fullBit  (c+331,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
-				  != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
-						   >> 0xbU))) 
-				 & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)) 
-				& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in))));
-	vcdp->fullBit  (c+332,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
-	vcdp->fullBit  (c+333,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
-	vcdp->fullBit  (c+334,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
-	vcdp->fullBit  (c+335,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
-	vcdp->fullBit  (c+336,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
-	vcdp->fullBit  (c+337,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
-	vcdp->fullBit  (c+338,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
-	vcdp->fullBit  (c+339,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
-	vcdp->fullBit  (c+340,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+341,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+342,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+343,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
-	vcdp->fullBus  (c+344,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32);
-	vcdp->fullBus  (c+345,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->fullBit  (c+680,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				      >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->fullBus  (c+681,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use 
+				 << 0xbU) | (0x7c0U 
+					     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))),32);
+	vcdp->fullArray(c+682,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->fullBus  (c+686,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->fullBit  (c+687,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->fullBit  (c+688,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access));
+	vcdp->fullBit  (c+689,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->fullBit  (c+690,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__miss));
+	vcdp->fullBit  (c+691,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
+	vcdp->fullBit  (c+692,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
+	vcdp->fullBit  (c+693,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
+	vcdp->fullBit  (c+694,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
+	vcdp->fullBit  (c+695,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))));
+	vcdp->fullBit  (c+696,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
+	vcdp->fullBit  (c+697,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
+	vcdp->fullBit  (c+698,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))));
+	vcdp->fullBit  (c+699,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+700,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+701,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+702,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))));
+	vcdp->fullBus  (c+703,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->fullBus  (c+704,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 				 ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 				 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->fullBus  (c+346,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->fullBus  (c+705,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 				 ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 				 : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->fullBus  (c+347,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	vcdp->fullBus  (c+348,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	__Vtemp159[0U] = 0U;
-	__Vtemp159[1U] = 0U;
-	__Vtemp159[2U] = 0U;
-	__Vtemp159[3U] = 0U;
-	__Vtemp160[0U] = 0U;
-	__Vtemp160[1U] = 0U;
-	__Vtemp160[2U] = 0U;
-	__Vtemp160[3U] = 0U;
-	__Vtemp161[0U] = 0U;
-	__Vtemp161[1U] = 0U;
-	__Vtemp161[2U] = 0U;
-	__Vtemp161[3U] = 0U;
-	__Vtemp162[0U] = 0U;
-	__Vtemp162[1U] = 0U;
-	__Vtemp162[2U] = 0U;
-	__Vtemp162[3U] = 0U;
-	vcdp->fullBus  (c+349,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
-				 ? (0xff00U & (__Vtemp159[
+	vcdp->fullBus  (c+706,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+707,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	__Vtemp100[0U] = 0U;
+	__Vtemp100[1U] = 0U;
+	__Vtemp100[2U] = 0U;
+	__Vtemp100[3U] = 0U;
+	__Vtemp101[0U] = 0U;
+	__Vtemp101[1U] = 0U;
+	__Vtemp101[2U] = 0U;
+	__Vtemp101[3U] = 0U;
+	__Vtemp102[0U] = 0U;
+	__Vtemp102[1U] = 0U;
+	__Vtemp102[2U] = 0U;
+	__Vtemp102[3U] = 0U;
+	__Vtemp103[0U] = 0U;
+	__Vtemp103[1U] = 0U;
+	__Vtemp103[2U] = 0U;
+	__Vtemp103[3U] = 0U;
+	vcdp->fullBus  (c+708,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+				 ? (0xff00U & (__Vtemp100[
 					       (3U 
 						& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 					       << 8U))
 				 : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 				     ? (0xff0000U & 
-					(__Vtemp160[
+					(__Vtemp101[
 					 (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 					 << 0x10U))
 				     : ((3U == (3U 
 						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 					 ? (0xff000000U 
-					    & (__Vtemp161[
+					    & (__Vtemp102[
 					       (3U 
 						& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 					       << 0x18U))
-					 : __Vtemp162[
+					 : __Vtemp103[
 					(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])))),32);
-	__Vtemp163[0U] = 0U;
-	__Vtemp163[1U] = 0U;
-	__Vtemp163[2U] = 0U;
-	__Vtemp163[3U] = 0U;
-	__Vtemp164[0U] = 0U;
-	__Vtemp164[1U] = 0U;
-	__Vtemp164[2U] = 0U;
-	__Vtemp164[3U] = 0U;
-	vcdp->fullBus  (c+350,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+	__Vtemp104[0U] = 0U;
+	__Vtemp104[1U] = 0U;
+	__Vtemp104[2U] = 0U;
+	__Vtemp104[3U] = 0U;
+	__Vtemp105[0U] = 0U;
+	__Vtemp105[1U] = 0U;
+	__Vtemp105[2U] = 0U;
+	__Vtemp105[3U] = 0U;
+	vcdp->fullBus  (c+709,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 				 ? (0xffff0000U & (
-						   __Vtemp163[
+						   __Vtemp104[
 						   (3U 
 						    & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] 
 						   << 0x10U))
-				 : __Vtemp164[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])),32);
-	vcdp->fullBus  (c+351,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__use_write_data),32);
-	vcdp->fullBus  (c+352,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
+				 : __Vtemp105[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])),32);
+	vcdp->fullBus  (c+710,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__use_write_data),32);
+	vcdp->fullBus  (c+711,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				 ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 				     ? (0xffffff00U 
 					| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
@@ -2805,54 +4361,76 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 					     ? (0xffU 
 						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)
 					     : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
-	vcdp->fullBus  (c+353,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4);
-	vcdp->fullBus  (c+354,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
+	vcdp->fullBus  (c+712,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->fullBus  (c+713,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))
 				 ? 3U : 0xcU)),4);
-	vcdp->fullBus  (c+355,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16);
-	vcdp->fullArray(c+356,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128);
-	vcdp->fullBit  (c+360,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
-	vcdp->fullBus  (c+361,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
-	vcdp->fullBus  (c+362,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
-	vcdp->fullArray(c+363,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
-	vcdp->fullBus  (c+371,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
-	vcdp->fullBus  (c+372,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
-	vcdp->fullBus  (c+373,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
-	vcdp->fullBit  (c+374,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
-	vcdp->fullBus  (c+375,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
-	vcdp->fullBit  (c+376,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
-	__Vtemp165[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
-	__Vtemp165[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
-	__Vtemp165[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
-	__Vtemp165[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
-	vcdp->fullArray(c+377,(__Vtemp165),128);
-	vcdp->fullBit  (c+381,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
-	vcdp->fullBit  (c+382,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->fullBus  (c+714,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->fullArray(c+715,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->fullBit  (c+719,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
+	vcdp->fullBit  (c+720,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
+	vcdp->fullBit  (c+721,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
+	vcdp->fullBit  (c+722,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
+	vcdp->fullQuad (c+723,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->fullArray(c+725,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->fullBus  (c+733,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->fullBus  (c+734,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->fullBus  (c+735,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->fullBus  (c+736,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->fullArray(c+737,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->fullBus  (c+745,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->fullBit  (c+746,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->fullBus  (c+747,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->fullBus  (c+748,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->fullBus  (c+749,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->fullBus  (c+750,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->fullBit  (c+751,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->fullBus  (c+752,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->fullBit  (c+753,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp106[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp106[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp106[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp106[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->fullArray(c+754,(__Vtemp106),128);
+	vcdp->fullBit  (c+758,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+759,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->fullBit  (c+760,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				      | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->fullBit  (c+761,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				       ? 0U : (0U != 
 					       (0xffffU 
 						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
-	vcdp->fullBus  (c+383,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	vcdp->fullBus  (c+762,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 					   >> 0x10U))),16);
-	vcdp->fullBit  (c+384,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+	vcdp->fullBit  (c+763,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
 				      >> 1U))));
-	__Vtemp166[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
-	__Vtemp166[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
-	__Vtemp166[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
-	__Vtemp166[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
-	vcdp->fullArray(c+385,(__Vtemp166),128);
-	vcdp->fullBit  (c+389,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	__Vtemp107[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp107[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp107[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp107[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->fullArray(c+764,(__Vtemp107),128);
+	vcdp->fullBit  (c+768,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+769,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						  >> 0x10U)))));
-	vcdp->fullBit  (c+390,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->fullBit  (c+770,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						    >> 0x10U)))) 
+				      | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					 >> 1U)))));
+	vcdp->fullBit  (c+771,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				       ? 0U : (0U != 
 					       (0xffffU 
 						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						   >> 0x10U)))))));
-	__Vtemp167[0U] = 0U;
-	__Vtemp167[1U] = 0U;
-	__Vtemp167[2U] = 0U;
-	__Vtemp167[3U] = 0U;
-	vcdp->fullBus  (c+391,(__Vtemp167[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
+	__Vtemp108[0U] = 0U;
+	__Vtemp108[1U] = 0U;
+	__Vtemp108[2U] = 0U;
+	__Vtemp108[3U] = 0U;
+	vcdp->fullBus  (c+772,(__Vtemp108[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						 >> 2U))]),32);
-	vcdp->fullBus  (c+392,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
+	vcdp->fullBus  (c+773,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)
 				 ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				     ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 					 ? (0xffffff00U 
@@ -2875,96 +4453,95 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 						 : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))
 				 : 0U)),32);
-	vcdp->fullBit  (c+393,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) 
+	vcdp->fullBit  (c+774,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) 
 				 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
 				    == (0x1fffffU & 
 					(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
 					 >> 0xbU)))) 
 				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use))));
-	vcdp->fullBus  (c+394,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
-				<< 0xbU)),32);
-	vcdp->fullArray(c+395,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
-	vcdp->fullBus  (c+399,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21);
-	vcdp->fullBit  (c+400,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use));
-	vcdp->fullBit  (c+401,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access));
-	vcdp->fullBit  (c+402,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem));
-	vcdp->fullBit  (c+403,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
-				  != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
-						   >> 0xbU))) 
-				 & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)) 
-				& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in))));
-	vcdp->fullBit  (c+404,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+405,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+406,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+407,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
-	vcdp->fullBus  (c+408,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32);
-	vcdp->fullBus  (c+409,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->fullBit  (c+775,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				      >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->fullBus  (c+776,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use 
+				 << 0xbU) | (0x7c0U 
+					     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))),32);
+	vcdp->fullArray(c+777,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->fullBus  (c+781,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->fullBit  (c+782,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->fullBit  (c+783,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access));
+	vcdp->fullBit  (c+784,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->fullBit  (c+785,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__miss));
+	vcdp->fullBit  (c+786,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+787,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+788,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+789,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))));
+	vcdp->fullBus  (c+790,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->fullBus  (c+791,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 				 ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 				 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->fullBus  (c+410,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->fullBus  (c+792,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 				 ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 				 : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->fullBus  (c+411,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	vcdp->fullBus  (c+412,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	__Vtemp168[0U] = 0U;
-	__Vtemp168[1U] = 0U;
-	__Vtemp168[2U] = 0U;
-	__Vtemp168[3U] = 0U;
-	__Vtemp169[0U] = 0U;
-	__Vtemp169[1U] = 0U;
-	__Vtemp169[2U] = 0U;
-	__Vtemp169[3U] = 0U;
-	__Vtemp170[0U] = 0U;
-	__Vtemp170[1U] = 0U;
-	__Vtemp170[2U] = 0U;
-	__Vtemp170[3U] = 0U;
-	__Vtemp171[0U] = 0U;
-	__Vtemp171[1U] = 0U;
-	__Vtemp171[2U] = 0U;
-	__Vtemp171[3U] = 0U;
-	vcdp->fullBus  (c+413,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
-				 ? (0xff00U & (__Vtemp168[
+	vcdp->fullBus  (c+793,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+794,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	__Vtemp109[0U] = 0U;
+	__Vtemp109[1U] = 0U;
+	__Vtemp109[2U] = 0U;
+	__Vtemp109[3U] = 0U;
+	__Vtemp110[0U] = 0U;
+	__Vtemp110[1U] = 0U;
+	__Vtemp110[2U] = 0U;
+	__Vtemp110[3U] = 0U;
+	__Vtemp111[0U] = 0U;
+	__Vtemp111[1U] = 0U;
+	__Vtemp111[2U] = 0U;
+	__Vtemp111[3U] = 0U;
+	__Vtemp112[0U] = 0U;
+	__Vtemp112[1U] = 0U;
+	__Vtemp112[2U] = 0U;
+	__Vtemp112[3U] = 0U;
+	vcdp->fullBus  (c+795,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+				 ? (0xff00U & (__Vtemp109[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 2U))] 
 					       << 8U))
 				 : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 				     ? (0xff0000U & 
-					(__Vtemp169[
+					(__Vtemp110[
 					 (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 2U))] 
 					 << 0x10U))
 				     : ((3U == (3U 
 						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 					 ? (0xff000000U 
-					    & (__Vtemp170[
+					    & (__Vtemp111[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 2U))] 
 					       << 0x18U))
-					 : __Vtemp171[
+					 : __Vtemp112[
 					(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					       >> 2U))])))),32);
-	__Vtemp172[0U] = 0U;
-	__Vtemp172[1U] = 0U;
-	__Vtemp172[2U] = 0U;
-	__Vtemp172[3U] = 0U;
-	__Vtemp173[0U] = 0U;
-	__Vtemp173[1U] = 0U;
-	__Vtemp173[2U] = 0U;
-	__Vtemp173[3U] = 0U;
-	vcdp->fullBus  (c+414,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+	__Vtemp113[0U] = 0U;
+	__Vtemp113[1U] = 0U;
+	__Vtemp113[2U] = 0U;
+	__Vtemp113[3U] = 0U;
+	__Vtemp114[0U] = 0U;
+	__Vtemp114[1U] = 0U;
+	__Vtemp114[2U] = 0U;
+	__Vtemp114[3U] = 0U;
+	vcdp->fullBus  (c+796,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 				 ? (0xffff0000U & (
-						   __Vtemp172[
+						   __Vtemp113[
 						   (3U 
 						    & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						       >> 2U))] 
 						   << 0x10U))
-				 : __Vtemp173[(3U & 
+				 : __Vtemp114[(3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 2U))])),32);
-	vcdp->fullBus  (c+415,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__use_write_data),32);
-	vcdp->fullBus  (c+416,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
+	vcdp->fullBus  (c+797,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__use_write_data),32);
+	vcdp->fullBus  (c+798,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				 ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 				     ? (0xffffff00U 
 					| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
@@ -2982,54 +4559,76 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 					     ? (0xffU 
 						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)
 					     : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
-	vcdp->fullBus  (c+417,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4);
-	vcdp->fullBus  (c+418,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
+	vcdp->fullBus  (c+799,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->fullBus  (c+800,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))
 				 ? 3U : 0xcU)),4);
-	vcdp->fullBus  (c+419,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16);
-	vcdp->fullArray(c+420,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128);
-	vcdp->fullBit  (c+424,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
-	vcdp->fullBus  (c+425,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
-	vcdp->fullBus  (c+426,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
-	vcdp->fullArray(c+427,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
-	vcdp->fullBus  (c+435,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
-	vcdp->fullBus  (c+436,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
-	vcdp->fullBus  (c+437,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
-	vcdp->fullBit  (c+438,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
-	vcdp->fullBus  (c+439,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
-	vcdp->fullBit  (c+440,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
-	__Vtemp174[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
-	__Vtemp174[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
-	__Vtemp174[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
-	__Vtemp174[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
-	vcdp->fullArray(c+441,(__Vtemp174),128);
-	vcdp->fullBit  (c+445,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
-	vcdp->fullBit  (c+446,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->fullBus  (c+801,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->fullArray(c+802,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->fullBit  (c+806,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
+	vcdp->fullBit  (c+807,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
+	vcdp->fullBit  (c+808,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
+	vcdp->fullBit  (c+809,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
+	vcdp->fullQuad (c+810,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->fullArray(c+812,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->fullBus  (c+820,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->fullBus  (c+821,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->fullBus  (c+822,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->fullBus  (c+823,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->fullArray(c+824,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->fullBus  (c+832,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->fullBit  (c+833,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->fullBus  (c+834,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->fullBus  (c+835,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->fullBus  (c+836,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->fullBus  (c+837,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->fullBit  (c+838,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->fullBus  (c+839,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->fullBit  (c+840,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp115[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp115[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp115[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp115[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->fullArray(c+841,(__Vtemp115),128);
+	vcdp->fullBit  (c+845,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+846,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->fullBit  (c+847,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				      | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->fullBit  (c+848,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				       ? 0U : (0U != 
 					       (0xffffU 
 						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
-	vcdp->fullBus  (c+447,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	vcdp->fullBus  (c+849,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 					   >> 0x10U))),16);
-	vcdp->fullBit  (c+448,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+	vcdp->fullBit  (c+850,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
 				      >> 1U))));
-	__Vtemp175[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
-	__Vtemp175[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
-	__Vtemp175[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
-	__Vtemp175[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
-	vcdp->fullArray(c+449,(__Vtemp175),128);
-	vcdp->fullBit  (c+453,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	__Vtemp116[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp116[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp116[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp116[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->fullArray(c+851,(__Vtemp116),128);
+	vcdp->fullBit  (c+855,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+856,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						  >> 0x10U)))));
-	vcdp->fullBit  (c+454,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->fullBit  (c+857,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						    >> 0x10U)))) 
+				      | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					 >> 1U)))));
+	vcdp->fullBit  (c+858,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				       ? 0U : (0U != 
 					       (0xffffU 
 						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						   >> 0x10U)))))));
-	__Vtemp176[0U] = 0U;
-	__Vtemp176[1U] = 0U;
-	__Vtemp176[2U] = 0U;
-	__Vtemp176[3U] = 0U;
-	vcdp->fullBus  (c+455,(__Vtemp176[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
+	__Vtemp117[0U] = 0U;
+	__Vtemp117[1U] = 0U;
+	__Vtemp117[2U] = 0U;
+	__Vtemp117[3U] = 0U;
+	vcdp->fullBus  (c+859,(__Vtemp117[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						 >> 4U))]),32);
-	vcdp->fullBus  (c+456,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
+	vcdp->fullBus  (c+860,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)
 				 ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				     ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 					 ? (0xffffff00U 
@@ -3052,96 +4651,95 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 						 : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))
 				 : 0U)),32);
-	vcdp->fullBit  (c+457,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) 
+	vcdp->fullBit  (c+861,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) 
 				 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
 				    == (0x1fffffU & 
 					(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
 					 >> 0xbU)))) 
 				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use))));
-	vcdp->fullBus  (c+458,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
-				<< 0xbU)),32);
-	vcdp->fullArray(c+459,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
-	vcdp->fullBus  (c+463,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21);
-	vcdp->fullBit  (c+464,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use));
-	vcdp->fullBit  (c+465,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access));
-	vcdp->fullBit  (c+466,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem));
-	vcdp->fullBit  (c+467,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
-				  != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
-						   >> 0xbU))) 
-				 & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)) 
-				& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in))));
-	vcdp->fullBit  (c+468,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+469,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+470,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+471,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
-	vcdp->fullBus  (c+472,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32);
-	vcdp->fullBus  (c+473,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->fullBit  (c+862,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				      >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->fullBus  (c+863,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use 
+				 << 0xbU) | (0x7c0U 
+					     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))),32);
+	vcdp->fullArray(c+864,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->fullBus  (c+868,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->fullBit  (c+869,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->fullBit  (c+870,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access));
+	vcdp->fullBit  (c+871,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->fullBit  (c+872,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__miss));
+	vcdp->fullBit  (c+873,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+874,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+875,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+876,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))));
+	vcdp->fullBus  (c+877,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->fullBus  (c+878,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 				 ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 				 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->fullBus  (c+474,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->fullBus  (c+879,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 				 ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 				 : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->fullBus  (c+475,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	vcdp->fullBus  (c+476,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	__Vtemp177[0U] = 0U;
-	__Vtemp177[1U] = 0U;
-	__Vtemp177[2U] = 0U;
-	__Vtemp177[3U] = 0U;
-	__Vtemp178[0U] = 0U;
-	__Vtemp178[1U] = 0U;
-	__Vtemp178[2U] = 0U;
-	__Vtemp178[3U] = 0U;
-	__Vtemp179[0U] = 0U;
-	__Vtemp179[1U] = 0U;
-	__Vtemp179[2U] = 0U;
-	__Vtemp179[3U] = 0U;
-	__Vtemp180[0U] = 0U;
-	__Vtemp180[1U] = 0U;
-	__Vtemp180[2U] = 0U;
-	__Vtemp180[3U] = 0U;
-	vcdp->fullBus  (c+477,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
-				 ? (0xff00U & (__Vtemp177[
+	vcdp->fullBus  (c+880,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+881,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	__Vtemp118[0U] = 0U;
+	__Vtemp118[1U] = 0U;
+	__Vtemp118[2U] = 0U;
+	__Vtemp118[3U] = 0U;
+	__Vtemp119[0U] = 0U;
+	__Vtemp119[1U] = 0U;
+	__Vtemp119[2U] = 0U;
+	__Vtemp119[3U] = 0U;
+	__Vtemp120[0U] = 0U;
+	__Vtemp120[1U] = 0U;
+	__Vtemp120[2U] = 0U;
+	__Vtemp120[3U] = 0U;
+	__Vtemp121[0U] = 0U;
+	__Vtemp121[1U] = 0U;
+	__Vtemp121[2U] = 0U;
+	__Vtemp121[3U] = 0U;
+	vcdp->fullBus  (c+882,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+				 ? (0xff00U & (__Vtemp118[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 4U))] 
 					       << 8U))
 				 : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 				     ? (0xff0000U & 
-					(__Vtemp178[
+					(__Vtemp119[
 					 (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 4U))] 
 					 << 0x10U))
 				     : ((3U == (3U 
 						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 					 ? (0xff000000U 
-					    & (__Vtemp179[
+					    & (__Vtemp120[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 4U))] 
 					       << 0x18U))
-					 : __Vtemp180[
+					 : __Vtemp121[
 					(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					       >> 4U))])))),32);
-	__Vtemp181[0U] = 0U;
-	__Vtemp181[1U] = 0U;
-	__Vtemp181[2U] = 0U;
-	__Vtemp181[3U] = 0U;
-	__Vtemp182[0U] = 0U;
-	__Vtemp182[1U] = 0U;
-	__Vtemp182[2U] = 0U;
-	__Vtemp182[3U] = 0U;
-	vcdp->fullBus  (c+478,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+	__Vtemp122[0U] = 0U;
+	__Vtemp122[1U] = 0U;
+	__Vtemp122[2U] = 0U;
+	__Vtemp122[3U] = 0U;
+	__Vtemp123[0U] = 0U;
+	__Vtemp123[1U] = 0U;
+	__Vtemp123[2U] = 0U;
+	__Vtemp123[3U] = 0U;
+	vcdp->fullBus  (c+883,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 				 ? (0xffff0000U & (
-						   __Vtemp181[
+						   __Vtemp122[
 						   (3U 
 						    & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						       >> 4U))] 
 						   << 0x10U))
-				 : __Vtemp182[(3U & 
+				 : __Vtemp123[(3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 4U))])),32);
-	vcdp->fullBus  (c+479,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__use_write_data),32);
-	vcdp->fullBus  (c+480,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
+	vcdp->fullBus  (c+884,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__use_write_data),32);
+	vcdp->fullBus  (c+885,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				 ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 				     ? (0xffffff00U 
 					| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
@@ -3159,54 +4757,76 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 					     ? (0xffU 
 						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)
 					     : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
-	vcdp->fullBus  (c+481,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4);
-	vcdp->fullBus  (c+482,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
+	vcdp->fullBus  (c+886,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->fullBus  (c+887,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))
 				 ? 3U : 0xcU)),4);
-	vcdp->fullBus  (c+483,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16);
-	vcdp->fullArray(c+484,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128);
-	vcdp->fullBit  (c+488,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
-	vcdp->fullBus  (c+489,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
-	vcdp->fullBus  (c+490,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
-	vcdp->fullArray(c+491,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
-	vcdp->fullBus  (c+499,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
-	vcdp->fullBus  (c+500,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
-	vcdp->fullBus  (c+501,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
-	vcdp->fullBit  (c+502,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
-	vcdp->fullBus  (c+503,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
-	vcdp->fullBit  (c+504,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
-	__Vtemp183[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
-	__Vtemp183[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
-	__Vtemp183[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
-	__Vtemp183[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
-	vcdp->fullArray(c+505,(__Vtemp183),128);
-	vcdp->fullBit  (c+509,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
-	vcdp->fullBit  (c+510,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->fullBus  (c+888,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->fullArray(c+889,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->fullBit  (c+893,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
+	vcdp->fullBit  (c+894,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
+	vcdp->fullBit  (c+895,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
+	vcdp->fullBit  (c+896,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
+	vcdp->fullQuad (c+897,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->fullArray(c+899,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->fullBus  (c+907,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->fullBus  (c+908,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->fullBus  (c+909,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->fullBus  (c+910,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->fullArray(c+911,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->fullBus  (c+919,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->fullBit  (c+920,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->fullBus  (c+921,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->fullBus  (c+922,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->fullBus  (c+923,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->fullBus  (c+924,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->fullBit  (c+925,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->fullBus  (c+926,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->fullBit  (c+927,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp124[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp124[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp124[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp124[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->fullArray(c+928,(__Vtemp124),128);
+	vcdp->fullBit  (c+932,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+933,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->fullBit  (c+934,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				      | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->fullBit  (c+935,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				       ? 0U : (0U != 
 					       (0xffffU 
 						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
-	vcdp->fullBus  (c+511,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	vcdp->fullBus  (c+936,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 					   >> 0x10U))),16);
-	vcdp->fullBit  (c+512,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+	vcdp->fullBit  (c+937,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
 				      >> 1U))));
-	__Vtemp184[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
-	__Vtemp184[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
-	__Vtemp184[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
-	__Vtemp184[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
-	vcdp->fullArray(c+513,(__Vtemp184),128);
-	vcdp->fullBit  (c+517,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+	__Vtemp125[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp125[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp125[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp125[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->fullArray(c+938,(__Vtemp125),128);
+	vcdp->fullBit  (c+942,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+943,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						  >> 0x10U)))));
-	vcdp->fullBit  (c+518,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+	vcdp->fullBit  (c+944,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+				       & (0U != (0xffffU 
+						 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						    >> 0x10U)))) 
+				      | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					 >> 1U)))));
+	vcdp->fullBit  (c+945,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
 				       ? 0U : (0U != 
 					       (0xffffU 
 						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
 						   >> 0x10U)))))));
-	__Vtemp185[0U] = 0U;
-	__Vtemp185[1U] = 0U;
-	__Vtemp185[2U] = 0U;
-	__Vtemp185[3U] = 0U;
-	vcdp->fullBus  (c+519,(__Vtemp185[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
+	__Vtemp126[0U] = 0U;
+	__Vtemp126[1U] = 0U;
+	__Vtemp126[2U] = 0U;
+	__Vtemp126[3U] = 0U;
+	vcdp->fullBus  (c+946,(__Vtemp126[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						 >> 6U))]),32);
-	vcdp->fullBus  (c+520,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
+	vcdp->fullBus  (c+947,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)
 				 ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				     ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 					 ? (0xffffff00U 
@@ -3229,96 +4849,95 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 						 : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))
 				 : 0U)),32);
-	vcdp->fullBit  (c+521,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) 
+	vcdp->fullBit  (c+948,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) 
 				 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
 				    == (0x1fffffU & 
 					(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
 					 >> 0xbU)))) 
 				& (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use))));
-	vcdp->fullBus  (c+522,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
-				<< 0xbU)),32);
-	vcdp->fullArray(c+523,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
-	vcdp->fullBus  (c+527,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21);
-	vcdp->fullBit  (c+528,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use));
-	vcdp->fullBit  (c+529,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access));
-	vcdp->fullBit  (c+530,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem));
-	vcdp->fullBit  (c+531,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
-				  != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
-						   >> 0xbU))) 
-				 & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)) 
-				& (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in))));
-	vcdp->fullBit  (c+532,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+533,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+534,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
-	vcdp->fullBit  (c+535,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
-	vcdp->fullBus  (c+536,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32);
-	vcdp->fullBus  (c+537,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->fullBit  (c+949,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) 
+				      >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))));
+	vcdp->fullBus  (c+950,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use 
+				 << 0xbU) | (0x7c0U 
+					     & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))),32);
+	vcdp->fullArray(c+951,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128);
+	vcdp->fullBus  (c+955,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21);
+	vcdp->fullBit  (c+956,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use));
+	vcdp->fullBit  (c+957,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access));
+	vcdp->fullBit  (c+958,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem));
+	vcdp->fullBit  (c+959,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__miss));
+	vcdp->fullBit  (c+960,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+961,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+962,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->fullBit  (c+963,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))));
+	vcdp->fullBus  (c+964,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32);
+	vcdp->fullBus  (c+965,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 				 ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 				 : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->fullBus  (c+538,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
+	vcdp->fullBus  (c+966,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 				 ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 				 : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32);
-	vcdp->fullBus  (c+539,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	vcdp->fullBus  (c+540,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
-	__Vtemp186[0U] = 0U;
-	__Vtemp186[1U] = 0U;
-	__Vtemp186[2U] = 0U;
-	__Vtemp186[3U] = 0U;
-	__Vtemp187[0U] = 0U;
-	__Vtemp187[1U] = 0U;
-	__Vtemp187[2U] = 0U;
-	__Vtemp187[3U] = 0U;
-	__Vtemp188[0U] = 0U;
-	__Vtemp188[1U] = 0U;
-	__Vtemp188[2U] = 0U;
-	__Vtemp188[3U] = 0U;
-	__Vtemp189[0U] = 0U;
-	__Vtemp189[1U] = 0U;
-	__Vtemp189[2U] = 0U;
-	__Vtemp189[3U] = 0U;
-	vcdp->fullBus  (c+541,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
-				 ? (0xff00U & (__Vtemp186[
+	vcdp->fullBus  (c+967,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	vcdp->fullBus  (c+968,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32);
+	__Vtemp127[0U] = 0U;
+	__Vtemp127[1U] = 0U;
+	__Vtemp127[2U] = 0U;
+	__Vtemp127[3U] = 0U;
+	__Vtemp128[0U] = 0U;
+	__Vtemp128[1U] = 0U;
+	__Vtemp128[2U] = 0U;
+	__Vtemp128[3U] = 0U;
+	__Vtemp129[0U] = 0U;
+	__Vtemp129[1U] = 0U;
+	__Vtemp129[2U] = 0U;
+	__Vtemp129[3U] = 0U;
+	__Vtemp130[0U] = 0U;
+	__Vtemp130[1U] = 0U;
+	__Vtemp130[2U] = 0U;
+	__Vtemp130[3U] = 0U;
+	vcdp->fullBus  (c+969,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+				 ? (0xff00U & (__Vtemp127[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 6U))] 
 					       << 8U))
 				 : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 				     ? (0xff0000U & 
-					(__Vtemp187[
+					(__Vtemp128[
 					 (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 6U))] 
 					 << 0x10U))
 				     : ((3U == (3U 
 						& vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 					 ? (0xff000000U 
-					    & (__Vtemp188[
+					    & (__Vtemp129[
 					       (3U 
 						& ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						   >> 6U))] 
 					       << 0x18U))
-					 : __Vtemp189[
+					 : __Vtemp130[
 					(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 					       >> 6U))])))),32);
-	__Vtemp190[0U] = 0U;
-	__Vtemp190[1U] = 0U;
-	__Vtemp190[2U] = 0U;
-	__Vtemp190[3U] = 0U;
-	__Vtemp191[0U] = 0U;
-	__Vtemp191[1U] = 0U;
-	__Vtemp191[2U] = 0U;
-	__Vtemp191[3U] = 0U;
-	vcdp->fullBus  (c+542,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+	__Vtemp131[0U] = 0U;
+	__Vtemp131[1U] = 0U;
+	__Vtemp131[2U] = 0U;
+	__Vtemp131[3U] = 0U;
+	__Vtemp132[0U] = 0U;
+	__Vtemp132[1U] = 0U;
+	__Vtemp132[2U] = 0U;
+	__Vtemp132[3U] = 0U;
+	vcdp->fullBus  (c+970,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 				 ? (0xffff0000U & (
-						   __Vtemp190[
+						   __Vtemp131[
 						   (3U 
 						    & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						       >> 6U))] 
 						   << 0x10U))
-				 : __Vtemp191[(3U & 
+				 : __Vtemp132[(3U & 
 					       ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) 
 						>> 6U))])),32);
-	vcdp->fullBus  (c+543,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__use_write_data),32);
-	vcdp->fullBus  (c+544,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
+	vcdp->fullBus  (c+971,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__use_write_data),32);
+	vcdp->fullBus  (c+972,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))
 				 ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 				     ? (0xffffff00U 
 					| vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
@@ -3336,4430 +4955,6763 @@ void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, Verila
 					     ? (0xffU 
 						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)
 					     : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))),32);
-	vcdp->fullBus  (c+545,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4);
-	vcdp->fullBus  (c+546,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
+	vcdp->fullBus  (c+973,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4);
+	vcdp->fullBus  (c+974,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))
 				 ? 3U : 0xcU)),4);
-	vcdp->fullBus  (c+547,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16);
-	vcdp->fullArray(c+548,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128);
-	vcdp->fullBit  (c+552,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
-	vcdp->fullBus  (c+553,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
-	vcdp->fullBus  (c+554,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
-	vcdp->fullArray(c+555,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
-	vcdp->fullBus  (c+563,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
-	vcdp->fullBus  (c+564,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
-	vcdp->fullBus  (c+565,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
-	vcdp->fullBit  (c+566,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
-	vcdp->fullBus  (c+567,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
-	vcdp->fullBit  (c+568,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
-	__Vtemp192[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
-	__Vtemp192[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
-	__Vtemp192[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
-	__Vtemp192[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
-	vcdp->fullArray(c+569,(__Vtemp192),128);
-	vcdp->fullBit  (c+573,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
-	vcdp->fullBit  (c+574,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
-				       ? 0U : (0U != 
-					       (0xffffU 
-						& vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
-	vcdp->fullBus  (c+575,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
-					   >> 0x10U))),16);
-	vcdp->fullBit  (c+576,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
-				      >> 1U))));
-	__Vtemp193[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
-	__Vtemp193[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
-	__Vtemp193[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
-	__Vtemp193[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
-	vcdp->fullArray(c+577,(__Vtemp193),128);
-	vcdp->fullBit  (c+581,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
-						  >> 0x10U)))));
-	vcdp->fullBit  (c+582,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
-				       ? 0U : (0U != 
-					       (0xffffU 
-						& (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
-						   >> 0x10U)))))));
-	vcdp->fullBit  (c+583,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
-				| (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))));
-	vcdp->fullBus  (c+584,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)
-				 ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read
-				 : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read)),32);
-	vcdp->fullBit  (c+585,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) 
-				| (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)))));
-	vcdp->fullBit  (c+586,((1U & ((~ ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
-					  | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))) 
-				      & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)))));
-	vcdp->fullBus  (c+587,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
-				 ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) 
-				    & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))
-				 : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) 
-				    & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))))),4);
-	__Vtemp196[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
+	vcdp->fullBus  (c+975,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16);
+	vcdp->fullArray(c+976,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128);
+	vcdp->fullBit  (c+980,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write));
+	vcdp->fullBit  (c+981,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write));
+	vcdp->fullBit  (c+982,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write));
+	vcdp->fullBit  (c+983,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write));
+	vcdp->fullQuad (c+984,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
+	vcdp->fullArray(c+986,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
+	vcdp->fullBus  (c+994,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
+	vcdp->fullBus  (c+995,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
+	vcdp->fullBus  (c+996,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2);
+	vcdp->fullBus  (c+997,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32);
+	vcdp->fullArray(c+998,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256);
+	vcdp->fullBus  (c+1006,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2);
+	vcdp->fullBit  (c+1007,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
+	vcdp->fullBus  (c+1008,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1);
+	vcdp->fullBus  (c+1009,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
+	vcdp->fullBus  (c+1010,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1);
+	vcdp->fullBus  (c+1011,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
+	vcdp->fullBit  (c+1012,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found));
+	vcdp->fullBus  (c+1013,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16);
+	vcdp->fullBit  (c+1014,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))));
+	__Vtemp133[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U];
+	__Vtemp133[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U];
+	__Vtemp133[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U];
+	__Vtemp133[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U];
+	vcdp->fullArray(c+1015,(__Vtemp133),128);
+	vcdp->fullBit  (c+1019,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+1020,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))));
+	vcdp->fullBit  (c+1021,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use)) 
+					& (0U != (0xffffU 
+						  & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) 
+				       | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))));
+	vcdp->fullBit  (c+1022,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				        ? 0U : (0U 
+						!= 
+						(0xffffU 
+						 & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))))));
+	vcdp->fullBus  (c+1023,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+					    >> 0x10U))),16);
+	vcdp->fullBit  (c+1024,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+				       >> 1U))));
+	__Vtemp134[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U];
+	__Vtemp134[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U];
+	__Vtemp134[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U];
+	__Vtemp134[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U];
+	vcdp->fullArray(c+1025,(__Vtemp134),128);
+	vcdp->fullBit  (c+1029,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use));
+	vcdp->fullBit  (c+1030,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						   >> 0x10U)))));
+	vcdp->fullBit  (c+1031,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use)) 
+					& (0U != (0xffffU 
+						  & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						     >> 0x10U)))) 
+				       | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) 
+					  >> 1U)))));
+	vcdp->fullBit  (c+1032,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))
+				        ? 0U : (0U 
+						!= 
+						(0xffffU 
+						 & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way 
+						    >> 0x10U)))))));
+	vcdp->fullBit  (c+1033,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
+				 | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))));
+	vcdp->fullBus  (c+1034,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual)
+				  ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read
+				  : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read)),32);
+	vcdp->fullBit  (c+1035,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) 
+				 | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)))));
+	vcdp->fullBit  (c+1036,((1U & ((~ ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
+					   | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))) 
+				       & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)))));
+	vcdp->fullBus  (c+1037,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))
+				  ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) 
+				     & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))
+				  : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) 
+				     & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))))),4);
+	__Vtemp137[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]);
-	__Vtemp196[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
+	__Vtemp137[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]);
-	__Vtemp196[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
+	__Vtemp137[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]);
-	__Vtemp196[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
+	__Vtemp137[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]);
-	vcdp->fullArray(c+588,(__Vtemp196),128);
-	__Vtemp199[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
+	vcdp->fullArray(c+1038,(__Vtemp137),128);
+	__Vtemp140[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 7U))][0U]);
-	__Vtemp199[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
+	__Vtemp140[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 7U))][1U]);
-	__Vtemp199[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
+	__Vtemp140[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 7U))][2U]);
-	__Vtemp199[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
+	__Vtemp140[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 7U))][3U]);
-	vcdp->fullArray(c+592,(__Vtemp199),128);
-	__Vtemp202[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
+	vcdp->fullArray(c+1042,(__Vtemp140),128);
+	__Vtemp143[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 0xeU))][0U]);
-	__Vtemp202[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
+	__Vtemp143[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 0xeU))][1U]);
-	__Vtemp202[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
+	__Vtemp143[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 0xeU))][2U]);
-	__Vtemp202[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
+	__Vtemp143[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 0xeU))][3U]);
-	vcdp->fullArray(c+596,(__Vtemp202),128);
-	__Vtemp205[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
+	vcdp->fullArray(c+1046,(__Vtemp143),128);
+	__Vtemp146[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 0x15U))][0U]);
-	__Vtemp205[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
+	__Vtemp146[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 0x15U))][1U]);
-	__Vtemp205[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
+	__Vtemp146[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 0x15U))][2U]);
-	__Vtemp205[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
+	__Vtemp146[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)
 			   ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory
 			  [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr 
 				     >> 0x15U))][3U]);
-	vcdp->fullArray(c+600,(__Vtemp205),128);
-	vcdp->fullBit  (c+604,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
-				& (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)))));
-	vcdp->fullBit  (c+605,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
-				& (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state)))));
-	__Vtemp206[0U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					    << 7U)))
-			    ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[
-				    ((IData)(1U) + 
-				     (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					    << 2U)))] 
-				    << ((IData)(0x20U) 
-					- (0x1fU & 
-					   ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) 
-					    << 7U))))) 
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-	vcdp->fullBus  (c+675,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
-	vcdp->fullBus  (c+676,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__way_to_update),1);
-	vcdp->fullQuad (c+677,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
-	vcdp->fullArray(c+679,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
-	vcdp->fullBus  (c+687,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
-	vcdp->fullBus  (c+688,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
-	vcdp->fullBit  (c+689,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
-	vcdp->fullBus  (c+690,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
-	vcdp->fullBus  (c+691,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
-	vcdp->fullBus  (c+692,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__way_to_update),1);
-	vcdp->fullQuad (c+693,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42);
-	vcdp->fullArray(c+695,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256);
-	vcdp->fullBus  (c+703,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2);
-	vcdp->fullBus  (c+704,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2);
-	vcdp->fullBit  (c+705,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found));
-	vcdp->fullBus  (c+706,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1);
-	vcdp->fullBus  (c+707,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2);
-	vcdp->fullBit  (c+708,(vlTOPp->cache_simX__DOT__icache_i_m_ready));
-	vcdp->fullBit  (c+709,(vlTOPp->cache_simX__DOT__dcache_i_m_ready));
-	vcdp->fullBus  (c+710,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests),4);
-	vcdp->fullBit  (c+711,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))));
-	vcdp->fullBus  (c+712,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
-	vcdp->fullBus  (c+713,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
-	vcdp->fullBus  (c+714,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
-	vcdp->fullBus  (c+715,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
-	vcdp->fullBus  (c+716,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr)),32);
-	vcdp->fullBit  (c+717,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))));
-	vcdp->fullArray(c+718,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read),128);
-	vcdp->fullBus  (c+722,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict),1);
-	vcdp->fullBus  (c+723,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state),4);
-	vcdp->fullBus  (c+724,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid),4);
-	vcdp->fullBus  (c+725,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr),32);
-	vcdp->fullBus  (c+726,((0xfffffff0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr)),32);
-	vcdp->fullBit  (c+727,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))));
-	vcdp->fullBus  (c+728,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read),32);
-	vcdp->fullBus  (c+729,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict),1);
-	vcdp->fullBus  (c+730,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state),4);
-	vcdp->fullBus  (c+731,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid),1);
-	vcdp->fullBus  (c+732,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr),32);
-	vcdp->fullBus  (c+733,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
-			       [0U]),23);
-	__Vtemp207[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	vcdp->fullArray(c+1050,(__Vtemp146),128);
+	vcdp->fullBit  (c+1054,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
+				 & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)))));
+	vcdp->fullBit  (c+1055,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) 
+				 & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state)))));
+	vcdp->fullBit  (c+1056,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+				 & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb)))));
+	vcdp->fullBit  (c+1057,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) 
+				 & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state)))));
+	vcdp->fullBit  (c+1058,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) 
+				 | ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) 
+				    | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))))));
+	vcdp->fullBus  (c+1059,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp147[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp147[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp147[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp147[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1060,(__Vtemp147),128);
+	vcdp->fullBit  (c+1064,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1065,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp148[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp148[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp148[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp148[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1066,(__Vtemp148),128);
+	vcdp->fullBit  (c+1070,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1071,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp149[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp149[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp149[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp149[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1072,(__Vtemp149),128);
+	vcdp->fullBit  (c+1076,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1077,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp150[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp150[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp150[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp150[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1078,(__Vtemp150),128);
+	vcdp->fullBit  (c+1082,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1083,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp151[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp151[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp151[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp151[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1084,(__Vtemp151),128);
+	vcdp->fullBit  (c+1088,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1089,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp152[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp152[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp152[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp152[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1090,(__Vtemp152),128);
+	vcdp->fullBit  (c+1094,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1095,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp153[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp153[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp153[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp153[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1096,(__Vtemp153),128);
+	vcdp->fullBit  (c+1100,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1101,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp154[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp154[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp154[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp154[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1102,(__Vtemp154),128);
+	vcdp->fullBit  (c+1106,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1107,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp155[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp155[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp155[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp155[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1108,(__Vtemp155),128);
+	vcdp->fullBit  (c+1112,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1113,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp156[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp156[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp156[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp156[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1114,(__Vtemp156),128);
+	vcdp->fullBit  (c+1118,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1119,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp157[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp157[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp157[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp157[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1120,(__Vtemp157),128);
+	vcdp->fullBit  (c+1124,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1125,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp158[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp158[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp158[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp158[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1126,(__Vtemp158),128);
+	vcdp->fullBit  (c+1130,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1131,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp159[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp159[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp159[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp159[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1132,(__Vtemp159),128);
+	vcdp->fullBit  (c+1136,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1137,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp160[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp160[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp160[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp160[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1138,(__Vtemp160),128);
+	vcdp->fullBit  (c+1142,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1143,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp161[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp161[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp161[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp161[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1144,(__Vtemp161),128);
+	vcdp->fullBit  (c+1148,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1149,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					   >> 6U))]),21);
+	__Vtemp162[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][0U];
+	__Vtemp162[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][1U];
+	__Vtemp162[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][2U];
+	__Vtemp162[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+		       >> 6U))][3U];
+	vcdp->fullArray(c+1150,(__Vtemp162),128);
+	vcdp->fullBit  (c+1154,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid
+				[(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr 
+					   >> 6U))]));
+	vcdp->fullBus  (c+1155,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->fullBus  (c+1156,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->fullBus  (c+1157,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->fullBus  (c+1158,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->fullBus  (c+1159,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->fullBus  (c+1160,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->fullBus  (c+1161,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->fullBus  (c+1162,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__way_to_update),1);
+	vcdp->fullBit  (c+1163,(vlTOPp->cache_simX__DOT__icache_i_m_ready));
+	vcdp->fullBit  (c+1164,(vlTOPp->cache_simX__DOT__dcache_i_m_ready));
+	vcdp->fullBus  (c+1165,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests),4);
+	vcdp->fullBit  (c+1166,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests))));
+	vcdp->fullBus  (c+1167,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
+	vcdp->fullBus  (c+1168,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
+	vcdp->fullBus  (c+1169,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
+	vcdp->fullBus  (c+1170,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32);
+	vcdp->fullBus  (c+1171,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr)),32);
+	vcdp->fullBit  (c+1172,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))));
+	vcdp->fullArray(c+1173,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read),128);
+	vcdp->fullBus  (c+1177,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict),1);
+	vcdp->fullBus  (c+1178,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state),4);
+	vcdp->fullBus  (c+1179,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid),4);
+	vcdp->fullBus  (c+1180,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr),32);
+	vcdp->fullBus  (c+1181,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr)),32);
+	vcdp->fullBit  (c+1182,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))));
+	vcdp->fullBus  (c+1183,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read),32);
+	vcdp->fullBus  (c+1184,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict),1);
+	vcdp->fullBus  (c+1185,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state),4);
+	vcdp->fullBus  (c+1186,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid),1);
+	vcdp->fullBus  (c+1187,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr),32);
+	__Vtemp163[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [0U][0U];
-	__Vtemp207[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	__Vtemp163[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [0U][1U];
-	__Vtemp207[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	__Vtemp163[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [0U][2U];
-	__Vtemp207[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	__Vtemp163[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [0U][3U];
-	vcdp->fullArray(c+734,(__Vtemp207),128);
-	vcdp->fullBit  (c+738,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid
-			       [0U]));
-	vcdp->fullBit  (c+739,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty
-			       [0U]));
-	__Vtemp208[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	    [0U][0U];
-	__Vtemp208[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	    [0U][1U];
-	__Vtemp208[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	    [0U][2U];
-	__Vtemp208[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
-	    [0U][3U];
-	vcdp->fullArray(c+740,(__Vtemp208),128);
-	__Vtemp209[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	vcdp->fullArray(c+1188,(__Vtemp163),128);
+	__Vtemp164[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [1U][0U];
-	__Vtemp209[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	__Vtemp164[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [1U][1U];
-	__Vtemp209[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	__Vtemp164[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [1U][2U];
-	__Vtemp209[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	__Vtemp164[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [1U][3U];
-	vcdp->fullArray(c+744,(__Vtemp209),128);
-	__Vtemp210[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	vcdp->fullArray(c+1192,(__Vtemp164),128);
+	__Vtemp165[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
 	    [2U][0U];
-	__Vtemp210[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
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+	    [2U][3U];
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+	    [5U][3U];
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+	    [6U][1U];
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+	    [6U][2U];
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+	    [6U][3U];
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+	    [7U][1U];
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+	__Vtemp521[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [6U][2U];
+	__Vtemp521[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [6U][3U];
+	vcdp->fullArray(c+3698,(__Vtemp521),128);
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+	    [7U][0U];
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+	    [7U][1U];
+	__Vtemp522[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [7U][2U];
+	__Vtemp522[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [7U][3U];
+	vcdp->fullArray(c+3702,(__Vtemp522),128);
+	__Vtemp523[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [8U][0U];
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+	    [8U][1U];
+	__Vtemp523[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [8U][2U];
+	__Vtemp523[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [8U][3U];
+	vcdp->fullArray(c+3706,(__Vtemp523),128);
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+	    [9U][0U];
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+	    [9U][1U];
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+	    [9U][2U];
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+	    [9U][3U];
+	vcdp->fullArray(c+3710,(__Vtemp524),128);
+	__Vtemp525[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xaU][0U];
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+	    [0xaU][1U];
+	__Vtemp525[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xaU][2U];
+	__Vtemp525[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xaU][3U];
+	vcdp->fullArray(c+3714,(__Vtemp525),128);
+	__Vtemp526[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xbU][0U];
+	__Vtemp526[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xbU][1U];
+	__Vtemp526[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xbU][2U];
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+	    [0xbU][3U];
+	vcdp->fullArray(c+3718,(__Vtemp526),128);
+	__Vtemp527[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xcU][0U];
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+	    [0xcU][1U];
+	__Vtemp527[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xcU][2U];
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+	    [0xcU][3U];
+	vcdp->fullArray(c+3722,(__Vtemp527),128);
+	__Vtemp528[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xdU][0U];
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+	    [0xdU][1U];
+	__Vtemp528[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xdU][2U];
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+	    [0xdU][3U];
+	vcdp->fullArray(c+3726,(__Vtemp528),128);
+	__Vtemp529[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xeU][0U];
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+	    [0xeU][1U];
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+	    [0xeU][2U];
+	__Vtemp529[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xeU][3U];
+	vcdp->fullArray(c+3730,(__Vtemp529),128);
+	__Vtemp530[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xfU][0U];
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+	    [0xfU][1U];
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+	    [0xfU][2U];
+	__Vtemp530[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0xfU][3U];
+	vcdp->fullArray(c+3734,(__Vtemp530),128);
+	__Vtemp531[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
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+	    [0x10U][1U];
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+	    [0x10U][2U];
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+	    [0x10U][3U];
+	vcdp->fullArray(c+3738,(__Vtemp531),128);
+	__Vtemp532[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x11U][0U];
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+	    [0x11U][1U];
+	__Vtemp532[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x11U][2U];
+	__Vtemp532[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x11U][3U];
+	vcdp->fullArray(c+3742,(__Vtemp532),128);
+	__Vtemp533[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x12U][0U];
+	__Vtemp533[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x12U][1U];
+	__Vtemp533[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x12U][2U];
+	__Vtemp533[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x12U][3U];
+	vcdp->fullArray(c+3746,(__Vtemp533),128);
+	__Vtemp534[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x13U][0U];
+	__Vtemp534[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x13U][1U];
+	__Vtemp534[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x13U][2U];
+	__Vtemp534[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x13U][3U];
+	vcdp->fullArray(c+3750,(__Vtemp534),128);
+	__Vtemp535[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x14U][0U];
+	__Vtemp535[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x14U][1U];
+	__Vtemp535[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x14U][2U];
+	__Vtemp535[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x14U][3U];
+	vcdp->fullArray(c+3754,(__Vtemp535),128);
+	__Vtemp536[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x15U][0U];
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+	    [0x15U][1U];
+	__Vtemp536[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x15U][2U];
+	__Vtemp536[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x15U][3U];
+	vcdp->fullArray(c+3758,(__Vtemp536),128);
+	__Vtemp537[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x16U][0U];
+	__Vtemp537[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x16U][1U];
+	__Vtemp537[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x16U][2U];
+	__Vtemp537[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x16U][3U];
+	vcdp->fullArray(c+3762,(__Vtemp537),128);
+	__Vtemp538[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x17U][0U];
+	__Vtemp538[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x17U][1U];
+	__Vtemp538[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
+	    [0x17U][2U];
+	__Vtemp538[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data
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+	vcdp->fullArray(c+3766,(__Vtemp538),128);
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+	    [5U][0U];
+	__Vtemp552[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [5U][1U];
+	__Vtemp552[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [5U][2U];
+	__Vtemp552[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [5U][3U];
+	vcdp->fullArray(c+3920,(__Vtemp552),128);
+	__Vtemp553[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [6U][0U];
+	__Vtemp553[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [6U][1U];
+	__Vtemp553[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [6U][2U];
+	__Vtemp553[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [6U][3U];
+	vcdp->fullArray(c+3924,(__Vtemp553),128);
+	__Vtemp554[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [7U][0U];
+	__Vtemp554[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [7U][1U];
+	__Vtemp554[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [7U][2U];
+	__Vtemp554[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [7U][3U];
+	vcdp->fullArray(c+3928,(__Vtemp554),128);
+	__Vtemp555[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [8U][0U];
+	__Vtemp555[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [8U][1U];
+	__Vtemp555[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [8U][2U];
+	__Vtemp555[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [8U][3U];
+	vcdp->fullArray(c+3932,(__Vtemp555),128);
+	__Vtemp556[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [9U][0U];
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+	    [9U][1U];
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+	    [9U][2U];
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+	    [9U][3U];
+	vcdp->fullArray(c+3936,(__Vtemp556),128);
+	__Vtemp557[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xaU][0U];
+	__Vtemp557[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xaU][1U];
+	__Vtemp557[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xaU][2U];
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+	    [0xaU][3U];
+	vcdp->fullArray(c+3940,(__Vtemp557),128);
+	__Vtemp558[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xbU][0U];
+	__Vtemp558[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xbU][1U];
+	__Vtemp558[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xbU][2U];
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+	    [0xbU][3U];
+	vcdp->fullArray(c+3944,(__Vtemp558),128);
+	__Vtemp559[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xcU][0U];
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+	    [0xcU][1U];
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+	    [0xcU][2U];
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+	    [0xcU][3U];
+	vcdp->fullArray(c+3948,(__Vtemp559),128);
+	__Vtemp560[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xdU][0U];
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+	    [0xdU][1U];
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+	    [0xdU][2U];
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+	    [0xdU][3U];
+	vcdp->fullArray(c+3952,(__Vtemp560),128);
+	__Vtemp561[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xeU][0U];
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+	    [0xeU][1U];
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+	    [0xeU][2U];
+	__Vtemp561[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xeU][3U];
+	vcdp->fullArray(c+3956,(__Vtemp561),128);
+	__Vtemp562[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xfU][0U];
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+	    [0xfU][1U];
+	__Vtemp562[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xfU][2U];
+	__Vtemp562[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0xfU][3U];
+	vcdp->fullArray(c+3960,(__Vtemp562),128);
+	__Vtemp563[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x10U][0U];
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+	    [0x10U][1U];
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+	    [0x10U][2U];
+	__Vtemp563[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x10U][3U];
+	vcdp->fullArray(c+3964,(__Vtemp563),128);
+	__Vtemp564[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x11U][0U];
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+	    [0x11U][1U];
+	__Vtemp564[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x11U][2U];
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+	    [0x11U][3U];
+	vcdp->fullArray(c+3968,(__Vtemp564),128);
+	__Vtemp565[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x12U][0U];
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+	    [0x12U][1U];
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+	    [0x12U][2U];
+	__Vtemp565[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x12U][3U];
+	vcdp->fullArray(c+3972,(__Vtemp565),128);
+	__Vtemp566[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x13U][0U];
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+	    [0x13U][1U];
+	__Vtemp566[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x13U][2U];
+	__Vtemp566[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x13U][3U];
+	vcdp->fullArray(c+3976,(__Vtemp566),128);
+	__Vtemp567[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x14U][0U];
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+	    [0x14U][1U];
+	__Vtemp567[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x14U][2U];
+	__Vtemp567[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x14U][3U];
+	vcdp->fullArray(c+3980,(__Vtemp567),128);
+	__Vtemp568[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x15U][0U];
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+	    [0x15U][1U];
+	__Vtemp568[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x15U][2U];
+	__Vtemp568[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x15U][3U];
+	vcdp->fullArray(c+3984,(__Vtemp568),128);
+	__Vtemp569[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x16U][0U];
+	__Vtemp569[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x16U][1U];
+	__Vtemp569[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data
+	    [0x16U][2U];
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+	    [2U][3U];
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+	    [3U][2U];
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+	    [3U][3U];
+	vcdp->fullArray(c+4138,(__Vtemp582),128);
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+	vcdp->fullBit  (c+4811,(vlTOPp->in_dcache_in_valid[0]));
+	vcdp->fullBit  (c+4812,(vlTOPp->in_dcache_in_valid[1]));
+	vcdp->fullBit  (c+4813,(vlTOPp->in_dcache_in_valid[2]));
+	vcdp->fullBit  (c+4814,(vlTOPp->in_dcache_in_valid[3]));
+	vcdp->fullBus  (c+4815,(vlTOPp->in_dcache_in_address[0]),32);
+	vcdp->fullBus  (c+4816,(vlTOPp->in_dcache_in_address[1]),32);
+	vcdp->fullBus  (c+4817,(vlTOPp->in_dcache_in_address[2]),32);
+	vcdp->fullBus  (c+4818,(vlTOPp->in_dcache_in_address[3]),32);
+	vcdp->fullBit  (c+4819,(vlTOPp->out_dcache_stall));
+	vcdp->fullBus  (c+4820,(((IData)(vlTOPp->in_icache_valid_pc_addr)
 				  ? 2U : 7U)),3);
-	__Vtemp537[0U] = 0U;
-	__Vtemp537[1U] = 0U;
-	__Vtemp537[2U] = 0U;
-	__Vtemp537[3U] = 0U;
-	vcdp->fullArray(c+3080,(__Vtemp537),128);
-	vcdp->fullBus  (c+3084,(7U),3);
-	vcdp->fullBus  (c+3085,(0U),32);
-	vcdp->fullBit  (c+3086,(0U));
-	vcdp->fullBus  (c+3087,(0x2000U),32);
-	vcdp->fullBus  (c+3088,(4U),32);
-	vcdp->fullBus  (c+3089,(0x10U),32);
-	vcdp->fullBus  (c+3090,(2U),32);
-	vcdp->fullBus  (c+3091,(0x80U),32);
-	vcdp->fullBus  (c+3092,(3U),32);
-	vcdp->fullBus  (c+3093,(5U),32);
-	vcdp->fullBus  (c+3094,(6U),32);
-	vcdp->fullBus  (c+3095,(0xcU),32);
-	vcdp->fullBus  (c+3096,(4U),32);
-	vcdp->fullBus  (c+3097,(0xffffffffU),32);
-	vcdp->fullBus  (c+3098,(0x1000U),32);
-	vcdp->fullBus  (c+3099,(0x40U),32);
-	vcdp->fullBus  (c+3100,(0x20U),32);
-	vcdp->fullBus  (c+3101,(1U),32);
-	vcdp->fullBus  (c+3102,(0x14U),32);
-	vcdp->fullBus  (c+3103,(0xbU),32);
-	vcdp->fullBus  (c+3104,(0x1fU),32);
-	vcdp->fullBus  (c+3105,(0xaU),32);
-	vcdp->fullBus  (c+3106,(0xffffffc0U),32);
-	vcdp->fullArray(c+3107,(vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata),512);
-	vcdp->fullBus  (c+3123,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old),4);
-	vcdp->fullBus  (c+3124,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b),32);
-	vcdp->fullBus  (c+3125,(0U),2);
-	vcdp->fullBus  (c+3126,(0U),5);
-	vcdp->fullBus  (c+3127,(0x400U),32);
-	vcdp->fullBus  (c+3128,(0x16U),32);
-	vcdp->fullBus  (c+3129,(9U),32);
-	vcdp->fullBus  (c+3130,(8U),32);
-	vcdp->fullBus  (c+3131,(0xfffffff0U),32);
-	vcdp->fullArray(c+3132,(vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata),128);
-	vcdp->fullBus  (c+3136,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old),1);
-	vcdp->fullBus  (c+3137,(1U),32);
-	vcdp->fullBus  (c+3138,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b),32);
-	__Vtemp538[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U];
-	__Vtemp538[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U];
-	__Vtemp538[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U];
-	__Vtemp538[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U];
-	vcdp->fullArray(c+3139,(__Vtemp538),128);
-	__Vtemp539[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U];
-	__Vtemp539[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U];
-	__Vtemp539[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U];
-	__Vtemp539[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U];
-	vcdp->fullArray(c+3143,(__Vtemp539),128);
-	__Vtemp540[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U];
-	__Vtemp540[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U];
-	__Vtemp540[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU];
-	__Vtemp540[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU];
-	vcdp->fullArray(c+3147,(__Vtemp540),128);
-	__Vtemp541[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU];
-	__Vtemp541[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU];
-	__Vtemp541[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU];
-	__Vtemp541[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU];
-	vcdp->fullArray(c+3151,(__Vtemp541),128);
+	__Vtemp675[0U] = 0U;
+	__Vtemp675[1U] = 0U;
+	__Vtemp675[2U] = 0U;
+	__Vtemp675[3U] = 0U;
+	vcdp->fullArray(c+4821,(__Vtemp675),128);
+	vcdp->fullBus  (c+4825,(7U),3);
+	vcdp->fullBus  (c+4826,(0U),32);
+	vcdp->fullBit  (c+4827,(0U));
+	vcdp->fullBus  (c+4828,(0x2000U),32);
+	vcdp->fullBus  (c+4829,(4U),32);
+	vcdp->fullBus  (c+4830,(0x10U),32);
+	vcdp->fullBus  (c+4831,(2U),32);
+	vcdp->fullBus  (c+4832,(0x80U),32);
+	vcdp->fullBus  (c+4833,(3U),32);
+	vcdp->fullBus  (c+4834,(5U),32);
+	vcdp->fullBus  (c+4835,(6U),32);
+	vcdp->fullBus  (c+4836,(0xcU),32);
+	vcdp->fullBus  (c+4837,(4U),32);
+	vcdp->fullBus  (c+4838,(0xffffffffU),32);
+	vcdp->fullBus  (c+4839,(0x1000U),32);
+	vcdp->fullBus  (c+4840,(0x40U),32);
+	vcdp->fullBus  (c+4841,(0x20U),32);
+	vcdp->fullBus  (c+4842,(1U),32);
+	vcdp->fullBus  (c+4843,(0x14U),32);
+	vcdp->fullBus  (c+4844,(0xbU),32);
+	vcdp->fullBus  (c+4845,(0x1fU),32);
+	vcdp->fullBus  (c+4846,(0xaU),32);
+	vcdp->fullBus  (c+4847,(0xffffffc0U),32);
+	vcdp->fullArray(c+4848,(vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata),512);
+	vcdp->fullBus  (c+4864,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old),4);
+	vcdp->fullBus  (c+4865,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b),32);
+	vcdp->fullArray(c+4866,(vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata),512);
+	vcdp->fullBus  (c+4882,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old),4);
+	vcdp->fullBus  (c+4883,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b),32);
+	vcdp->fullBus  (c+4884,(1U),32);
+	__Vtemp676[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0U];
+	__Vtemp676[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[1U];
+	__Vtemp676[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[2U];
+	__Vtemp676[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[3U];
+	vcdp->fullArray(c+4885,(__Vtemp676),128);
+	__Vtemp677[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[4U];
+	__Vtemp677[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[5U];
+	__Vtemp677[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[6U];
+	__Vtemp677[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[7U];
+	vcdp->fullArray(c+4889,(__Vtemp677),128);
+	__Vtemp678[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[8U];
+	__Vtemp678[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[9U];
+	__Vtemp678[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0xaU];
+	__Vtemp678[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0xbU];
+	vcdp->fullArray(c+4893,(__Vtemp678),128);
+	__Vtemp679[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0xcU];
+	__Vtemp679[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0xdU];
+	__Vtemp679[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0xeU];
+	__Vtemp679[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0xfU];
+	vcdp->fullArray(c+4897,(__Vtemp679),128);
+	__Vtemp680[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U];
+	__Vtemp680[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U];
+	__Vtemp680[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U];
+	__Vtemp680[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U];
+	vcdp->fullArray(c+4901,(__Vtemp680),128);
+	__Vtemp681[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U];
+	__Vtemp681[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U];
+	__Vtemp681[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U];
+	__Vtemp681[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U];
+	vcdp->fullArray(c+4905,(__Vtemp681),128);
+	__Vtemp682[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U];
+	__Vtemp682[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U];
+	__Vtemp682[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU];
+	__Vtemp682[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU];
+	vcdp->fullArray(c+4909,(__Vtemp682),128);
+	__Vtemp683[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU];
+	__Vtemp683[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU];
+	__Vtemp683[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU];
+	__Vtemp683[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU];
+	vcdp->fullArray(c+4913,(__Vtemp683),128);
     }
 }
diff --git a/simX/obj_dir/Vcache_simX__ver.d b/simX/obj_dir/Vcache_simX__ver.d
index 8c664704..7374f89e 100644
--- a/simX/obj_dir/Vcache_simX__ver.d
+++ b/simX/obj_dir/Vcache_simX__ver.d
@@ -1 +1 @@
-obj_dir/Vcache_simX.cpp obj_dir/Vcache_simX.h obj_dir/Vcache_simX.mk obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h obj_dir/Vcache_simX_VX_dcache_request_inter.cpp obj_dir/Vcache_simX_VX_dcache_request_inter.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h obj_dir/Vcache_simX__Syms.cpp obj_dir/Vcache_simX__Syms.h obj_dir/Vcache_simX__Trace.cpp obj_dir/Vcache_simX__Trace__Slow.cpp obj_dir/Vcache_simX__ver.d obj_dir/Vcache_simX_classes.mk  : /usr/bin/verilator_bin   ../rtl/./VX_define_synth.v ../rtl/VX_countones.v ../rtl/VX_define.v ../rtl/VX_dmem_controller.v ../rtl/VX_generic_priority_encoder.v ../rtl/VX_priority_encoder_w_mask.v ../rtl/cache/VX_Cache_Bank.v ../rtl/cache/VX_cache_bank_valid.v ../rtl/cache/VX_cache_data.v ../rtl/cache/VX_cache_data_per_index.v ../rtl/cache/VX_d_cache.v ../rtl/interfaces/VX_dcache_request_inter.v ../rtl/interfaces/VX_dcache_response_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_icache_request_inter.v ../rtl/interfaces/VX_icache_response_inter.v ../rtl/shared_memory/../VX_define.v ../rtl/shared_memory/VX_bank_valids.v ../rtl/shared_memory/VX_priority_encoder_sm.v ../rtl/shared_memory/VX_shared_memory.v ../rtl/shared_memory/VX_shared_memory_block.v /usr/bin/verilator_bin cache_simX.v 
+obj_dir/Vcache_simX.cpp obj_dir/Vcache_simX.h obj_dir/Vcache_simX.mk obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h obj_dir/Vcache_simX_VX_dcache_request_inter.cpp obj_dir/Vcache_simX_VX_dcache_request_inter.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h obj_dir/Vcache_simX__Syms.cpp obj_dir/Vcache_simX__Syms.h obj_dir/Vcache_simX__Trace.cpp obj_dir/Vcache_simX__Trace__Slow.cpp obj_dir/Vcache_simX__ver.d obj_dir/Vcache_simX_classes.mk  : /usr/bin/verilator_bin   ../rtl/./VX_define_synth.v ../rtl/VX_countones.v ../rtl/VX_define.v ../rtl/VX_dmem_controller.v ../rtl/VX_generic_priority_encoder.v ../rtl/VX_priority_encoder_w_mask.v ../rtl/cache/VX_Cache_Bank.v ../rtl/cache/VX_cache_bank_valid.v ../rtl/cache/VX_cache_data.v ../rtl/cache/VX_cache_data_per_index.v ../rtl/cache/VX_d_cache.v ../rtl/interfaces/VX_dcache_request_inter.v ../rtl/interfaces/VX_dcache_response_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_icache_request_inter.v ../rtl/interfaces/VX_icache_response_inter.v ../rtl/shared_memory/../VX_define.v ../rtl/shared_memory/VX_bank_valids.v ../rtl/shared_memory/VX_priority_encoder_sm.v ../rtl/shared_memory/VX_shared_memory.v ../rtl/shared_memory/VX_shared_memory_block.v /usr/bin/verilator_bin cache_simX.v 
diff --git a/simX/obj_dir/Vcache_simX__verFiles.dat b/simX/obj_dir/Vcache_simX__verFiles.dat
index 97154400..8f8ba9d8 100644
--- a/simX/obj_dir/Vcache_simX__verFiles.dat
+++ b/simX/obj_dir/Vcache_simX__verFiles.dat
@@ -1,43 +1,43 @@
 # DESCRIPTION: Verilator output: Timestamp data for --skip-identical.  Delete at will.
-C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
-S        26  4200738  1579395713   628434579  1579395713   628434579 "../rtl/./VX_define_synth.v"
-S       283  4200733  1579395713   624434332  1579395713   624434332 "../rtl/VX_countones.v"
-S      7240  4200737  1579395713   628434579  1579395713   628434579 "../rtl/VX_define.v"
-S      8325  4200739  1579395713   628434579  1579395713   628434579 "../rtl/VX_dmem_controller.v"
-S       517  4200743  1579395713   628434579  1579395713   628434579 "../rtl/VX_generic_priority_encoder.v"
-S       683  4200754  1579395713   628434579  1579395713   628434579 "../rtl/VX_priority_encoder_w_mask.v"
-S      8590  4200764  1579395713   628434579  1579395713   628434579 "../rtl/cache/VX_Cache_Bank.v"
-S       748  4200765  1579395713   628434579  1579395713   628434579 "../rtl/cache/VX_cache_bank_valid.v"
-S      7349  4200766  1579395713   628434579  1579395713   628434579 "../rtl/cache/VX_cache_data.v"
-S      6476  4200767  1579395713   628434579  1579395713   628434579 "../rtl/cache/VX_cache_data_per_index.v"
-S     14645  4200768  1579395713   628434579  1579395713   628434579 "../rtl/cache/VX_d_cache.v"
-S       393  4200780  1579395713   628434579  1579395713   628434579 "../rtl/interfaces/VX_dcache_request_inter.v"
-S       215  4200781  1579395713   628434579  1579395713   628434579 "../rtl/interfaces/VX_dcache_response_inter.v"
-S       870  4200782  1579395713   628434579  1579395713   628434579 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
-S       354  4200791  1579395713   628434579  1579395713   628434579 "../rtl/interfaces/VX_icache_request_inter.v"
-S       212  4200792  1579395713   628434579  1579395713   628434579 "../rtl/interfaces/VX_icache_response_inter.v"
-S      7240  4200737  1579395713   628434579  1579395713   628434579 "../rtl/shared_memory/../VX_define.v"
-S       676  4200836  1579395713   632434826  1579395713   632434826 "../rtl/shared_memory/VX_bank_valids.v"
-S      3038  4200837  1579395713   632434826  1579395713   632434826 "../rtl/shared_memory/VX_priority_encoder_sm.v"
-S      4962  4200838  1579395713   632434826  1579395713   632434826 "../rtl/shared_memory/VX_shared_memory.v"
-S      3207  4200839  1579395713   632434826  1579395713   632434826 "../rtl/shared_memory/VX_shared_memory_block.v"
-S   5279832  2492902  1578745602   593855204  1519110675           0 "/usr/bin/verilator_bin"
-S      3144  4201058  1579395714   588493892  1579395714   588493892 "cache_simX.v"
-T    606556  4194579  1579629057   329619018  1579629057   329619018 "obj_dir/Vcache_simX.cpp"
-T     31121  4194577  1579629057   321619018  1579629057   321619018 "obj_dir/Vcache_simX.h"
-T      2305  4196430  1579629057   341619018  1579629057   341619018 "obj_dir/Vcache_simX.mk"
-T    539818  4194597  1579629057   341619018  1579629057   341619018 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
-T     19062  4194595  1579629057   329619018  1579629057   329619018 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
-T      1024  4194591  1579629057   329619018  1579629057   329619018 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
-T      1561  4194589  1579629057   329619018  1579629057   329619018 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
-T       999  4194587  1579629057   329619018  1579629057   329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
-T      1556  4194585  1579629057   329619018  1579629057   329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
-T       999  4194583  1579629057   329619018  1579629057   329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
-T      1557  4194581  1579629057   329619018  1579629057   329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
-T      3807  4194517  1579629057   293619017  1579629057   293619017 "obj_dir/Vcache_simX__Syms.cpp"
-T      1918  4194514  1579629057   293619017  1579629057   293619017 "obj_dir/Vcache_simX__Syms.h"
-T    704422  4194575  1579629057   317619018  1579629057   317619018 "obj_dir/Vcache_simX__Trace.cpp"
-T    921157  4194573  1579629057   309619018  1579629057   309619018 "obj_dir/Vcache_simX__Trace__Slow.cpp"
-T      1461  4196431  1579629057   341619018  1579629057   341619018 "obj_dir/Vcache_simX__ver.d"
-T         0        0  1579629057   341619018  1579629057   341619018 "obj_dir/Vcache_simX__verFiles.dat"
-T      1403  4196429  1579629057   341619018  1579629057   341619018 "obj_dir/Vcache_simX_classes.mk"
+C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
+S        26 1407374883617647  1583036691   972658000  1583036691   972658000 "../rtl/./VX_define_synth.v"
+S       283 1407374883617640  1583036691   969666100  1583036691   969666100 "../rtl/VX_countones.v"
+S      7257 1407374883617646  1583036691   972658000  1583036691   972658000 "../rtl/VX_define.v"
+S      8325 1407374883617648  1583036691   973655300  1583036691   973655300 "../rtl/VX_dmem_controller.v"
+S       517 1407374883617652  1583036691   975649300  1583036691   975649300 "../rtl/VX_generic_priority_encoder.v"
+S       683 1407374883617664  1583036691   981634100  1583036691   981634100 "../rtl/VX_priority_encoder_w_mask.v"
+S      8590 1407374883617675  1583036691   985623400  1583036691   985623400 "../rtl/cache/VX_Cache_Bank.v"
+S       748 1407374883617676  1583036691   986620700  1583036691   986620700 "../rtl/cache/VX_cache_bank_valid.v"
+S      7349 1407374883617677  1583036691   986620700  1583036691   986620700 "../rtl/cache/VX_cache_data.v"
+S      6476 1407374883617678  1583036691   987617400  1583036691   987617400 "../rtl/cache/VX_cache_data_per_index.v"
+S     14645 1407374883617679  1583036691   987617400  1583036691   987617400 "../rtl/cache/VX_d_cache.v"
+S       393 1407374883617692  1583036691   993601900  1583036691   993601900 "../rtl/interfaces/VX_dcache_request_inter.v"
+S       215 1407374883617693  1583036691   994599200  1583036691   994599200 "../rtl/interfaces/VX_dcache_response_inter.v"
+S       870 1407374883617694  1583036691   994599200  1583036691   994599200 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
+S       354 1407374883617709  1583036691   999585900  1583036691   999585900 "../rtl/interfaces/VX_icache_request_inter.v"
+S       212 1407374883617710  1583036691   999585900  1583036691   999585900 "../rtl/interfaces/VX_icache_response_inter.v"
+S      7257 1407374883617646  1583036691   972658000  1583036691   972658000 "../rtl/shared_memory/../VX_define.v"
+S       676 1407374883617754  1583036692    20529900  1583036692    20529900 "../rtl/shared_memory/VX_bank_valids.v"
+S      3038 1407374883617755  1583036692    21526400  1583036692    21526400 "../rtl/shared_memory/VX_priority_encoder_sm.v"
+S      4962 1407374883617756  1583036692    22524600  1583036692    22524600 "../rtl/shared_memory/VX_shared_memory.v"
+S      3207 1407374883617757  1583036692    22524600  1583036692    22524600 "../rtl/shared_memory/VX_shared_memory_block.v"
+S   5279832 1125899907857040  1579658333   790142700  1519110675           0 "/usr/bin/verilator_bin"
+S      3144 1407374883617983  1583036693   278327800  1583036693   278327800 "cache_simX.v"
+T    390173 4222124650721525  1583038884   772480200  1583038884   772480200 "obj_dir/Vcache_simX.cpp"
+T     28278 5066549580853492  1583038884   765499600  1583038884   765499600 "obj_dir/Vcache_simX.h"
+T      2365 18858823439675736  1583038884   803378700  1583038884   803378700 "obj_dir/Vcache_simX.mk"
+T    643931 2533274790457603  1583038884   802128000  1583038884   802128000 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
+T     23659 2533274790457602  1583038884   788131800  1583038884   788131800 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
+T    578414 2533274790457601  1583038884   787134700  1583038884   787134700 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp"
+T     23321 4222124650721534  1583038884   776161100  1583038884   776161100 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h"
+T      1024 2251799813746939  1583038884   775163700  1583038884   775163700 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
+T      1561 5348024557564153  1583038884   774165800  1583038884   774165800 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
+T       999 2533274790457592  1583038884   773299100  1583038884   773299100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
+T      1557 2814749767168246  1583038884   773299100  1583038884   773299100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
+T      6004 14073748835594442  1583038884   720643500  1583038884   720643500 "obj_dir/Vcache_simX__Syms.cpp"
+T      2455 3096224743878468  1583038884   719619200  1583038884   719619200 "obj_dir/Vcache_simX__Syms.h"
+T   1114242 5066549580853489  1583038884   763504200  1583038884   763504200 "obj_dir/Vcache_simX__Trace.cpp"
+T   1433229 3377699720589552  1583038884   745891000  1583038884   745891000 "obj_dir/Vcache_simX__Trace__Slow.cpp"
+T      1439 1688849860325816  1583038884   804364500  1583038884   804364500 "obj_dir/Vcache_simX__ver.d"
+T         0        0  1583038884   836313300  1583038884   836313300 "obj_dir/Vcache_simX__verFiles.dat"
+T      1392 2251799813746948  1583038884   802128000  1583038884   802128000 "obj_dir/Vcache_simX_classes.mk"
diff --git a/simX/obj_dir/Vcache_simX_classes.mk b/simX/obj_dir/Vcache_simX_classes.mk
index 61f3273c..cb8571dc 100644
--- a/simX/obj_dir/Vcache_simX_classes.mk
+++ b/simX/obj_dir/Vcache_simX_classes.mk
@@ -17,8 +17,8 @@ VM_TRACE = 1
 VM_CLASSES_FAST += \
 	Vcache_simX \
 	Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 \
-	Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 \
 	Vcache_simX_VX_dcache_request_inter \
+	Vcache_simX_VX_Cache_Bank__pi9 \
 	Vcache_simX_VX_Cache_Bank__pi8 \
 
 # Generated module classes, non-fast-path, compile with low/medium optimization
diff --git a/simX/obj_dir/core.o b/simX/obj_dir/core.o
index e17e2431..45c63a1d 100644
Binary files a/simX/obj_dir/core.o and b/simX/obj_dir/core.o differ
diff --git a/simX/obj_dir/emulator.debug b/simX/obj_dir/emulator.debug
deleted file mode 100644
index 48bafd32..00000000
--- a/simX/obj_dir/emulator.debug
+++ /dev/null
@@ -1 +0,0 @@
-../rvvector/basic/vx_vector_main.hex not found
diff --git a/simX/obj_dir/enc.o b/simX/obj_dir/enc.o
index b35d5861..ebf7ce94 100644
Binary files a/simX/obj_dir/enc.o and b/simX/obj_dir/enc.o differ
diff --git a/simX/obj_dir/instruction.o b/simX/obj_dir/instruction.o
index 2ce51278..59823d29 100644
Binary files a/simX/obj_dir/instruction.o and b/simX/obj_dir/instruction.o differ
diff --git a/simX/obj_dir/mem.o b/simX/obj_dir/mem.o
index 4e52e766..728ad627 100644
Binary files a/simX/obj_dir/mem.o and b/simX/obj_dir/mem.o differ
diff --git a/simX/obj_dir/simX.o b/simX/obj_dir/simX.o
index b7d7869f..4e1f7a1c 100644
Binary files a/simX/obj_dir/simX.o and b/simX/obj_dir/simX.o differ
diff --git a/simX/out b/simX/out
deleted file mode 100644
index 40a41b45..00000000
--- a/simX/out
+++ /dev/null
@@ -1,2 +0,0 @@
-verilator --compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp  -CFLAGS '-std=c++11 -fPIC -O3' -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1 
-Makefile:26: recipe for target 'simX' failed
diff --git a/simX/reading_data.txt b/simX/reading_data.txt
deleted file mode 100644
index f9ca6812..00000000
--- a/simX/reading_data.txt
+++ /dev/null
@@ -1 +0,0 @@
-hello this is the data read from a file!
diff --git a/simX/results.txt b/simX/results.txt
deleted file mode 100644
index d44e18fb..00000000
--- a/simX/results.txt
+++ /dev/null
@@ -1 +0,0 @@
-start
diff --git a/simX/test_rv32ui.sh b/simX/test_rv32ui.sh
old mode 100644
new mode 100755