From 8a9a67aa5a29f3e29b8273893b89b99406a8343d Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 27 Feb 2021 21:54:55 -0800 Subject: [PATCH] minor update --- hw/rtl/VX_decode.v | 28 ++++++++++++++++++---------- hw/rtl/VX_define.vh | 22 ++++++++++++++++------ hw/rtl/VX_lsu_unit.v | 12 +++++++----- hw/rtl/VX_print_instr.vh | 7 +++++-- 4 files changed, 46 insertions(+), 23 deletions(-) diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index 8ad5b1e2..d03f31f7 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -209,7 +209,7 @@ module VX_decode #( `endif `INST_L: begin ex_type = `EX_LSU; - op_type = `OP_BITS'(func3); + op_type = `OP_BITS'({1'b0, func3}); imm = {{20{u_12[11]}}, u_12}; use_rd = 1; use_rs1 = 1; @@ -222,7 +222,7 @@ module VX_decode #( `endif `INST_S: begin ex_type = `EX_LSU; - op_type = `OP_BITS'(func3); + op_type = `OP_BITS'({1'b1, func3}); imm = {{20{func7[6]}}, func7, rd}; use_rs1 = 1; use_rs2 = 1; @@ -291,6 +291,11 @@ module VX_decode #( // FSGNJ=0, FSGNJN=1, FSGNJX=2 op_type = `OP_BITS'(`FPU_MISC); op_mod = {1'b0, func3[1:0]}; + use_rs1 = 1; + use_rs2 = 1; + rd_fp = 1; + rs1_fp = 1; + rs2_fp = 1; end 7'h14: begin // FMIN=3, FMAX=4 @@ -358,17 +363,20 @@ module VX_decode #( endcase end + // disable write to integer register r0 + wire use_rd_qual = use_rd && (rd_fp || (rd != 0)); + // EX_ALU needs rs1=0 for LUI operation wire [4:0] rs1_qual = (opcode == `INST_LUI) ? 5'h0 : rs1; - assign decode_if.valid = ifetch_rsp_if.valid; - assign decode_if.wid = ifetch_rsp_if.wid; - assign decode_if.tmask = ifetch_rsp_if.tmask; - assign decode_if.PC = ifetch_rsp_if.PC; - assign decode_if.ex_type= ex_type; - assign decode_if.op_type= op_type; - assign decode_if.op_mod = op_mod; - assign decode_if.wb = use_rd; + assign decode_if.valid = ifetch_rsp_if.valid; + assign decode_if.wid = ifetch_rsp_if.wid; + assign decode_if.tmask = ifetch_rsp_if.tmask; + assign decode_if.PC = ifetch_rsp_if.PC; + assign decode_if.ex_type = ex_type; + assign decode_if.op_type = op_type; + assign decode_if.op_mod = op_mod; + assign decode_if.wb = use_rd_qual; `ifdef EXT_F_ENABLE assign decode_if.rd = {rd_fp, rd}; diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 88fc0242..66afd80e 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -132,12 +132,22 @@ `define IS_DIV_OP(x) x[2] `define IS_MUL_MOD(x) x[1] -`define LSU_SB 3'h0 -`define LSU_SH 3'h1 -`define LSU_SW 3'h2 -`define LSU_UB 3'h4 -`define LSU_UH 3'h5 -`define LSU_BITS 3 +`define FMT_B 3'b000 +`define FMT_H 3'b001 +`define FMT_W 3'b010 +`define FMT_BU 3'b100 +`define FMT_HU 3'b101 + +`define LSU_LB 4'b0000 +`define LSU_LH 4'b0001 +`define LSU_LW 4'b0010 +`define LSU_LBU 4'b0100 +`define LSU_LHU 4'b0101 +`define LSU_SB 4'b1000 +`define LSU_SH 4'b1001 +`define LSU_SW 4'b1010 +`define LSU_BITS 4 +`define LSU_FMT(x) x[2:0] `define LSU_WSIZE(x) x[1:0] `define LSU_OP(x) x[`LSU_BITS-1:0] diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index d33e74e5..2fa7e50a 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -69,6 +69,8 @@ module VX_lsu_unit #( wire rsp_wb; wire [`LSU_BITS-1:0] rsp_type; wire rsp_is_dup; + + `UNUSED_VAR (rsp_type) reg [`LSUQ_SIZE-1:0][`NUM_THREADS-1:0] rsp_rem_mask; reg [`NUM_THREADS-1:0] rsp_rem_mask_n; @@ -220,11 +222,11 @@ module VX_lsu_unit #( end always @(*) begin - case (rsp_type) - `LSU_SB: rsp_data[i] = 32'(signed'(rsp_data_shifted[7:0])); - `LSU_SH: rsp_data[i] = 32'(signed'(rsp_data_shifted[15:0])); - `LSU_UB: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[7:0])); - `LSU_UH: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[15:0])); + case (`LSU_FMT(rsp_type)) + `FMT_B: rsp_data[i] = 32'(signed'(rsp_data_shifted[7:0])); + `FMT_H: rsp_data[i] = 32'(signed'(rsp_data_shifted[15:0])); + `FMT_BU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[7:0])); + `FMT_HU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[15:0])); default: rsp_data[i] = rsp_data_shifted; endcase end diff --git a/hw/rtl/VX_print_instr.vh b/hw/rtl/VX_print_instr.vh index d25624e2..81f63aeb 100644 --- a/hw/rtl/VX_print_instr.vh +++ b/hw/rtl/VX_print_instr.vh @@ -72,11 +72,14 @@ task print_ex_op ( end `EX_LSU: begin case (`LSU_BITS'(op_type)) + `LSU_LB: $write("LB"); + `LSU_LH: $write("LH"); + `LSU_LW: $write("LW"); + `LSU_LBU:$write("LBU"); + `LSU_LHU:$write("LHU"); `LSU_SB: $write("SB"); `LSU_SH: $write("SH"); `LSU_SW: $write("SW"); - `LSU_UB: $write("UB"); - `LSU_UH: $write("UH"); default: $write("?"); endcase end