From 8ab7c590fd2c48d7929cd0a486b34886571767ac Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 31 Jan 2024 06:16:54 -0800 Subject: [PATCH] disabling fetch's deadlock check when L1 caches are present --- hw/rtl/VX_define.vh | 7 +++++++ hw/rtl/core/VX_decode.sv | 3 ++- hw/rtl/core/VX_fetch.sv | 11 +++++++---- hw/rtl/core/VX_ibuffer.sv | 3 ++- hw/rtl/interfaces/VX_decode_if.sv | 13 +++++++++---- hw/rtl/interfaces/VX_fetch_if.sv | 11 ++++++++--- 6 files changed, 35 insertions(+), 13 deletions(-) diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 63f2d42d..093a5fd2 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -291,6 +291,13 @@ /////////////////////////////////////////////////////////////////////////////// +`ifdef ICACHE_ENABLE +`define L1_ENABLE +`endif +`ifdef DCACHE_ENABLE +`define L1_ENABLE +`endif + `ifdef L2_ENABLE `define L2_LINE_SIZE `MEM_BLOCK_SIZE `else diff --git a/hw/rtl/core/VX_decode.sv b/hw/rtl/core/VX_decode.sv index 0032fe7b..0a6b00ec 100644 --- a/hw/rtl/core/VX_decode.sv +++ b/hw/rtl/core/VX_decode.sv @@ -533,8 +533,9 @@ module VX_decode #( assign decode_sched_if.valid = fetch_fire; assign decode_sched_if.wid = fetch_if.data.wid; assign decode_sched_if.is_wstall = is_wstall; - +`ifndef L1_ENABLE assign fetch_if.ibuf_pop = decode_if.ibuf_pop; +`endif `ifdef DBG_TRACE_CORE_PIPELINE always @(posedge clk) begin diff --git a/hw/rtl/core/VX_fetch.sv b/hw/rtl/core/VX_fetch.sv index ef52ef65..db5a1d73 100644 --- a/hw/rtl/core/VX_fetch.sv +++ b/hw/rtl/core/VX_fetch.sv @@ -32,7 +32,6 @@ module VX_fetch import VX_gpu_pkg::*; #( ); `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (reset) - localparam ISW_WIDTH = `LOG2UP(`ISSUE_WIDTH); wire icache_req_valid; wire [ICACHE_ADDR_WIDTH-1:0] icache_req_addr; @@ -44,8 +43,6 @@ module VX_fetch import VX_gpu_pkg::*; #( wire icache_req_fire = icache_req_valid && icache_req_ready; - wire [ISW_WIDTH-1:0] schedule_isw = wid_to_isw(schedule_if.data.wid); - assign req_tag = schedule_if.data.wid; assign {rsp_uuid, rsp_tag} = icache_bus_if.rsp_data.tag; @@ -68,9 +65,12 @@ module VX_fetch import VX_gpu_pkg::*; #( .rdata ({rsp_PC, rsp_tmask}) ); +`ifndef L1_ENABLE // Ensure that the ibuffer doesn't fill up. // This resolves potential deadlock if ibuffer fills and the LSU stalls the execute stage due to pending dcache request. // This issue is particularly prevalent when the icache and dcache is disabled and both requests share the same bus. + wire [ISSUE_ISW-1:0] schedule_isw = wid_to_isw(schedule_if.data.wid); + wire [`ISSUE_WIDTH-1:0] pending_ibuf_full; for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin VX_pending_size #( @@ -85,13 +85,16 @@ module VX_fetch import VX_gpu_pkg::*; #( `UNUSED_PIN (empty) ); end + wire ibuf_ready = ~pending_ibuf_full[schedule_isw]; +`else + wire ibuf_ready = 1'b1; +`endif `RUNTIME_ASSERT((!schedule_if.valid || schedule_if.data.PC != 0), ("%t: *** invalid PC=0x%0h, wid=%0d, tmask=%b (#%0d)", $time, schedule_if.data.PC, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.uuid)) // Icache Request - wire ibuf_ready = ~pending_ibuf_full[schedule_isw]; assign icache_req_valid = schedule_if.valid && ibuf_ready; assign icache_req_addr = schedule_if.data.PC[`MEM_ADDR_WIDTH-1:2]; assign icache_req_tag = {schedule_if.data.uuid, req_tag}; diff --git a/hw/rtl/core/VX_ibuffer.sv b/hw/rtl/core/VX_ibuffer.sv index b6847edc..b465c195 100644 --- a/hw/rtl/core/VX_ibuffer.sv +++ b/hw/rtl/core/VX_ibuffer.sv @@ -66,8 +66,9 @@ module VX_ibuffer import VX_gpu_pkg::*; #( .valid_out (ibuffer_if[i].valid), .ready_out(ibuffer_if[i].ready) ); - + `ifndef L1_ENABLE assign decode_if.ibuf_pop[i] = ibuffer_if[i].valid && ibuffer_if[i].ready; + `endif end endmodule diff --git a/hw/rtl/interfaces/VX_decode_if.sv b/hw/rtl/interfaces/VX_decode_if.sv index d433ca47..2a357abd 100644 --- a/hw/rtl/interfaces/VX_decode_if.sv +++ b/hw/rtl/interfaces/VX_decode_if.sv @@ -36,21 +36,26 @@ interface VX_decode_if (); logic valid; data_t data; logic ready; - - wire [`ISSUE_WIDTH-1:0] ibuf_pop; +`ifndef L1_ENABLE + logic [`ISSUE_WIDTH-1:0] ibuf_pop; +`endif modport master ( output valid, output data, - input ibuf_pop, input ready + `ifndef L1_ENABLE + , input ibuf_pop + `endif ); modport slave ( input valid, input data, - output ibuf_pop, output ready + `ifndef L1_ENABLE + , output ibuf_pop + `endif ); endinterface diff --git a/hw/rtl/interfaces/VX_fetch_if.sv b/hw/rtl/interfaces/VX_fetch_if.sv index 06b27d90..cbfecdd2 100644 --- a/hw/rtl/interfaces/VX_fetch_if.sv +++ b/hw/rtl/interfaces/VX_fetch_if.sv @@ -26,21 +26,26 @@ interface VX_fetch_if (); logic valid; data_t data; logic ready; - +`ifndef L1_ENABLE logic [`ISSUE_WIDTH-1:0] ibuf_pop; +`endif modport master ( output valid, output data, - input ibuf_pop, input ready + `ifndef L1_ENABLE + , input ibuf_pop + `endif ); modport slave ( input valid, input data, - output ibuf_pop, output ready + `ifndef L1_ENABLE + , output ibuf_pop + `endif ); endinterface