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minor update

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This commit is contained in:
Blaise Tine
2021-01-06 21:39:15 -08:00
parent 146c285aa0
commit 8aea9cbe07
3 changed files with 12 additions and 7 deletions
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4
hw/rtl/VX_config.vh
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@@ -55,6 +55,10 @@
`define SHARED_MEM_BASE_ADDR `IO_BUS_BASE_ADDR `define SHARED_MEM_BASE_ADDR `IO_BUS_BASE_ADDR
`endif `endif
`ifndef SHARED_MEM_BASE_ADDR_ALIGN
`define SHARED_MEM_BASE_ADDR_ALIGN 64
`endif
`ifndef IO_BUS_ADDR_COUT `ifndef IO_BUS_ADDR_COUT
`define IO_BUS_ADDR_COUT 32'hFFFFFFFC `define IO_BUS_ADDR_COUT 32'hFFFFFFFC
`endif `endif

8
hw/rtl/VX_databus_arb.v
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@@ -18,7 +18,9 @@ module VX_databus_arb (
// output response // output response
VX_cache_core_rsp_if core_rsp_if VX_cache_core_rsp_if core_rsp_if
); );
localparam REQ_ADDRW = 32 - `CLOG2(`DWORD_SIZE); localparam SMEM_ASHIFT = `CLOG2(`SHARED_MEM_BASE_ADDR_ALIGN);
localparam REQ_ASHIFT = `CLOG2(`DWORD_SIZE);
localparam REQ_ADDRW = 32 - REQ_ASHIFT;
localparam REQ_DATAW = REQ_ADDRW + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH; localparam REQ_DATAW = REQ_ADDRW + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH; localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
@@ -33,8 +35,8 @@ module VX_databus_arb (
// select shared memory bus // select shared memory bus
wire is_smem_addr = core_req_if.valid[i] && `SM_ENABLE wire is_smem_addr = core_req_if.valid[i] && `SM_ENABLE
&& (core_req_if.addr[i] >= REQ_ADDRW'((`SHARED_MEM_BASE_ADDR - `SMEM_SIZE) >> 2)) && (core_req_if.addr[i][REQ_ADDRW-1:SMEM_ASHIFT-REQ_ASHIFT] >= (32-SMEM_ASHIFT)'((`SHARED_MEM_BASE_ADDR - `SMEM_SIZE) >> SMEM_ASHIFT))
&& (core_req_if.addr[i] < REQ_ADDRW'(`SHARED_MEM_BASE_ADDR >> 2)); && (core_req_if.addr[i][REQ_ADDRW-1:SMEM_ASHIFT-REQ_ASHIFT] < (32-SMEM_ASHIFT)'(`SHARED_MEM_BASE_ADDR >> SMEM_ASHIFT));
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (REQ_DATAW) .DATAW (REQ_DATAW)

3
hw/rtl/VX_lsu_unit.v
View File

@@ -77,8 +77,7 @@ module VX_lsu_unit #(
VX_pipe_register #( VX_pipe_register #(
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 2 + (`NUM_THREADS * (30 + 2 + 4 + 32))), .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 2 + (`NUM_THREADS * (30 + 2 + 4 + 32))),
.RESETW (1), .RESETW (1)
.DEPTH (0)
) req_pipe_reg ( ) req_pipe_reg (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),