From 8bc3b8b0a5a928c05b0ded36b481b720c841be08 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Mon, 14 Oct 2019 23:25:14 -0400 Subject: [PATCH] Need to link SystemC for sc_time_stamp() --- kernel/vortex_test.dump | 198 ++++---- kernel/vortex_test.elf | Bin 15604 -> 15636 bytes kernel/vortex_test.hex | 49 +- kernel/vx_main.c | 9 +- kernel/vx_os/vx_back/vx_back.s | 30 +- .../obj_dir/Vrf2_32x128_wm1.cpp | 289 +++++++++++ .../rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.h | 101 ++++ .../rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.mk | 53 +++ .../obj_dir/Vrf2_32x128_wm1__Syms.cpp | 19 + .../obj_dir/Vrf2_32x128_wm1__Syms.h | 35 ++ .../obj_dir/Vrf2_32x128_wm1__ver.d | 1 + .../obj_dir/Vrf2_32x128_wm1__verFiles.dat | 12 + .../obj_dir/Vrf2_32x128_wm1_classes.mk | 40 ++ .../cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v | 449 +++++++++--------- rtl/Makefile | 6 +- rtl/VX_decode.v | 4 +- rtl/VX_gpr.v | 11 +- rtl/VX_gpr_stage.v | 6 +- rtl/byte_enabled_simple_dual_port_ram.v | 6 +- rtl/results.txt | 8 +- rtl/tb_debug.h | 2 +- rtl/test_bench.h | 2 +- 22 files changed, 958 insertions(+), 372 deletions(-) create mode 100644 models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.cpp create mode 100644 models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.h create mode 100644 models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.mk create mode 100644 models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.cpp create mode 100644 models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.h create mode 100644 models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__ver.d create mode 100644 models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__verFiles.dat create mode 100644 models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1_classes.mk diff --git a/kernel/vortex_test.dump b/kernel/vortex_test.dump index 704a63ee..0b18e6bf 100644 --- a/kernel/vortex_test.dump +++ b/kernel/vortex_test.dump @@ -5,14 +5,14 @@ vortex_test.elf: file format elf32-littleriscv Disassembly of section .text: 80000000 <_start>: -80000000: 00800513 li a0,8 -80000004: 02051073 csrw 0x20,a0 -80000008: 00400513 li a0,4 -8000000c: 02151073 csrw 0x21,a0 -80000010: f1401073 csrw mhartid,zero -80000014: 30101073 csrw misa,zero -80000018: 7ffff137 lui sp,0x7ffff -8000001c: 091010ef jal ra,800018ac
+80000000: 00200593 li a1,2 +80000004: 00000013 nop +80000008: 00000013 nop +8000000c: 00000013 nop +80000010: 00058613 mv a2,a1 +80000014: 00000013 nop +80000018: 00000013 nop +8000001c: 00000013 nop 80000020: 00000073 ecall 80000024 : @@ -28,7 +28,7 @@ Disassembly of section .text: 80000038: 00755c63 bge a0,t2,80000050 8000003c : -8000003c: 80010113 addi sp,sp,-2048 # 7fffe800 +8000003c: 80010113 addi sp,sp,-2048 80000040: 00050313 mv t1,a0 80000044: 0003506b 0x3506b @@ -1604,96 +1604,102 @@ Disassembly of section .text: 80001788: 03010113 addi sp,sp,48 8000178c: 00008067 ret -80001790 : -80001790: fe010113 addi sp,sp,-32 -80001794: 00812e23 sw s0,28(sp) -80001798: 02010413 addi s0,sp,32 -8000179c: fe042623 sw zero,-20(s0) -800017a0: 0480006f j 800017e8 -800017a4: 810267b7 lui a5,0x81026 -800017a8: fec42703 lw a4,-20(s0) -800017ac: 00271713 slli a4,a4,0x2 -800017b0: 21c78793 addi a5,a5,540 # 8102621c -800017b4: 00f707b3 add a5,a4,a5 -800017b8: 00300713 li a4,3 -800017bc: 00e7a023 sw a4,0(a5) -800017c0: 810277b7 lui a5,0x81027 -800017c4: fec42703 lw a4,-20(s0) -800017c8: 00271713 slli a4,a4,0x2 -800017cc: 21c78793 addi a5,a5,540 # 8102721c -800017d0: 00f707b3 add a5,a4,a5 -800017d4: 00200713 li a4,2 -800017d8: 00e7a023 sw a4,0(a5) -800017dc: fec42783 lw a5,-20(s0) -800017e0: 00178793 addi a5,a5,1 -800017e4: fef42623 sw a5,-20(s0) -800017e8: fec42703 lw a4,-20(s0) -800017ec: 0ff00793 li a5,255 -800017f0: fae7dae3 bge a5,a4,800017a4 -800017f4: 00000013 nop -800017f8: 01c12403 lw s0,28(sp) -800017fc: 02010113 addi sp,sp,32 -80001800: 00008067 ret +80001790 : +80001790: ff010113 addi sp,sp,-16 +80001794: 00812623 sw s0,12(sp) +80001798: 01010413 addi s0,sp,16 +8000179c: 00000793 li a5,0 +800017a0: 00000813 li a6,0 +800017a4: 00078513 mv a0,a5 +800017a8: 00080593 mv a1,a6 +800017ac: 00c12403 lw s0,12(sp) +800017b0: 01010113 addi sp,sp,16 +800017b4: 00008067 ret -80001804 : -80001804: fd010113 addi sp,sp,-48 -80001808: 02112623 sw ra,44(sp) -8000180c: 02812423 sw s0,40(sp) -80001810: 03010413 addi s0,sp,48 -80001814: fca42e23 sw a0,-36(s0) -80001818: 810007b7 lui a5,0x81000 -8000181c: 11878513 addi a0,a5,280 # 81000118 -80001820: fb5fe0ef jal ra,800007d4 -80001824: fe042623 sw zero,-20(s0) -80001828: 0580006f j 80001880 -8000182c: fec42783 lw a5,-20(s0) -80001830: 00078e63 beqz a5,8000184c -80001834: fec42783 lw a5,-20(s0) -80001838: 00f7f793 andi a5,a5,15 -8000183c: 00079863 bnez a5,8000184c +800017b8 : +800017b8: fe010113 addi sp,sp,-32 +800017bc: 00812e23 sw s0,28(sp) +800017c0: 02010413 addi s0,sp,32 +800017c4: fe042623 sw zero,-20(s0) +800017c8: 0480006f j 80001810 +800017cc: 810267b7 lui a5,0x81026 +800017d0: fec42703 lw a4,-20(s0) +800017d4: 00271713 slli a4,a4,0x2 +800017d8: 21c78793 addi a5,a5,540 # 8102621c +800017dc: 00f707b3 add a5,a4,a5 +800017e0: 00300713 li a4,3 +800017e4: 00e7a023 sw a4,0(a5) +800017e8: 810277b7 lui a5,0x81027 +800017ec: fec42703 lw a4,-20(s0) +800017f0: 00271713 slli a4,a4,0x2 +800017f4: 21c78793 addi a5,a5,540 # 8102721c +800017f8: 00f707b3 add a5,a4,a5 +800017fc: 00200713 li a4,2 +80001800: 00e7a023 sw a4,0(a5) +80001804: fec42783 lw a5,-20(s0) +80001808: 00178793 addi a5,a5,1 +8000180c: fef42623 sw a5,-20(s0) +80001810: fec42703 lw a4,-20(s0) +80001814: 0ff00793 li a5,255 +80001818: fae7dae3 bge a5,a4,800017cc +8000181c: 00000013 nop +80001820: 01c12403 lw s0,28(sp) +80001824: 02010113 addi sp,sp,32 +80001828: 00008067 ret + +8000182c : +8000182c: fd010113 addi sp,sp,-48 +80001830: 02112623 sw ra,44(sp) +80001834: 02812423 sw s0,40(sp) +80001838: 03010413 addi s0,sp,48 +8000183c: fca42e23 sw a0,-36(s0) 80001840: 810007b7 lui a5,0x81000 -80001844: 13c78513 addi a0,a5,316 # 8100013c +80001844: 11878513 addi a0,a5,280 # 81000118 80001848: f8dfe0ef jal ra,800007d4 -8000184c: fec42783 lw a5,-20(s0) -80001850: 00279793 slli a5,a5,0x2 -80001854: fdc42703 lw a4,-36(s0) -80001858: 00f707b3 add a5,a4,a5 -8000185c: 0007a783 lw a5,0(a5) -80001860: 00078513 mv a0,a5 -80001864: fadfe0ef jal ra,80000810 +8000184c: fe042623 sw zero,-20(s0) +80001850: 0580006f j 800018a8 +80001854: fec42783 lw a5,-20(s0) +80001858: 00078e63 beqz a5,80001874 +8000185c: fec42783 lw a5,-20(s0) +80001860: 00f7f793 andi a5,a5,15 +80001864: 00079863 bnez a5,80001874 80001868: 810007b7 lui a5,0x81000 -8000186c: 14078513 addi a0,a5,320 # 81000140 +8000186c: 13c78513 addi a0,a5,316 # 8100013c 80001870: f65fe0ef jal ra,800007d4 80001874: fec42783 lw a5,-20(s0) -80001878: 00178793 addi a5,a5,1 -8000187c: fef42623 sw a5,-20(s0) -80001880: fec42703 lw a4,-20(s0) -80001884: 0ff00793 li a5,255 -80001888: fae7d2e3 bge a5,a4,8000182c -8000188c: 810007b7 lui a5,0x81000 -80001890: 14478513 addi a0,a5,324 # 81000144 -80001894: f41fe0ef jal ra,800007d4 -80001898: 00000013 nop -8000189c: 02c12083 lw ra,44(sp) -800018a0: 02812403 lw s0,40(sp) -800018a4: 03010113 addi sp,sp,48 -800018a8: 00008067 ret +80001878: 00279793 slli a5,a5,0x2 +8000187c: fdc42703 lw a4,-36(s0) +80001880: 00f707b3 add a5,a4,a5 +80001884: 0007a783 lw a5,0(a5) +80001888: 00078513 mv a0,a5 +8000188c: f85fe0ef jal ra,80000810 +80001890: 810007b7 lui a5,0x81000 +80001894: 14078513 addi a0,a5,320 # 81000140 +80001898: f3dfe0ef jal ra,800007d4 +8000189c: fec42783 lw a5,-20(s0) +800018a0: 00178793 addi a5,a5,1 +800018a4: fef42623 sw a5,-20(s0) +800018a8: fec42703 lw a4,-20(s0) +800018ac: 0ff00793 li a5,255 +800018b0: fae7d2e3 bge a5,a4,80001854 +800018b4: 810007b7 lui a5,0x81000 +800018b8: 14478513 addi a0,a5,324 # 81000144 +800018bc: f19fe0ef jal ra,800007d4 +800018c0: 00000013 nop +800018c4: 02c12083 lw ra,44(sp) +800018c8: 02812403 lw s0,40(sp) +800018cc: 03010113 addi sp,sp,48 +800018d0: 00008067 ret -800018ac
: -800018ac: ff010113 addi sp,sp,-16 -800018b0: 00112623 sw ra,12(sp) -800018b4: 00812423 sw s0,8(sp) -800018b8: 01010413 addi s0,sp,16 -800018bc: ed5ff0ef jal ra,80001790 -800018c0: 810267b7 lui a5,0x81026 -800018c4: 21c78513 addi a0,a5,540 # 8102621c -800018c8: f3dff0ef jal ra,80001804 -800018cc: 00000793 li a5,0 -800018d0: 00078513 mv a0,a5 -800018d4: 00c12083 lw ra,12(sp) -800018d8: 00812403 lw s0,8(sp) -800018dc: 01010113 addi sp,sp,16 -800018e0: 00008067 ret +800018d4
: +800018d4: ff010113 addi sp,sp,-16 +800018d8: 00812623 sw s0,12(sp) +800018dc: 01010413 addi s0,sp,16 +800018e0: 00000793 li a5,0 +800018e4: 00078513 mv a0,a5 +800018e8: 00c12403 lw s0,12(sp) +800018ec: 01010113 addi sp,sp,16 +800018f0: 00008067 ret Disassembly of section .rodata: @@ -1720,7 +1726,7 @@ Disassembly of section .rodata: 8100002a: 0000 unimp 8100002c: 0062 c.slli zero,0x18 8100002e: 0000 unimp -81000030: 00000063 beqz zero,81000030 +81000030: 00000063 beqz zero,81000030 81000034: 0064 addi s1,sp,12 81000036: 0000 unimp 81000038: 0065 c.nop 25 @@ -1757,7 +1763,7 @@ Disassembly of section .rodata: 8100007e: 0000 unimp 81000080: 0062 c.slli zero,0x18 81000082: 0000 unimp -81000084: 00000063 beqz zero,81000084 +81000084: 00000063 beqz zero,81000084 81000088: 0064 addi s1,sp,12 8100008a: 0000 unimp 8100008c: 0065 c.nop 25 @@ -1788,7 +1794,7 @@ Disassembly of section .rodata: 810000c2: 0000 unimp 810000c4: 0062 c.slli zero,0x18 810000c6: 0000 unimp -810000c8: 00000063 beqz zero,810000c8 +810000c8: 00000063 beqz zero,810000c8 810000cc: 0064 addi s1,sp,12 810000ce: 0000 unimp 810000d0: 0065 c.nop 25 @@ -1817,7 +1823,7 @@ Disassembly of section .rodata: 81000102: 0000 unimp 81000104: 0062 c.slli zero,0x18 81000106: 0000 unimp -81000108: 00000063 beqz zero,81000108 +81000108: 00000063 beqz zero,81000108 8100010c: 0064 addi s1,sp,12 8100010e: 0000 unimp 81000110: 0065 c.nop 25 diff --git a/kernel/vortex_test.elf b/kernel/vortex_test.elf index 996387d49ab2d374698f06a5ff48130e43ba9afa..6c907e0e028fad5986c8f37aaebfcb5d837efb4e 100755 GIT binary patch delta 945 zcmYk4OK1~O7={0NW#XevY-(Cc784ulEF!)ZO-Lw}229jN6p9qoq_s)}tHs1ebdfv0 z5G~U7intJq;KGf9MyxJ`O0yJnk)4Hh;l@=f4J8Xf&xA{724?R4?m6?nW*X%uH>VBh z?o7B>YjhJe-eu-}2G4!3~|GO;D`ei%Hd5?d3z z7fjF#f(O8Lyq^}FmMaK=icL{b7KT^{u~UN2fM4lO!i(V0ZD%5vzPw!Vqy)SO+h-68;81aPbCsa4Ru}Kz2t83ihk$=(OBQ zsDYcV3G{&Tn)6Ab;BTFq6Fxu*96WdZ0~tHOcIPJ<21n8HYjj{I+{3^0r#$1=uN_Sv z=6cNX3?ICDIiBK=V_DDslOyF5S^g__zO8sRSGq89E>|p#PE1xa@gbQ%Oa!F{f04vYeJ)&S_e#dwD%y(X@u5uI1XqtLR;p`6UL7 z?K>B1qtVh|@gPdRXz5Q;U8B+GDg|z!W|FA@f1!=|W%{r8LWjWPPW%&CV+--LqdxyYjDUCK@+w%~;PN`yWW+x?2?A*7qD;K%aHriMbkpG&cmdxZaCjfsM8gL1 z*aP>lJW;%b_;JTEh=8Z6Tks?}bkp5P7OWv*$w_z~ob?QF1B{2;FT21MJKjeYj`fY+ z0xx*-r}93c*-h?B#}FWU0(OBX+o3xNhhamP+=d=Q|2@Pk9e(?lO@K@Hn1y;^gTOPp; + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void Vrf2_32x128_wm1::__Vconfigure(Vrf2_32x128_wm1__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vrf2_32x128_wm1::~Vrf2_32x128_wm1() { + delete __VlSymsp; __VlSymsp=NULL; +} + +//-------------------- + + +void Vrf2_32x128_wm1::eval() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vrf2_32x128_wm1::eval\n"); ); + Vrf2_32x128_wm1__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void Vrf2_32x128_wm1::_eval_initial_loop(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + _eval_settle(vlSymsp); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +//-------------------- +// Internal Methods + +VL_INLINE_OPT void Vrf2_32x128_wm1::_combo__TOP__1(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_combo__TOP__1\n"); ); + Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // ALWAYS at rf2_32x128_wm1.v:15356 + if ((1U & (((~ (IData)(vlTOPp->CEN)) & (~ (IData)(vlTOPp->DFTRAMBYP))) + & (~ (IData)(vlTOPp->SE))))) { + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = 0U; + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i = 0U; + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[0U] + = vlTOPp->Q_in[0U]; + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[1U] + = vlTOPp->Q_in[1U]; + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[2U] + = vlTOPp->Q_in[2U]; + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[3U] + = vlTOPp->Q_in[3U]; + while ((1U & (~ (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete)))) { + vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry + = vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_table + [(0xfU & vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i)]; + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address + = (0xfU & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry + >> 0xdU)); + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address + = (1U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry + >> 0xcU)); + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace + = (0x7fU & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry + >> 5U)); + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type + = (3U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry + >> 3U)); + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault + = (3U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry + >> 1U)); + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid + = (1U & vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry); + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i + = ((IData)(1U) + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i); + if (vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid) { + if ((0U == (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault))) { + if ((((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address) + == (0xfU & ((IData)(vlTOPp->A) + >> 1U))) & ((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address) + == + (1U + & (IData)(vlTOPp->A))))) { + if ((0x40U > (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace))) { + // Function: bit_error at rf2_32x128_wm1.v:15345 + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc + = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace; + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type + = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type; + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc) + >> 5U)] + = (((~ ((IData)(1U) + << (0x1fU & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc)))) + & vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[ + ((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc) + >> 5U)]) | (((0U + != (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type)) + & ((1U + == (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type)) + | (~ + (vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[ + ((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc) + >> 5U)] + >> + (0x1fU + & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc)))))) + << + (0x1fU + & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc)))); + } else { + if ((0x40U <= (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace))) { + // Function: bit_error at rf2_32x128_wm1.v:15347 + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc + = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace; + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type + = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type; + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc) + >> 5U)] + = (((~ ((IData)(1U) + << (0x1fU + & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc)))) + & vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[ + ((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc) + >> 5U)]) | + (((0U != (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type)) + & ((1U == (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type)) + | (~ (vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[ + ((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc) + >> 5U)] + >> + (0x1fU + & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc)))))) + << (0x1fU & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc)))); + } + } + } + } + } else { + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = 1U; + } + } + vlTOPp->Q_out[0U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[0U]; + vlTOPp->Q_out[1U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[1U]; + vlTOPp->Q_out[2U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[2U]; + vlTOPp->Q_out[3U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[3U]; + } else { + vlTOPp->Q_out[0U] = vlTOPp->Q_in[0U]; + vlTOPp->Q_out[1U] = vlTOPp->Q_in[1U]; + vlTOPp->Q_out[2U] = vlTOPp->Q_in[2U]; + vlTOPp->Q_out[3U] = vlTOPp->Q_in[3U]; + } +} + +void Vrf2_32x128_wm1::_eval(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval\n"); ); + Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_combo__TOP__1(vlSymsp); +} + +void Vrf2_32x128_wm1::_eval_initial(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval_initial\n"); ); + Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void Vrf2_32x128_wm1::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::final\n"); ); + // Variables + Vrf2_32x128_wm1__Syms* __restrict vlSymsp = this->__VlSymsp; + Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void Vrf2_32x128_wm1::_eval_settle(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval_settle\n"); ); + Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_combo__TOP__1(vlSymsp); +} + +VL_INLINE_OPT QData Vrf2_32x128_wm1::_change_request(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_change_request\n"); ); + Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void Vrf2_32x128_wm1::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((CLK & 0xfeU))) { + Verilated::overWidthError("CLK");} + if (VL_UNLIKELY((A & 0xe0U))) { + Verilated::overWidthError("A");} + if (VL_UNLIKELY((CEN & 0xfeU))) { + Verilated::overWidthError("CEN");} + if (VL_UNLIKELY((DFTRAMBYP & 0xfeU))) { + Verilated::overWidthError("DFTRAMBYP");} + if (VL_UNLIKELY((SE & 0xfeU))) { + Verilated::overWidthError("SE");} +} +#endif // VL_DEBUG + +void Vrf2_32x128_wm1::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_ctor_var_reset\n"); ); + // Body + VL_RAND_RESET_W(128,Q_out); + VL_RAND_RESET_W(128,Q_in); + CLK = VL_RAND_RESET_I(1); + A = VL_RAND_RESET_I(5); + CEN = VL_RAND_RESET_I(1); + DFTRAMBYP = VL_RAND_RESET_I(1); + SE = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + rf2_32x128_wm1_error_injection__DOT__fault_table[__Vi0] = VL_RAND_RESET_I(17); + }} + rf2_32x128_wm1_error_injection__DOT__fault_entry = VL_RAND_RESET_I(17); + VL_RAND_RESET_W(128,__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output); + __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = VL_RAND_RESET_I(1); + __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i = VL_RAND_RESET_I(32); + __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address = VL_RAND_RESET_I(4); + __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address = VL_RAND_RESET_I(1); + __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace = VL_RAND_RESET_I(7); + __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type = VL_RAND_RESET_I(2); + __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault = VL_RAND_RESET_I(2); + __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid = VL_RAND_RESET_I(1); + __Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type = VL_RAND_RESET_I(2); + __Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc = VL_RAND_RESET_I(7); + __Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type = VL_RAND_RESET_I(2); + __Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc = VL_RAND_RESET_I(7); +} diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.h b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.h new file mode 100644 index 00000000..c4ae029a --- /dev/null +++ b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.h @@ -0,0 +1,101 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _Vrf2_32x128_wm1_H_ +#define _Vrf2_32x128_wm1_H_ + +#include "verilated.h" + +class Vrf2_32x128_wm1__Syms; + +//---------- + +VL_MODULE(Vrf2_32x128_wm1) { + public: + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + // Begin mtask footprint all: + VL_IN8(CLK,0,0); + VL_IN8(A,4,0); + VL_IN8(CEN,0,0); + VL_IN8(DFTRAMBYP,0,0); + VL_IN8(SE,0,0); + VL_OUTW(Q_out,127,0,4); + VL_INW(Q_in,127,0,4); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + // Begin mtask footprint all: + VL_SIG(rf2_32x128_wm1_error_injection__DOT__fault_entry,16,0); + VL_SIG(rf2_32x128_wm1_error_injection__DOT__fault_table[16],16,0); + + // LOCAL VARIABLES + // Internals; generally not touched by application code + // Begin mtask footprint all: + VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete,0,0); + VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address,3,0); + VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address,0,0); + VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace,6,0); + VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type,1,0); + VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault,1,0); + VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid,0,0); + VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type,1,0); + VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc,6,0); + VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type,1,0); + VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc,6,0); + VL_SIGW(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output,127,0,4); + VL_SIG(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i,31,0); + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + Vrf2_32x128_wm1__Syms* __VlSymsp; // Symbol table + + // PARAMETERS + // Parameters marked /*verilator public*/ for use by application code + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(Vrf2_32x128_wm1); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible with respect to DPI scope names. + Vrf2_32x128_wm1(const char* name="TOP"); + /// Destroy the model; called (often implicitly) by application code + ~Vrf2_32x128_wm1(); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval(); + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + private: + static void _eval_initial_loop(Vrf2_32x128_wm1__Syms* __restrict vlSymsp); + public: + void __Vconfigure(Vrf2_32x128_wm1__Syms* symsp, bool first); + private: + static QData _change_request(Vrf2_32x128_wm1__Syms* __restrict vlSymsp); + public: + static void _combo__TOP__1(Vrf2_32x128_wm1__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset() VL_ATTR_COLD; + public: + static void _eval(Vrf2_32x128_wm1__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _eval_settle(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) VL_ATTR_COLD; +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.mk b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.mk new file mode 100644 index 00000000..2f138e59 --- /dev/null +++ b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.mk @@ -0,0 +1,53 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f Vrf2_32x128_wm1.mk + +default: Vrf2_32x128_wm1__ALL.a + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/local/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = Vrf2_32x128_wm1 +# Module prefix (from --prefix) +VM_MODPREFIX = Vrf2_32x128_wm1 +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + + +### Default rules... +# Include list of all generated classes +include Vrf2_32x128_wm1_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +# Verilated -*- Makefile -*- diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.cpp b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.cpp new file mode 100644 index 00000000..ef09ff5f --- /dev/null +++ b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.cpp @@ -0,0 +1,19 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "Vrf2_32x128_wm1__Syms.h" +#include "Vrf2_32x128_wm1.h" + +// FUNCTIONS +Vrf2_32x128_wm1__Syms::Vrf2_32x128_wm1__Syms(Vrf2_32x128_wm1* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_didInit(false) + // Setup submodule names +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); +} diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.h b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.h new file mode 100644 index 00000000..f77ac3fb --- /dev/null +++ b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.h @@ -0,0 +1,35 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header, +// unless using verilator public meta comments. + +#ifndef _Vrf2_32x128_wm1__Syms_H_ +#define _Vrf2_32x128_wm1__Syms_H_ + +#include "verilated.h" + +// INCLUDE MODULE CLASSES +#include "Vrf2_32x128_wm1.h" + +// SYMS CLASS +class Vrf2_32x128_wm1__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_didInit; + + // SUBCELL STATE + Vrf2_32x128_wm1* TOPp; + + // CREATORS + Vrf2_32x128_wm1__Syms(Vrf2_32x128_wm1* topp, const char* namep); + ~Vrf2_32x128_wm1__Syms() {} + + // METHODS + inline const char* name() { return __Vm_namep; } + +} VL_ATTR_ALIGNED(64); + +#endif // guard diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__ver.d b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__ver.d new file mode 100644 index 00000000..00d3baae --- /dev/null +++ b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__ver.d @@ -0,0 +1 @@ +obj_dir/Vrf2_32x128_wm1.cpp obj_dir/Vrf2_32x128_wm1.h obj_dir/Vrf2_32x128_wm1.mk obj_dir/Vrf2_32x128_wm1__Syms.cpp obj_dir/Vrf2_32x128_wm1__Syms.h obj_dir/Vrf2_32x128_wm1__ver.d obj_dir/Vrf2_32x128_wm1_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin rf2_32x128_wm1.v diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__verFiles.dat b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__verFiles.dat new file mode 100644 index 00000000..925e8fe6 --- /dev/null +++ b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__verFiles.dat @@ -0,0 +1,12 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "-cc rf2_32x128_wm1.v" +S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin" +T 14325 1013347 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1.cpp" +T 4125 1013346 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1.h" +T 1478 1013349 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1.mk" +T 570 1013345 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__Syms.cpp" +T 817 1013344 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__Syms.h" +T 292 1013350 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__ver.d" +T 0 0 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__verFiles.dat" +T 1269 1013348 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1_classes.mk" +S 1252191 1011852 1571096122 0 1571096122 0 "rf2_32x128_wm1.v" diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1_classes.mk b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1_classes.mk new file mode 100644 index 00000000..a8a44681 --- /dev/null +++ b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1_classes.mk @@ -0,0 +1,40 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See Vrf2_32x128_wm1.mk for the caller. + +### Switches... +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace) +VM_TRACE = 0 +# Tracing threadeds output mode? 0/1 (from --trace-fst-thread) +VM_TRACE_THREADED = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + Vrf2_32x128_wm1 \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + Vrf2_32x128_wm1__Syms \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v b/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v index ddae1b27..aefa3087 100644 --- a/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v +++ b/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v @@ -56,6 +56,12 @@ `define ARM_MEM_HOLD 0.500 `define ARM_MEM_COLLISION 3.000 +`define REALTIME 1 + +`undef POWER_PINS +`undef ARM_MESSAGES +/* verilator lint_off UNUSED */ + module datapath_latch_rf2_32x128_wm1 (CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ,Q); input CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ; output Q; @@ -77,7 +83,7 @@ module datapath_latch_rf2_32x128_wm1 (CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ // model output side of RAM latch always @(posedge Q_update or posedge XQ) begin - #0; + //#0; if (XQ===1'b0) begin if (DFTRAMBYP===1'b1) Q=D_int; @@ -97,7 +103,7 @@ endmodule // datapath_latch_rf2_32x128_wm1 // ARM_UD_DP Defines the delay through Data Paths, for Memory Models it represents BIST MUX output delays. `ifdef ARM_UD_DP `else -`define ARM_UD_DP #0.001 +`define ARM_UD_DP //#0.001 `endif // ARM_UD_CP Defines the delay through Clock Path Cells, for Memory Models it is not used. `ifdef ARM_UD_CP @@ -107,7 +113,7 @@ endmodule // datapath_latch_rf2_32x128_wm1 // ARM_UD_SEQ Defines the delay through the Memory, for Memory Models it is used for CLK->Q delays. `ifdef ARM_UD_SEQ `else -`define ARM_UD_SEQ #0.01 +`define ARM_UD_SEQ //#0.01 `endif `celldefine @@ -1125,23 +1131,23 @@ module rf2_32x128_wm1 (CENYA, AYA, CENYB, WENYB, AYB, QA, SOA, SOB, CLKA, CENA, `ifdef INITIALIZE_MEMORY integer i; initial begin - #0; + //#0; for (i = 0; i < MEM_HEIGHT; i = i + 1) mem[i] = {MEM_WIDTH{1'b0}}; end `endif - always @ (EMAA_) begin - if(EMAA_ < 3) - $display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", $time); - end - always @ (EMASA_) begin - if(EMASA_ < 0) - $display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", $time); - end - always @ (EMAB_) begin - if(EMAB_ < 3) - $display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", $time); - end + // always @ (EMAA_) begin + // if(EMAA_ < 3) + // //$display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", 0); + // end + // always @ (EMASA_) begin + // if(EMASA_ < 0) + // //$display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", 0); + // end + // always @ (EMAB_) begin + // if(EMAB_ < 3) + // //$display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", 0); + // end task failedWrite; input port_f; @@ -1262,7 +1268,7 @@ task dumpmem; reg [BITS-1:0] wordtemp; reg [4:0] Atemp; begin - dump_file_desc = $fopen(filename_dump); + dump_file_desc = $fopen(filename_dump, "w"); if (CENA_ === 1'b1 && CENB_ === 1'b1) begin for (i=0;i tb_debug.h - verilator --compiler gcc -Wall -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3 + verilator --compiler gcc -Wno-fatal -Wno-UNOPTFLAT -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-lint -cc Vortex.v -I. -I../models/memory/cln28hpc/rf2_32x128_wm1/ -I/usr/local/systemc/ -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS '-std=c++11 -O3' -LDFLAGS '-L/usr/local/systemc/' compdebug: echo "#define VCD_OUTPUT" > tb_debug.h - verilator --compiler gcc --prof-cfuncs -DVL_DEBUG=1 --coverage -Wall --trace -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS '-std=c++11 -DVL_DEBUG' + verilator --compiler gcc -Wno-fatal -Wno-UNOPTFLAT -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-lint --prof-cfuncs -DVL_DEBUG=1 --coverage --trace -cc Vortex.v -I/usr/local/systemc/ -I. -I../models/memory/cln28hpc/rf2_32x128_wm1/ -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS '-std=c++11 -DVL_DEBUG' -LDFLAGS '-L/usr/local/systemc/' RUNFILE: VERILATOR (cd obj_dir && make -j -f VVortex.mk) diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v index a030697e..d14b82b8 100644 --- a/rtl/VX_decode.v +++ b/rtl/VX_decode.v @@ -33,9 +33,7 @@ module VX_decode( assign VX_frE_to_bckE_req.curr_PC = in_curr_PC; - wire in_valid[`NT_M1:0]; - genvar index; - for (index = 0; index <= `NT_M1; index = index + 1) assign in_valid[index] = fd_inst_meta_de.valid[index]; + wire[`NT_M1:0] in_valid = fd_inst_meta_de.valid; wire[6:0] curr_opcode; diff --git a/rtl/VX_gpr.v b/rtl/VX_gpr.v index fee1d1dc..25bfe6b3 100644 --- a/rtl/VX_gpr.v +++ b/rtl/VX_gpr.v @@ -55,7 +55,11 @@ module VX_gpr ( // .q1 (out_b_reg_data) // ); + wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}}; + // Port A is a read port, Port B is a write port + + /* verilator lint_off PINCONNECTEMPTY */ rf2_32x128_wm1 first_ram ( .CENYA(), .AYA(), @@ -70,7 +74,7 @@ module VX_gpr ( .AA(VX_gpr_read.rs1), .CLKB(clk), .CENB(1'b0), - .WENB({32{~(VX_writeback_inter.wb_valid[3])}, 32{~(VX_writeback_inter.wb_valid[2])}, 32{~(VX_writeback_inter.wb_valid[1])}, 32{~(VX_writeback_inter.wb_valid[0])}}), + .WENB(write_bit_mask), .AB(VX_writeback_inter.rd), .DB(VX_writeback_inter.write_data), .EMAA(3'b011), @@ -92,7 +96,9 @@ module VX_gpr ( .SEB(1'b0), .COLLDISN(1'b1) ); + /* verilator lint_on PINCONNECTEMPTY */ + /* verilator lint_off PINCONNECTEMPTY */ rf2_32x128_wm1 second_ram ( .CENYA(), .AYA(), @@ -107,7 +113,7 @@ module VX_gpr ( .AA(VX_gpr_read.rs2), .CLKB(clk), .CENB(1'b0), - .WENB({32{~(VX_writeback_inter.wb_valid[3])}, 32{~(VX_writeback_inter.wb_valid[2])}, 32{~(VX_writeback_inter.wb_valid[1])}, 32{~(VX_writeback_inter.wb_valid[0])}}), + .WENB(write_bit_mask), .AB(VX_writeback_inter.rd), .DB(VX_writeback_inter.write_data), .EMAA(3'b011), @@ -129,6 +135,7 @@ module VX_gpr ( .SEB(1'b0), .COLLDISN(1'b1) ); + /* verilator lint_on PINCONNECTEMPTY */ // >>>>>>> 5680b997b599ce2900997cab976681fe3881e880 diff --git a/rtl/VX_gpr_stage.v b/rtl/VX_gpr_stage.v index 343c718f..d1fa8e58 100644 --- a/rtl/VX_gpr_stage.v +++ b/rtl/VX_gpr_stage.v @@ -26,8 +26,10 @@ module VX_gpr_stage ( ); - // wire[31:0] curr_PC = VX_bckE_req.curr_PC; - // wire[2:0] branchType = VX_bckE_req.branch_type; + wire[31:0] curr_PC = VX_bckE_req.curr_PC; + wire[2:0] branchType = VX_bckE_req.branch_type; + + wire jalQual = VX_bckE_req.jalQual; assign VX_fwd_req_de.src1 = VX_bckE_req.rs1; diff --git a/rtl/byte_enabled_simple_dual_port_ram.v b/rtl/byte_enabled_simple_dual_port_ram.v index 863a5cd2..db2187ad 100644 --- a/rtl/byte_enabled_simple_dual_port_ram.v +++ b/rtl/byte_enabled_simple_dual_port_ram.v @@ -5,10 +5,10 @@ module byte_enabled_simple_dual_port_ram ( input we, clk, - input wire[4:0] waddr, raddr1, + input wire[4:0] waddr, raddr1, raddr2, input wire[`NT_M1:0] be, input wire[`NT_M1:0][31:0] wdata, - output reg[`NT_M1:0][31:0] q1 + output reg[`NT_M1:0][31:0] q1, q2 ); // integer regi; @@ -42,7 +42,7 @@ module byte_enabled_simple_dual_port_ram end assign q1 = GPR[raddr1]; - + assign q2 = GPR[raddr2]; // assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1]; // assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2]; diff --git a/rtl/results.txt b/rtl/results.txt index 58fd6b93..d7d36007 100644 --- a/rtl/results.txt +++ b/rtl/results.txt @@ -1,7 +1,7 @@ -# Dynamic Instructions: 58157 -# of total cycles: 58172 +# Dynamic Instructions: 13 +# of total cycles: 24 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.00026 -# time to simulate: 2.18459e-314 milliseconds +# CPI: 1.84615 +# time to simulate: 6.95312e-310 milliseconds # GRADE: Failed on test: 4294967295 diff --git a/rtl/tb_debug.h b/rtl/tb_debug.h index 711663cc..6aae22b3 100644 --- a/rtl/tb_debug.h +++ b/rtl/tb_debug.h @@ -1 +1 @@ -#define VCD_OFF +#define VCD_OUTPUT diff --git a/rtl/test_bench.h b/rtl/test_bench.h index 984a000a..95ad0559 100644 --- a/rtl/test_bench.h +++ b/rtl/test_bench.h @@ -376,7 +376,7 @@ bool Vortex::simulate(std::string file_to_simulate) // while (this->stats_total_cycles < 10) { // std::cout << "Counter: " << counter << "\n"; - // std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n"; + if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n"; // dstop = !dbus_driver(); vortex->clk = 1;