Merge remote-tracking branch 'upstream/master'

ci/prebuilt.sh

@@ -23,17 +23,17 @@ riscv()
 llvm() 
 {
     echo "prebuilt llvm-riscv..."
-    tar -C $SRCDIR -cvjf llvm-riscv.tar.bz2 llvm-riscv
-    split -b 50M llvm-riscv.tar.bz2 "llvm-riscv.tar.bz2.part"    
-    mv llvm-riscv.tar.bz2.part* $DESTDIR/llvm-riscv/$OS_DIR
-    rm llvm-riscv.tar.bz2
+    tar -C $SRCDIR -cvjf llvm-vortex1.tar.bz2 llvm-riscv
+    split -b 50M llvm-vortex1.tar.bz2 "llvm-vortex1.tar.bz2.part"    
+    mv llvm-vortex1.tar.bz2.part* $DESTDIR/llvm-vortex/$OS_DIR
+    rm llvm-vortex1.tar.bz2
 }
 
 pocl() 
 {
     echo "prebuilt pocl..."
-    tar -C $SRCDIR -cvjf pocl.tar.bz2 pocl
-    mv pocl.tar.bz2 $DESTDIR/pocl/$OS_DIR
+    tar -C $SRCDIR -cvjf pocl1.tar.bz2 pocl
+    mv pocl1.tar.bz2 $DESTDIR/pocl/$OS_DIR
 }
 
 verilator() 

ci/toolchain_install.sh

@@ -9,7 +9,7 @@ DESTDIR="${DESTDIR:=/opt}"
 
 riscv()
 {
-    for x in {a..o} 
+    for x in {a..j} 
     do
         wget $REPOSITORY/riscv-gnu-toolchain/ubuntu/bionic/riscv-gnu-toolchain.tar.bz2.parta$x
     done
@@ -37,20 +37,20 @@ llvm()
 {
     for x in {a..b} 
     do
-        wget $REPOSITORY/llvm-riscv/ubuntu/bionic/llvm-riscv.tar.bz2.parta$x
+        wget $REPOSITORY/llvm-vortex/ubuntu/bionic/llvm-vortex1.tar.bz2.parta$x
     done
-    cat llvm-riscv.tar.bz2.parta* > llvm-riscv.tar.bz2
-    tar -xvf llvm-riscv.tar.bz2
-    rm -f llvm-riscv.tar.bz2*
+    cat llvm-vortex1.tar.bz2.parta* > llvm-vortex1.tar.bz2
+    tar -xvf llvm-vortex1.tar.bz2
+    rm -f llvm-vortex1.tar.bz2*
     cp -r llvm-riscv $DESTDIR
     rm -rf llvm-riscv
 }
 
 pocl()
 {
-    wget $REPOSITORY/pocl/ubuntu/bionic/pocl.tar.bz2
-    tar -xvf pocl.tar.bz2
-    rm -f pocl.tar.bz2
+    wget $REPOSITORY/pocl/ubuntu/bionic/pocl1.tar.bz2
+    tar -xvf pocl1.tar.bz2
+    rm -f pocl1.tar.bz2
     cp -r pocl $DESTDIR
     rm -rf pocl
 }

ci/travis_run.py

@@ -23,12 +23,14 @@ def execute(command):
     process = subprocess.Popen(command, stdout=subprocess.PIPE)
     while True:
         output = process.stdout.readline()
-        if output == '' and process.poll() is not None:
-            break
         if output:
-            print output.strip()
-            sys.stdout.flush()
-    return process.returncode
+            line = output.decode('ascii').rstrip()
+            print(">>> " + line)
+            process.stdout.flush()
+        ret = process.poll()
+        if ret is not None:
+            return ret        
+    return -1
 
 def main(argv):
 

hw/rtl/cache/VX_core_req_bank_sel.sv

@@ -93,6 +93,7 @@ module VX_core_req_bank_sel #(
             
             always @(*) begin
                 per_bank_line_addr_r = 'x;
+                per_bank_rw_r = 'x;
                 for (integer i = NUM_REQS-1; i >= 0; --i) begin                                    
                     if (core_req_valid[i]) begin
                         per_bank_line_addr_r[core_req_bid[i]] = core_req_line_addr[i];

sim/rtlsim/Makefile

@@ -44,7 +44,7 @@ endif
 
 VL_FLAGS = --exe --cc $(TOP) --top-module $(TOP)
 VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic
-VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO
+VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO -Wno-EOFNEWLINE
 VL_FLAGS += --x-initial unique --x-assign unique
 VL_FLAGS += verilator.vlt
 VL_FLAGS += $(RTL_INCLUDE)

sim/rtlsim/processor.cpp

@@ -462,7 +462,7 @@ private:
           }
           printf("\n");
         */
-        memcpy((uint8_t*)device_->mem_rsp_data, mem_req->block.data(), MEM_BLOCK_SIZE);
+        memcpy(device_->mem_rsp_data.data(), mem_req->block.data(), MEM_BLOCK_SIZE);
         device_->mem_rsp_tag = mem_req->tag;   
         pending_mem_reqs_.erase(mem_rsp_it);
         mem_rd_rsp_active_ = true;
@@ -478,7 +478,7 @@ private:
       if (device_->mem_req_rw) {        
         // process writes
         uint64_t byteen = device_->mem_req_byteen;        
-        uint8_t* data = (uint8_t*)(device_->mem_req_data);
+        uint8_t* data = (uint8_t*)device_->mem_req_data.data();
 
         // check console output
         if (byte_addr >= IO_COUT_ADDR 

sim/vlsim/Makefile

@@ -41,7 +41,7 @@ TOP = vortex_afu_shim
 
 VL_FLAGS = --exe --cc $(TOP) --top-module $(TOP)
 VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic
-VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO
+VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO -Wno-EOFNEWLINE
 VL_FLAGS += --x-initial unique --x-assign unique
 VL_FLAGS += verilator.vlt
 VL_FLAGS += $(RTL_INCLUDE)

sim/vlsim/opae_sim.cpp

@@ -399,7 +399,7 @@ private:
       unsigned byte_addr = device_->avs_address[b] * MEM_BLOCK_SIZE;
       if (device_->avs_write[b]) {           
         uint64_t byteen = device_->avs_byteenable[b];        
-        uint8_t* data = (uint8_t*)(device_->avs_writedata[b]);
+        uint8_t* data = (uint8_t*)device_->avs_writedata[b].data();
         for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
           if ((byteen >> i) & 0x1) {            
             (*ram_)[byte_addr + i] = data[i];

tests/regression/diverge/Makefile

@@ -11,7 +11,7 @@ VX_CXX = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-g++
 VX_DP  = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objdump
 VX_CP  = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objcopy
 
-VX_CFLAGS += -march=rv32imf -mabi=ilp32f -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections
+VX_CFLAGS += -march=rv32imf -mabi=ilp32f -O1 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections
 VX_CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw
 
 VX_LDFLAGS += -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link$(XLEN).ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a