From 8d20b52ea2027b9b326ea5ca5dcc0f5693125004 Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Tue, 4 Feb 2020 10:54:25 -0500 Subject: [PATCH] Cleanup imports of VX_define --- rtl/VX_generic_priority_encoder.v | 2 +- rtl/VX_priority_encoder_w_mask.v | 2 +- rtl/VX_warp.v | 4 ++-- rtl/Vortex.v | 2 +- rtl/cache/VX_Cache_Bank.v | 2 +- rtl/cache/VX_cache_bank_valid.v | 2 +- rtl/cache/VX_cache_data.v | 2 +- rtl/cache/VX_cache_data_per_index.v | 2 +- rtl/cache/VX_d_cache.v | 2 +- rtl/cache/VX_d_cache_encapsulate.v | 2 +- rtl/interfaces/VX_frE_to_bckE_req_inter.v | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) diff --git a/rtl/VX_generic_priority_encoder.v b/rtl/VX_generic_priority_encoder.v index 6bef1a4f..b1fa2966 100644 --- a/rtl/VX_generic_priority_encoder.v +++ b/rtl/VX_generic_priority_encoder.v @@ -1,4 +1,4 @@ -`include "../VX_define.v" +`include "VX_define.v" module VX_generic_priority_encoder #( diff --git a/rtl/VX_priority_encoder_w_mask.v b/rtl/VX_priority_encoder_w_mask.v index fcd9d865..cba23415 100644 --- a/rtl/VX_priority_encoder_w_mask.v +++ b/rtl/VX_priority_encoder_w_mask.v @@ -1,4 +1,4 @@ -`include "../VX_define.v" +`include "VX_define.v" module VX_priority_encoder_w_mask #( parameter N = 10 diff --git a/rtl/VX_warp.v b/rtl/VX_warp.v index 21d72cb9..345d5bcd 100644 --- a/rtl/VX_warp.v +++ b/rtl/VX_warp.v @@ -20,8 +20,8 @@ module VX_warp ( ); reg[31:0] real_PC; - var[31:0] temp_PC; - var[31:0] use_PC; + logic [31:0] temp_PC; + logic [31:0] use_PC; reg[`NT_M1:0] valid; reg[`NT_M1:0] valid_zero; diff --git a/rtl/Vortex.v b/rtl/Vortex.v index ff60245d..d70b88f6 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -1,5 +1,5 @@ -`include "../VX_define.v" +`include "VX_define.v" module Vortex diff --git a/rtl/cache/VX_Cache_Bank.v b/rtl/cache/VX_Cache_Bank.v index 10415601..b3701b68 100644 --- a/rtl/cache/VX_Cache_Bank.v +++ b/rtl/cache/VX_Cache_Bank.v @@ -2,7 +2,7 @@ // Also add a bit about wheter the "Way ID" is valid / being held or if it is just default // Also make sure all possible output states are transmitted back to the bank correctly -`include "../VX_define.v" +`include "VX_define.v" // `include "VX_cache_data.v" diff --git a/rtl/cache/VX_cache_bank_valid.v b/rtl/cache/VX_cache_bank_valid.v index 48759b77..21dbb71b 100644 --- a/rtl/cache/VX_cache_bank_valid.v +++ b/rtl/cache/VX_cache_bank_valid.v @@ -1,4 +1,4 @@ -`include "../VX_define.v" +`include "VX_define.v" module VX_cache_bank_valid #( diff --git a/rtl/cache/VX_cache_data.v b/rtl/cache/VX_cache_data.v index 6b6c91b1..62c62bd9 100644 --- a/rtl/cache/VX_cache_data.v +++ b/rtl/cache/VX_cache_data.v @@ -1,6 +1,6 @@ -`include "../VX_define.v" +`include "VX_define.v" module VX_cache_data #( diff --git a/rtl/cache/VX_cache_data_per_index.v b/rtl/cache/VX_cache_data_per_index.v index 03b824ad..4fffd329 100644 --- a/rtl/cache/VX_cache_data_per_index.v +++ b/rtl/cache/VX_cache_data_per_index.v @@ -1,6 +1,6 @@ -`include "../VX_define.v" +`include "VX_define.v" module VX_cache_data_per_index #( diff --git a/rtl/cache/VX_d_cache.v b/rtl/cache/VX_d_cache.v index 808e360d..ccb266a8 100644 --- a/rtl/cache/VX_d_cache.v +++ b/rtl/cache/VX_d_cache.v @@ -8,7 +8,7 @@ // TO DO: // - Send in a response from memory of what the data is from the test bench -`include "../VX_define.v" +`include "VX_define.v" //`include "VX_priority_encoder.v" // `include "VX_Cache_Bank.v" //`include "cache_set.v" diff --git a/rtl/cache/VX_d_cache_encapsulate.v b/rtl/cache/VX_d_cache_encapsulate.v index d1badc8f..ca488152 100644 --- a/rtl/cache/VX_d_cache_encapsulate.v +++ b/rtl/cache/VX_d_cache_encapsulate.v @@ -1,7 +1,7 @@ `include "VX_define.v" -// `define NUM_WORDS_PER_BLOCK 4 +`define NUM_WORDS_PER_BLOCK 4 module VX_d_cache_encapsulate ( clk, diff --git a/rtl/interfaces/VX_frE_to_bckE_req_inter.v b/rtl/interfaces/VX_frE_to_bckE_req_inter.v index 610d3525..ba4ac9be 100644 --- a/rtl/interfaces/VX_frE_to_bckE_req_inter.v +++ b/rtl/interfaces/VX_frE_to_bckE_req_inter.v @@ -1,5 +1,5 @@ -`include "../VX_define.v" +`include "VX_define.v" `ifndef VX_FrE_to_BE_INTER