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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 14:05:08 -04:00
parent 1a2823da0d
commit 8e7046a388
15 changed files with 53 additions and 484 deletions
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15
hw/rtl/libs/VX_generic_stack.v
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@@ -1,10 +1,8 @@
module VX_generic_stack
#(
parameter WIDTH = 40,
parameter DEPTH = 2
)
(
module VX_generic_stack #(
parameter WIDTH = 40,
parameter DEPTH = 2
) (
input wire clk,
input wire reset,
input wire push,
@@ -12,8 +10,7 @@ module VX_generic_stack
input reg [WIDTH - 1:0] q1,
input reg [WIDTH - 1:0] q2,
output wire[WIDTH - 1:0] d
);
);
reg [DEPTH - 1:0] ptr;
reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
@@ -30,10 +27,8 @@ module VX_generic_stack
end else if (pop) begin
ptr <= ptr - 1;
end
end
assign d = stack[ptr - 1];
endmodule