From 956f3d1880f4efcc9f3376a6c31d7ea62cd21a7f Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 19 Oct 2021 16:32:31 -0400 Subject: [PATCH] docs update --- .../assets/img}/cache_hierarchy.png | Bin .../assets/img}/vortex_bank.png | Bin .../assets/img}/vortex_cache_top_module.png | Bin .../img}/vortex_microarchitecture_v2.png | Bin {doc => docs}/cache_subsystem.md | 6 +++--- {doc => docs}/codebase.md | 0 {doc => docs}/debugging.md | 0 {doc => docs}/execute_opencl_on_vortex.md | 0 {doc => docs}/fpga_setup.md | 20 +++++++++++------- doc/Vortex.md => docs/index.md | 6 +++--- {doc => docs}/microarchitecture.md | 2 +- {doc => docs}/references.md | 0 {doc => docs}/simulation.md | 0 {doc => docs}/software.md | 0 14 files changed, 19 insertions(+), 15 deletions(-) rename {doc/images => docs/assets/img}/cache_hierarchy.png (100%) rename {doc/images => docs/assets/img}/vortex_bank.png (100%) rename {doc/images => docs/assets/img}/vortex_cache_top_module.png (100%) rename {doc/images => docs/assets/img}/vortex_microarchitecture_v2.png (100%) rename {doc => docs}/cache_subsystem.md (91%) rename {doc => docs}/codebase.md (100%) rename {doc => docs}/debugging.md (100%) rename {doc => docs}/execute_opencl_on_vortex.md (100%) rename {doc => docs}/fpga_setup.md (85%) rename doc/Vortex.md => docs/index.md (73%) rename {doc => docs}/microarchitecture.md (97%) rename {doc => docs}/references.md (100%) rename {doc => docs}/simulation.md (100%) rename {doc => docs}/software.md (100%) diff --git a/doc/images/cache_hierarchy.png b/docs/assets/img/cache_hierarchy.png similarity index 100% rename from doc/images/cache_hierarchy.png rename to docs/assets/img/cache_hierarchy.png diff --git a/doc/images/vortex_bank.png b/docs/assets/img/vortex_bank.png similarity index 100% rename from doc/images/vortex_bank.png rename to docs/assets/img/vortex_bank.png diff --git a/doc/images/vortex_cache_top_module.png b/docs/assets/img/vortex_cache_top_module.png similarity index 100% rename from doc/images/vortex_cache_top_module.png rename to docs/assets/img/vortex_cache_top_module.png diff --git a/doc/images/vortex_microarchitecture_v2.png b/docs/assets/img/vortex_microarchitecture_v2.png similarity index 100% rename from doc/images/vortex_microarchitecture_v2.png rename to docs/assets/img/vortex_microarchitecture_v2.png diff --git a/doc/cache_subsystem.md b/docs/cache_subsystem.md similarity index 91% rename from doc/cache_subsystem.md rename to docs/cache_subsystem.md index 41d2fad6..1c03a326 100644 --- a/doc/cache_subsystem.md +++ b/docs/cache_subsystem.md @@ -8,7 +8,7 @@ The Vortex Cache Sub-system has the following main properties: ### Cache Hierarchy -![Image of Cache Hierarchy](./images/cache_hierarchy.png) +![Image of Cache Hierarchy](./assets/img/cache_hierarchy.png) - Cache can be configured to be any level in the hierarchy - Caches communicate via snooping @@ -18,7 +18,7 @@ The Vortex Cache Sub-system has the following main properties: VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/cache` directory. -![Image of Vortex Cache](./images/vortex_cache_top_module.png) +![Image of Vortex Cache](./assets/img/vortex_cache_top_module.png) - Configurable (Cache size, number of banks, bank line size, etc.) - I/O signals @@ -44,7 +44,7 @@ VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/c VX_bank.v is the verilog code that handles cache bank functionality and is located in the `/hw/rtl/cache` directory. -![Image of Vortex Cache Bank](./images/vortex_bank.png) +![Image of Vortex Cache Bank](./assets/img/vortex_bank.png) - Allows for high throughput​ - Each bank contains queues to hold requests to the cache​ diff --git a/doc/codebase.md b/docs/codebase.md similarity index 100% rename from doc/codebase.md rename to docs/codebase.md diff --git a/doc/debugging.md b/docs/debugging.md similarity index 100% rename from doc/debugging.md rename to docs/debugging.md diff --git a/doc/execute_opencl_on_vortex.md b/docs/execute_opencl_on_vortex.md similarity index 100% rename from doc/execute_opencl_on_vortex.md rename to docs/execute_opencl_on_vortex.md diff --git a/doc/fpga_setup.md b/docs/fpga_setup.md similarity index 85% rename from doc/fpga_setup.md rename to docs/fpga_setup.md index cbf06187..39e2084a 100644 --- a/doc/fpga_setup.md +++ b/docs/fpga_setup.md @@ -19,7 +19,7 @@ OPAE Build Configuration Within the `/hw/syn/opae` directory, there are source text files for each core-option for the fpga build (the 32 and 64 core options are not currently implemented) which have the following parameters that can be configured: - NUM_CORES: the number of cores per cluster - NUM_CLUSTERS: the number of clusters alotted to the processor -- L3_ENABLE: enable the use of the L3 cache +- L2_ENABLE: enable the use of the L2 cache - PERF_ENABLE: enable the use of all profile counters To enable L3 cache and profile counters for a build, simply uncomment the definition within the respective source file. @@ -33,41 +33,45 @@ The FPGA has to following configuration options: - 4 cores fpga (fpga-4c) - 8 cores fpga (fpga-8c) - 16 cores fpga (fpga-16c) +- 32 cores fpga (fpga-32c) +- 64 cores fpga (fpga-64c) + +Command line: $ cd hw/syn/opae - $ make fpga- *# of cores* c + $ make fpga-c Example: `make fpga-4c` -A new folder (ex: `build_fpga_4c`) will be created and the build will start and take ~30-45 min to complete. +A new folder (ex: `build_fpga_4c`) will be created and the build will start and take ~30-480 min to complete. OPAE Build Progress ------------------- You could check the last 10 lines in the build log for possible errors until build completion. - $ tail -n 10 ./build_fpga_4c/build.log + $ tail -n 10 ./build_fpga_c/build.log Check if the build is still running by looking for quartus_sh, quartus_syn, or quartus_fit programs. - $ ps -u *username* + $ ps -u If the build fails and you need to restart it, clean up the build folder using the following command: - $ make clean-fpga- *# of cores* c + $ make clean-fpga-c Example: `make clean-fpga-4c` The file `vortex_afu.gbs` should exist when the build is done: - $ ls -lsa ./build_fpga_ *# of cores* c/vortex_afu.gbs + $ ls -lsa ./build_fpga_c/vortex_afu.gbs Signing the bitstream and Programming the FPGA ---------------------------------------------- - $ cd ./build_fpga_`# of cores`c/ + $ cd ./build_fpga_c $ PACSign PR -t UPDATE -H openssl_manager -i vortex_afu.gbs -o vortex_afu_unsigned_ssl.gbs $ fpgasupdate vortex_afu_unsigned_ssl.gbs diff --git a/doc/Vortex.md b/docs/index.md similarity index 73% rename from doc/Vortex.md rename to docs/index.md index 3071e9f4..f7544b03 100644 --- a/doc/Vortex.md +++ b/docs/index.md @@ -21,10 +21,10 @@ Running Vortex simulators with different configurations: - Run basic driver test with rtlsim driver and Vortex config of 2 clusters, 2 cores, 2 warps, 4 threads - $ ./ci/blackbox.sh --clusters=2 --cores=2 --warps=2 --threads=4 --driver=rtlsim --app=basic + $ ./ci/blackbox.sh --driver=rtlsim --clusters=2 --cores=2 --warps=2 --threads=4 --app=basic - Run demo driver test with vlsim driver and Vortex config of 1 clusters, 4 cores, 4 warps, 2 threads - $ ./ci/blackbox.sh --clusters=1 --cores=4 --warps=4 --threads=2 --driver=vlsim --app=demo + $ ./ci/blackbox.sh --driver=vlsim --clusters=1 --cores=4 --warps=4 --threads=2 --app=demo - Run dogfood driver test with simx driver and Vortex config of 4 cluster, 4 cores, 8 warps, 6 threads - $ ./ci/blackbox.sh --clusters=4 --cores=4 --warps=8 --threads=6 --driver=simx --app=dogfood \ No newline at end of file + $ ./ci/blackbox.sh --driver=simx --clusters=4 --cores=4 --warps=8 --threads=6 --app=dogfood \ No newline at end of file diff --git a/doc/microarchitecture.md b/docs/microarchitecture.md similarity index 97% rename from doc/microarchitecture.md rename to docs/microarchitecture.md index 7e7a6a59..972da7b0 100644 --- a/doc/microarchitecture.md +++ b/docs/microarchitecture.md @@ -32,7 +32,7 @@ Vortex uses the SIMT (Single Instruction, Multiple Threads) execution model with ### Vortex Pipeline/Datapath -![Image of Vortex Microarchitecture](./images/vortex_microarchitecture_v2.png) +![Image of Vortex Microarchitecture](./assets/img/vortex_microarchitecture_v2.png) Vortex has a 5-stage pipeline: FI | ID | Issue | EX | WB. diff --git a/doc/references.md b/docs/references.md similarity index 100% rename from doc/references.md rename to docs/references.md diff --git a/doc/simulation.md b/docs/simulation.md similarity index 100% rename from doc/simulation.md rename to docs/simulation.md diff --git a/doc/software.md b/docs/software.md similarity index 100% rename from doc/software.md rename to docs/software.md