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VX_pipeline refactoring + logic analyzer

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Blaise Tine
2020-06-06 01:52:44 -04:00
parent 203ebb3445
commit 9ae38433fb
14 changed files with 609 additions and 198 deletions
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6
driver/rtlsim/Makefile
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@@ -19,7 +19,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
#DEBUG=1
#AFU=1
AFU=1
CFLAGS += -fPIC
@@ -55,8 +55,8 @@ endif
# AFU
ifdef AFU
TOP = vortex_afu_sim
VL_FLAGS += -DNOPAE
CFLAGS += -DNOPAE
VL_FLAGS += -DNOPAE -DSCOPE
CFLAGS += -DNOPAE -DSCOPE
RTL_INCLUDE += -I../../hw/opae -I../../hw/opae/ccip
endif