Finished Cache Integration
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felsabbagh3
196
rtl/cache/VX_Cache_Block_DM.v
vendored
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196
rtl/cache/VX_Cache_Block_DM.v
vendored
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// To Do: Change way_id_out to an internal register which holds when in between access and finished.
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// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default
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// Also make sure all possible output states are transmitted back to the bank correctly
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`include "VX_define.v"
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module VX_Cache_Block_DM(clk,
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rst,
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// These next 4 are possible modes that the Set could be in, I am making them 4 different variables for indexing purposes
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access, // First
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find_evict,
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write_from_mem,
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idle,
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// entry,
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o_tag,
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block_offset,
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writedata,
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//byte_en,
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write,
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fetched_writedata,
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//word_en,
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//way_id_in,
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//way_id_out,
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readdata,
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//wb_addr,
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hit,
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eviction_wb,
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eviction_tag,
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evicted_data,
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//modify,
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miss
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//valid_data
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//read_miss
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);
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parameter cache_entry = 14;
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parameter ways_per_set = 4;
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parameter Number_Blocks = 32;
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input wire clk, rst;
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input wire access;
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input wire find_evict;
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input wire write_from_mem;
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input wire idle;
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//input wire [cache_entry-1:0] entry;
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input wire [21:0] o_tag;
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input wire [4:0] block_offset;
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input wire [31:0] writedata;
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//input wire [3:0] byte_en;
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input wire write; // 0 == False
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input wire [31:0][31:0] fetched_writedata;
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//input wire [3:0] word_en;
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//input wire read_miss;
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//input wire [1:0] way_id_in;
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//output reg [1:0] way_id_out;
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//output reg [31:0] readdata;
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output wire [31:0] readdata;
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//output reg hit;
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output wire hit;
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output reg miss;
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output wire eviction_wb;
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output wire [21:0] eviction_tag;
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output wire [31:0][31:0] evicted_data;
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//reg [31:0] eviction_data;
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//output wire [22:0] wb_addr;
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//output wire modify, valid_data;
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//wire [2:0] i_tag;
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//wire dirty;
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//wire [24-cache_entry:0] write_tag_data;
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// Table for one set
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//reg [2:0] counter; // Determines which to evict
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reg valid;
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reg [21:0] tag;
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reg clean;
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//reg [31:0] data[31:0];
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reg [31:0] data[31:0];
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integer j;
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// WS AW BS
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//reg[3:0][31:0] some_data[5:0]; // before variable name is width, after name is height
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//wire blockNun;
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//wire WordNumWIthinABlock;
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//ddata[31:0] =some_data[blockNun][WordNumWIthinABlock]
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assign eviction_wb = miss && clean != 1'b1 && valid == 1'b1;
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assign eviction_tag = tag;
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assign readdata = (access && !write && tag == o_tag && valid) ? data[0] : 32'b0; // Fix with actual data
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assign hit = (access && !write && tag == o_tag && valid) ? 1'b1 : 1'b0;
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//assign evicted_data = (eviction_wb ) ? data : 0;
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genvar k;
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for (k = 0; k < Number_Blocks; k = k + 1) begin
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assign evicted_data[k] = (eviction_wb) ? data[k] : 32'b0;
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//data[j] <= fetched_writedata[(j+1) * 32 - 1 -: 32];
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end
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//assign eviction_data = data[counter[1:0]];
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//assign hit = valid_data && (o_tag == i_tag);
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//assign modify = valid_data && (o_tag != i_tag) && dirty;
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//assign miss = !valid_data || ((o_tag != i_tag) && !dirty);
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//assign wb_addr = {i_tag, entry};
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always @(posedge clk) begin
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if (rst) begin
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end
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if (find_evict) begin
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if (tag == o_tag && valid) begin
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//readdata <= data;
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// evicted_data <= data;
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end
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end else if (access) begin
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// Hit in First Column
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if (tag == o_tag && valid) begin
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if (write == 1'b0) begin // if it is a read
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if (clean == 1'b1 ) begin
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//hit <= 1'b1;
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//readdata <= data;
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miss <= 1'b0;
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end else begin
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//hit <= 1'b0;
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//readdata <= 32'b0;
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miss <= 1'b1;
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end
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end else if (write == 1'b1) begin
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//for (j = 0; j < Number_Blocks; j = j + 1) begin
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//data[j] <= fetched_writedata[(j+1) * 32 - 1 -: 32];
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//end
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data[block_offset] <= writedata;
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clean <= 1'b0;
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//hit <= 1'b1;
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end
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end
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// Miss
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else begin
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//way_id_out <= counter;
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miss <= 1'b1;
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if (write == 1'b0) begin // Read Miss
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clean <= 1'b1;
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//data <= 0; // FIX WITH ACTUAL MEMORY ACCESS
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for (j = 0; j < Number_Blocks; j = j + 1) begin
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data[j] <= 32'b0;
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end
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end else if (write == 1'b1) begin // Write Miss
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clean <= 1'b1;
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data[block_offset] <= writedata;
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//for (j = 0; j < Number_Blocks; j = j + 1) begin
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//data[j] <= fetched_writedata[(j+1) * 32 - 1 -: 32];
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//end
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end
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end
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end
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if (write_from_mem) begin
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tag <= o_tag;
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valid <= 1'b1;
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//hit <= 1'b1;
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if (write == 1'b0) begin // Read Miss
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clean <= 1'b1;
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//data <= 0; // FIX WITH ACTUAL MEMORY ACCESS
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for (j = 0; j < Number_Blocks; j = j + 1) begin
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data[j] <= 32'b0;
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end
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end else if (write == 1'b1) begin // Write Miss
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clean <= 1'b0;
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//data <= fetched_writedata;
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for (j = 0; j < Number_Blocks; j = j + 1) begin
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//data[j] <= fetched_writedata[(j+1) * 32 - 1 -: 32];
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data[j] <= fetched_writedata[j];
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end
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end
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end
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if (idle) begin // Set "way" register equal to invalid value
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//hit <= 1'b1; // set to know it is ready
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miss <= 1'b0;
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//readdata <= 32'hFFFFFFFF;
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end
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if (find_evict) begin // Keep "way" value the same !!!! Fix. Need to send back data with matching tag. Also need to ensure evicted data doesnt get lost
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if (tag == o_tag && valid) begin
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//readdata <= data;
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end
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//hit <= 1'b1;
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miss <= 1'b0;
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end
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//eviction_data <= data;
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end
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endmodule
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