diff --git a/rtl/pipe_regs/VX_d_e_reg.v b/rtl/pipe_regs/VX_d_e_reg.v
index c3e8f8ee..e25a0d88 100644
--- a/rtl/pipe_regs/VX_d_e_reg.v
+++ b/rtl/pipe_regs/VX_d_e_reg.v
@@ -18,7 +18,7 @@ module VX_d_e_reg (
 		wire flush = (in_branch_stall == `STALL);
 
 
-	VX_generic_register #(.N(240)) d_e_reg 
+	VX_generic_register #(.N(233 + `NW_M1 + 1 + `NT)) d_e_reg 
 	(
 		.clk  (clk),
 		.reset(reset),
diff --git a/rtl/pipe_regs/VX_f_d_reg.v b/rtl/pipe_regs/VX_f_d_reg.v
index dd69e196..0d5d99a8 100644
--- a/rtl/pipe_regs/VX_f_d_reg.v
+++ b/rtl/pipe_regs/VX_f_d_reg.v
@@ -14,8 +14,7 @@ module VX_f_d_reg (
 	wire stall = in_freeze == 1'b1;
 
 
-
-	VX_generic_register #(.N(71)) f_d_reg 
+	VX_generic_register #(.N(64 + `NW_M1 + 1 + `NT)) f_d_reg 
 	(
 		.clk  (clk),
 		.reset(reset),