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minor typo

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This commit is contained in:
Blaise Tine
2021-02-28 01:58:41 -08:00
parent 8a9a67aa5a
commit 9fda618815
1 changed files with 1 additions and 1 deletions
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driver/common/vx_utils.cpp
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@@ -213,7 +213,7 @@ extern int vx_dump_perf(vx_device_h device, FILE* stream) {
uint64_t dcache_miss_w_per_core; uint64_t dcache_miss_w_per_core;
ret |= vx_csr_get_l(device, core_id, CSR_MPM_DCACHE_MISS_W, CSR_MPM_DCACHE_MISS_W_H, &dcache_miss_w_per_core); ret |= vx_csr_get_l(device, core_id, CSR_MPM_DCACHE_MISS_W, CSR_MPM_DCACHE_MISS_W_H, &dcache_miss_w_per_core);
int dcache_write_hit_ratio = (int)((1.0 - (double(dcache_miss_w_per_core) / double(dcache_writes_per_core))) * 100); int dcache_write_hit_ratio = (int)((1.0 - (double(dcache_miss_w_per_core) / double(dcache_writes_per_core))) * 100);
if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache wrire misses=%ld (hit ratio=%d%%)\n", core_id, dcache_miss_w_per_core, dcache_write_hit_ratio); if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache write misses=%ld (hit ratio=%d%%)\n", core_id, dcache_miss_w_per_core, dcache_write_hit_ratio);
dcache_write_misses += dcache_miss_w_per_core; dcache_write_misses += dcache_miss_w_per_core;
// bank_stalls // bank_stalls
uint64_t dcache_bank_st_per_core; uint64_t dcache_bank_st_per_core;