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cache pipeline optimization

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This commit is contained in:
Blaise Tine
2021-01-17 17:19:52 -08:00
parent ed216ab39d
commit a046bd7a73
11 changed files with 129 additions and 166 deletions
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38
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -166,18 +166,18 @@ module VX_shared_mem #(
for (genvar i = 0; i < NUM_BANKS; i++) begin
VX_sp_ram #(
.DATAW(`WORD_WIDTH),
.SIZE(`LINES_PER_BANK),
.BYTEENW(WORD_SIZE),
.RWCHECK(1)
.DATAW (`WORD_WIDTH),
.SIZE (`LINES_PER_BANK),
.BYTEENW (WORD_SIZE),
.RWCHECK (1)
) data (
.clk(clk),
.addr(per_bank_core_req_addr[i]),
.wren(per_bank_core_req_valid[i] && per_bank_core_req_rw[i] && ~crsq_full),
.byteen(per_bank_core_req_byteen[i]),
.rden(1'b1),
.din(per_bank_core_req_data[i]),
.dout(per_bank_core_rsp_data[i])
.clk (clk),
.addr (per_bank_core_req_addr[i]),
.wren (per_bank_core_req_valid[i] && per_bank_core_req_rw[i] && ~crsq_full),
.byteen (per_bank_core_req_byteen[i]),
.rden (1'b1),
.din (per_bank_core_req_data[i]),
.dout (per_bank_core_rsp_data[i])
);
end
@@ -220,14 +220,14 @@ module VX_shared_mem #(
.BUFFERED (1),
.FASTRAM (1)
) core_rsp_queue (
.clk (clk),
.reset (reset),
.push (crsq_push),
.pop (crsq_pop),
.data_in ({core_rsp_valid_unqual, core_rsp_data_unqual, core_rsp_tag_unqual}),
.data_out({core_rsp_valid_tmask, core_rsp_data, core_rsp_tag}),
.empty (crsq_empty),
.full (crsq_full),
.clk (clk),
.reset (reset),
.push (crsq_push),
.pop (crsq_pop),
.data_in ({core_rsp_valid_unqual, core_rsp_data_unqual, core_rsp_tag_unqual}),
.data_out ({core_rsp_valid_tmask, core_rsp_data, core_rsp_tag}),
.empty (crsq_empty),
.full (crsq_full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (size)