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cache pipeline optimization

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This commit is contained in:
Blaise Tine
2021-01-17 17:19:52 -08:00
parent ed216ab39d
commit a046bd7a73
11 changed files with 129 additions and 166 deletions
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36
hw/rtl/libs/VX_fifo_queue.v
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@@ -1,14 +1,14 @@
`include "VX_platform.vh"
module VX_fifo_queue #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY= 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter BUFFERED = 0,
parameter FASTRAM = 1
parameter DATAW = 1,
parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter BUFFERED = 0,
parameter FASTRAM = 1
) (
input wire clk,
input wire reset,
@@ -111,11 +111,11 @@ module VX_fifo_queue #(
end
VX_dp_ram #(
.DATAW(DATAW),
.SIZE(SIZE),
.BUFFERED(0),
.RWCHECK(1),
.FASTRAM(FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),
@@ -156,11 +156,11 @@ module VX_fifo_queue #(
end
VX_dp_ram #(
.DATAW(DATAW),
.SIZE(SIZE),
.BUFFERED(0),
.RWCHECK(1),
.FASTRAM(FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),