diff --git a/.travis.yml b/.travis.yml index b07f5f45..54ecc638 100644 --- a/.travis.yml +++ b/.travis.yml @@ -54,7 +54,7 @@ jobs: script: cp -r $PWD ../build_tex && cd ../build_tex && ./ci/travis_run.py ./ci/regression.sh -tex - stage: test name: unittest - script: cp -r $PWD ../build_coverage && cd ../build_unittest && ./ci/travis_run.py ./ci/regression.sh -unittest + script: cp -r $PWD ../build_unittest && cd ../build_unittest && ./ci/travis_run.py ./ci/regression.sh -unittest after_success: # Gather code coverage diff --git a/ci/regression.sh b/ci/regression.sh index 6976b4e3..37eb33b6 100755 --- a/ci/regression.sh +++ b/ci/regression.sh @@ -144,8 +144,8 @@ FPU_CORE=FPU_DEFAULT CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driv FPU_CORE=FPU_DEFAULT CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr -CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=printf -CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=printf +CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --app=printf +CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --app=printf echo "stress0 tests done!" } diff --git a/driver/common/opae.cpp b/driver/common/opae.cpp index 1022639e..4246f4fb 100755 --- a/driver/common/opae.cpp +++ b/driver/common/opae.cpp @@ -50,6 +50,8 @@ #define MMIO_DEV_CAPS (AFU_IMAGE_MMIO_DEV_CAPS * 4) #define MMIO_STATUS (AFU_IMAGE_MMIO_STATUS * 4) +#define STATUS_STATE_BITS 8 + /////////////////////////////////////////////////////////////////////////////// class vx_device { @@ -373,7 +375,7 @@ extern int vx_ready_wait(vx_device_h hdevice, uint64_t timeout) { if (nullptr == hdevice) return -1; - std::unordered_map print_bufs; + std::unordered_map print_bufs; vx_device *device = ((vx_device*)hdevice); @@ -394,11 +396,13 @@ extern int vx_ready_wait(vx_device_h hdevice, uint64_t timeout) { uint64_t status; CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_STATUS, &status)); - uint16_t cout_data = (status >> 8) & 0xffff; - if (cout_data & 0x0001) { + // check for console data + uint32_t cout_data = status >> STATUS_STATE_BITS; + if (cout_data & 0x1) { + // retrieve console data do { char cout_char = (cout_data >> 1) & 0xff; - int cout_tid = (cout_data >> 9) & 0xff; + uint32_t cout_tid = (cout_data >> 9) & 0xff; auto& ss_buf = print_bufs[cout_tid]; ss_buf << cout_char; if (cout_char == '\n') { @@ -406,11 +410,11 @@ extern int vx_ready_wait(vx_device_h hdevice, uint64_t timeout) { ss_buf.str(""); } CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_STATUS, &status)); - cout_data = (status >> 8) & 0xffff; - } while (cout_data & 0x0001); + cout_data = status >> STATUS_STATE_BITS; + } while (cout_data & 0x1); } - uint8_t state = status & 0xff; + uint32_t state = status & ((1 << STATUS_STATE_BITS)-1); if (0 == state || 0 == timeout) { for (auto& buf : print_bufs) { diff --git a/hw/rtl/VX_alu_unit.sv b/hw/rtl/VX_alu_unit.sv index 72d36184..d4a79d46 100644 --- a/hw/rtl/VX_alu_unit.sv +++ b/hw/rtl/VX_alu_unit.sv @@ -223,7 +223,7 @@ module VX_alu_unit #( // can accept new request? assign alu_req_if.ready = ready_in; -`ifdef DBG_TRACE_PIPELINE +`ifdef DBG_TRACE_CORE_PIPELINE always @(posedge clk) begin if (branch_ctl_if.valid) begin dpi_trace("%d: core%0d-branch: wid=%0d, PC=%0h, taken=%b, dest=%0h (#%0d)\n", diff --git a/hw/rtl/VX_commit.sv b/hw/rtl/VX_commit.sv index 574ed36e..ef8ecc98 100644 --- a/hw/rtl/VX_commit.sv +++ b/hw/rtl/VX_commit.sv @@ -93,7 +93,7 @@ module VX_commit #( // store and gpu commits don't writeback assign st_commit_if.ready = 1'b1; -`ifdef DBG_TRACE_PIPELINE +`ifdef DBG_TRACE_CORE_PIPELINE always @(posedge clk) begin if (alu_commit_if.valid && alu_commit_if.ready) begin dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.wb, alu_commit_if.rd); diff --git a/hw/rtl/VX_decode.sv b/hw/rtl/VX_decode.sv index 3f9af431..e6646a32 100644 --- a/hw/rtl/VX_decode.sv +++ b/hw/rtl/VX_decode.sv @@ -1,5 +1,5 @@ `include "VX_define.vh" -`ifdef DBG_TRACE_PIPELINE +`ifdef DBG_TRACE_CORE_PIPELINE `include "VX_trace_instr.vh" `endif @@ -479,7 +479,7 @@ module VX_decode #( assign perf_decode_if.branches = perf_branches; `endif -`ifdef DBG_TRACE_PIPELINE +`ifdef DBG_TRACE_CORE_PIPELINE always @(posedge clk) begin if (decode_if.valid && decode_if.ready) begin dpi_trace("%d: core%0d-decode: wid=%0d, PC=%0h, ex=", $time, CORE_ID, decode_if.wid, decode_if.PC); diff --git a/hw/rtl/VX_issue.sv b/hw/rtl/VX_issue.sv index e20f5fce..4abedc63 100644 --- a/hw/rtl/VX_issue.sv +++ b/hw/rtl/VX_issue.sv @@ -204,7 +204,7 @@ module VX_issue #( `endif `endif -`ifdef DBG_TRACE_PIPELINE +`ifdef DBG_TRACE_CORE_PIPELINE always @(posedge clk) begin if (alu_req_if.valid && alu_req_if.ready) begin dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=ALU, tmask=%b, rd=%0d, rs1_data=", diff --git a/hw/rtl/VX_lsu_unit.sv b/hw/rtl/VX_lsu_unit.sv index 85cec545..5116035f 100644 --- a/hw/rtl/VX_lsu_unit.sv +++ b/hw/rtl/VX_lsu_unit.sv @@ -310,7 +310,7 @@ module VX_lsu_unit #( `ifndef SYNTHESIS reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + `UUID_BITS + 64 + 1)-1:0] pending_reqs; - wire [63:0] delay_timeout = 40000 * (1 ** (`L2_ENABLE + `L3_ENABLE)); + wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE)); always @(posedge clk) begin if (reset) begin diff --git a/hw/rtl/VX_scoreboard.sv b/hw/rtl/VX_scoreboard.sv index 9a3fed37..b4422d28 100644 --- a/hw/rtl/VX_scoreboard.sv +++ b/hw/rtl/VX_scoreboard.sv @@ -58,7 +58,7 @@ module VX_scoreboard #( if (reset) begin deadlock_ctr <= 0; end else begin - `ifdef DBG_TRACE_PIPELINE + `ifdef DBG_TRACE_CORE_PIPELINE if (ibuffer_if.valid && ~ibuffer_if.ready) begin dpi_trace("%d: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b (#%0d)\n", $time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb, diff --git a/hw/rtl/Vortex.sv b/hw/rtl/Vortex.sv index 96b5602b..c97f6bcf 100644 --- a/hw/rtl/Vortex.sv +++ b/hw/rtl/Vortex.sv @@ -201,7 +201,7 @@ module Vortex ( `SCOPE_ASSIGN (mem_rsp_tag, mem_rsp_tag); `SCOPE_ASSIGN (busy, busy); -`ifdef DBG_TRACE_MEM +`ifdef DBG_TRACE_CORE_MEM always @(posedge clk) begin if (mem_req_valid && mem_req_ready) begin if (mem_req_rw) diff --git a/hw/rtl/afu/VX_avs_wrapper.sv b/hw/rtl/afu/VX_avs_wrapper.sv index 755cdf05..c9aaf0e7 100644 --- a/hw/rtl/afu/VX_avs_wrapper.sv +++ b/hw/rtl/afu/VX_avs_wrapper.sv @@ -158,7 +158,7 @@ module VX_avs_wrapper #( .ready_out (mem_rsp_ready) ); -`ifdef DBG_TRACE_AVS +`ifdef DBG_TRACE_AFU always @(posedge clk) begin if (mem_req_valid && mem_req_ready) begin if (mem_req_rw) begin diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index 22d1ec29..7ef76233 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -187,36 +187,36 @@ always @(posedge clk) begin case (mmio_hdr.address) MMIO_IO_ADDR: begin cmd_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data); - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: MMIO_IO_ADDR: addr=%0h, data=0x%0h\n", $time, mmio_hdr.address, t_ccip_clAddr'(cp2af_sRxPort.c0.data)); `endif end MMIO_MEM_ADDR: begin cmd_mem_addr <= $bits(cmd_mem_addr)'(cp2af_sRxPort.c0.data); - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: MMIO_MEM_ADDR: addr=%0h, data=0x%0h\n", $time, mmio_hdr.address, $bits(cmd_mem_addr)'(cp2af_sRxPort.c0.data)); `endif end MMIO_DATA_SIZE: begin cmd_data_size <= $bits(cmd_data_size)'(cp2af_sRxPort.c0.data); - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: MMIO_DATA_SIZE: addr=%0h, data=%0d\n", $time, mmio_hdr.address, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); `endif end MMIO_CMD_TYPE: begin - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: MMIO_CMD_TYPE: addr=%0h, data=%0d\n", $time, mmio_hdr.address, $bits(cmd_type)'(cp2af_sRxPort.c0.data)); `endif end `ifdef SCOPE MMIO_SCOPE_WRITE: begin - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: MMIO_SCOPE_WRITE: addr=%0h, data=%0h\n", $time, mmio_hdr.address, 64'(cp2af_sRxPort.c0.data)); `endif end `endif default: begin - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: Unknown MMIO Wr: addr=%0h, data=%0h\n", $time, mmio_hdr.address, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); `endif end @@ -243,7 +243,7 @@ always @(posedge clk) begin 16'h0008: mmio_tx.data <= 64'h0; // reserved MMIO_STATUS: begin mmio_tx.data <= 64'({cout_q_dout, !cout_q_empty, 8'(state)}); - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU if (state != STATE_WIDTH'(mmio_tx.data)) begin dpi_trace("%d: MMIO_STATUS: addr=%0h, state=%0d\n", $time, mmio_hdr.address, state); end @@ -252,20 +252,20 @@ always @(posedge clk) begin `ifdef SCOPE MMIO_SCOPE_READ: begin mmio_tx.data <= cmd_scope_rdata; - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: MMIO_SCOPE_READ: addr=%0h, data=%0h\n", $time, mmio_hdr.address, cmd_scope_rdata); `endif end `endif MMIO_DEV_CAPS: begin mmio_tx.data <= dev_caps; - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: MMIO_DEV_CAPS: addr=%0h, data=%0h\n", $time, mmio_hdr.address, dev_caps); `endif end default: begin mmio_tx.data <= 64'h0; - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: Unknown MMIO Rd: addr=%0h\n", $time, mmio_hdr.address); `endif end @@ -299,19 +299,19 @@ always @(posedge clk) begin STATE_IDLE: begin case (cmd_type) CMD_MEM_READ: begin - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: STATE READ: ia=%0h addr=%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); `endif state <= STATE_READ; end CMD_MEM_WRITE: begin - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: STATE WRITE: ia=%0h addr=%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); `endif state <= STATE_WRITE; end CMD_RUN: begin - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: STATE START\n", $time); `endif vx_reset <= 1; @@ -326,7 +326,7 @@ always @(posedge clk) begin STATE_READ: begin if (cmd_read_done) begin state <= STATE_IDLE; - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: STATE IDLE\n", $time); `endif end @@ -335,7 +335,7 @@ always @(posedge clk) begin STATE_WRITE: begin if (cmd_write_done) begin state <= STATE_IDLE; - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: STATE IDLE\n", $time); `endif end @@ -347,7 +347,7 @@ always @(posedge clk) begin if (cmd_run_done) begin vx_started <= 0; state <= STATE_IDLE; - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: STATE IDLE\n", $time); `endif end @@ -701,7 +701,7 @@ always @(posedge clk) begin if (cci_rd_req_fire) begin cci_rd_req_addr <= cci_rd_req_addr + 1; cci_rd_req_ctr <= cci_rd_req_ctr + 1; - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: CCI Rd Req: addr=%0h, tag=%0h, rem=%0d, pending=%0d\n", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr - 1), cci_pending_reads); `endif end @@ -711,13 +711,13 @@ always @(posedge clk) begin if (CCI_RD_QUEUE_TAGW'(cci_rd_rsp_ctr) == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin cci_mem_wr_req_addr_base <= cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE); end - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: CCI Rd Rsp: idx=%0d, ctr=%0d, data=%0h\n", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, cp2af_sRxPort.c0.data); `endif end if (cci_rdq_pop) begin - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: CCI Rd Queue Pop: pending=%0d\n", $time, cci_pending_reads); `endif end @@ -858,13 +858,13 @@ begin if (cci_wr_req_ctr == CCI_ADDR_WIDTH'(1)) begin cci_wr_req_done <= 1; end - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: CCI Wr Req: addr=%0h, rem=%0d, pending=%0d, data=%0h\n", $time, cci_wr_req_addr, (cci_wr_req_ctr - 1), cci_pending_writes, af2cp_sTxPort.c1.data); `endif end if (cci_wr_rsp_fire) begin - `ifdef DBG_TRACE_OPAE + `ifdef DBG_TRACE_AFU dpi_trace("%d: CCI Wr Rsp: pending=%0d\n", $time, cci_pending_writes); `endif end diff --git a/hw/syn/opae/Makefile b/hw/syn/opae/Makefile index 29b6a922..891ca1e4 100644 --- a/hw/syn/opae/Makefile +++ b/hw/syn/opae/Makefile @@ -9,16 +9,15 @@ else endif # control RTL debug tracing states -DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA -DBG_TRACE_FLAGS += -DDBG_TRACE_MEM -DBG_TRACE_FLAGS += -DDBG_TRACE_OPAE -DBG_TRACE_FLAGS += -DDBG_TRACE_AVS +DBG_TRACE_FLAGS += -DDBG_TRACE_AFU DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE DBG_TRACE_FLAGS += -DDBG_TRACE_TEX diff --git a/hw/unit_tests/cache/Makefile b/hw/unit_tests/cache/Makefile index 96c2e9f1..e23b4898 100644 --- a/hw/unit_tests/cache/Makefile +++ b/hw/unit_tests/cache/Makefile @@ -1,16 +1,17 @@ PARAMS += -DCACHE_SIZE=4096 -DCACHE_WORD_SIZE=4 -DCACHE_LINE_SIZE=16 -DCACHE_NUM_BANKS=4 -DCACHE_CREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 # control RTL debug tracing states -DBG_TRACE_FLAGS = -DDBG_TRACE_CORE_ICACHE \ - -DDBG_TRACE_CORE_DCACHE \ - -DDBG_TRACE_CACHE_BANK \ - -DDBG_TRACE_CACHE_SNP \ - -DDBG_TRACE_CACHE_MSHR \ - -DDBG_TRACE_CACHE_TAG \ - -DDBG_TRACE_CACHE_DATA \ - -DDBG_TRACE_MEM \ - -DDBG_TRACE_OPAE \ - -DDBG_TRACE_AVS +DBG_TRACE_FLAGS = -DDBG_TRACE_CORE_PIPELINE \ + -DDBG_TRACE_CORE_ICACHE \ + -DDBG_TRACE_CORE_DCACHE \ + -DDBG_TRACE_CORE_MEM \ + -DDBG_TRACE_CACHE_BANK \ + -DDBG_TRACE_CACHE_SNP \ + -DDBG_TRACE_CACHE_MSHR \ + -DDBG_TRACE_CACHE_TAG \ + -DDBG_TRACE_CACHE_DATA \ + -DDBG_TRACE_AFU + #DBG_PRINT=$(DBG_TRACE_FLAGS) diff --git a/sim/rtlsim/Makefile b/sim/rtlsim/Makefile index 50c032c1..75a0da27 100644 --- a/sim/rtlsim/Makefile +++ b/sim/rtlsim/Makefile @@ -13,16 +13,15 @@ LDFLAGS += ../$(THIRD_PARTY_DIR)/softfloat/build/Linux-x86_64-GCC/softfloat.a LDFLAGS += -L../$(THIRD_PARTY_DIR)/ramulator -lramulator # control RTL debug tracing states -DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA -DBG_TRACE_FLAGS += -DDBG_TRACE_MEM -DBG_TRACE_FLAGS += -DDBG_TRACE_OPAE -DBG_TRACE_FLAGS += -DDBG_TRACE_AVS +DBG_TRACE_FLAGS += -DDBG_TRACE_AFU DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE DBG_TRACE_FLAGS += -DDBG_TRACE_TEX diff --git a/sim/rtlsim/processor.cpp b/sim/rtlsim/processor.cpp index 284d599f..0838c0ad 100644 --- a/sim/rtlsim/processor.cpp +++ b/sim/rtlsim/processor.cpp @@ -357,7 +357,7 @@ private: // check console output if (base_addr >= IO_COUT_ADDR - && base_addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) { + && base_addr < (IO_COUT_ADDR + IO_COUT_SIZE)) { for (int i = 0; i < MEM_BLOCK_SIZE; i++) { if ((byteen >> i) & 0x1) { auto& ss_buf = print_bufs_[i]; @@ -482,7 +482,7 @@ private: // check console output if (byte_addr >= IO_COUT_ADDR - && byte_addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) { + && byte_addr < (IO_COUT_ADDR + IO_COUT_SIZE)) { for (int i = 0; i < IO_COUT_SIZE; i++) { if ((byteen >> i) & 0x1) { auto& ss_buf = print_bufs_[i]; diff --git a/sim/simx/core.cpp b/sim/simx/core.cpp index 5b9e7a4d..4face7ec 100644 --- a/sim/simx/core.cpp +++ b/sim/simx/core.cpp @@ -419,7 +419,7 @@ Word Core::dcache_read(Addr addr, Size size) { void Core::dcache_write(Addr addr, Word data, Size size) { if (addr >= IO_COUT_ADDR - && addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) { + && addr < (IO_COUT_ADDR + IO_COUT_SIZE)) { this->writeToStdOut(addr, data); } else { auto type = get_addr_type(addr, size); diff --git a/sim/vlsim/Makefile b/sim/vlsim/Makefile index 663c764e..3358c664 100644 --- a/sim/vlsim/Makefile +++ b/sim/vlsim/Makefile @@ -14,16 +14,15 @@ LDFLAGS += -shared ../$(THIRD_PARTY_DIR)/softfloat/build/Linux-x86_64-GCC/softfl LDFLAGS += -L../$(THIRD_PARTY_DIR)/ramulator -lramulator # control RTL debug tracing states -DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA -DBG_TRACE_FLAGS += -DDBG_TRACE_MEM -DBG_TRACE_FLAGS += -DDBG_TRACE_OPAE -DBG_TRACE_FLAGS += -DDBG_TRACE_AVS +DBG_TRACE_FLAGS += -DDBG_TRACE_AFU DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE DBG_TRACE_FLAGS += -DDBG_TRACE_TEX @@ -58,7 +57,7 @@ VL_FLAGS += -j $(THREADS) # Debugigng ifdef DEBUG VL_FLAGS += --trace --trace-structs -DVCD_OUTPUT $(DBG_FLAGS) - #CXXFLAGS += -g -O0 -DVCD_OUTPUT $(DBG_FLAGS) + CXXFLAGS += -g -O0 -DVCD_OUTPUT $(DBG_FLAGS) else VL_FLAGS += -DNDEBUG CXXFLAGS += -O2 -DNDEBUG diff --git a/sim/vlsim/opae_sim.cpp b/sim/vlsim/opae_sim.cpp index ff632bf4..17bcbb2e 100644 --- a/sim/vlsim/opae_sim.cpp +++ b/sim/vlsim/opae_sim.cpp @@ -122,7 +122,7 @@ public: #ifdef VCD_OUTPUT Verilated::traceEverOn(true); trace_ = new VerilatedVcdC(); - device_->trace(this->trace, 99); + device_->trace(trace_, 99); trace_->open("trace.vcd"); #endif diff --git a/tests/regression/printf/kernel.c b/tests/regression/printf/kernel.c index ac2037c4..44f3b23a 100644 --- a/tests/regression/printf/kernel.c +++ b/tests/regression/printf/kernel.c @@ -6,7 +6,8 @@ void kernel_body(int task_id, kernel_arg_t* arg) { int* src_ptr = (int*)arg->src_addr; - vx_printf("task=%d, value=%d\n", task_id, src_ptr[task_id]); + char value = 'A' + src_ptr[task_id]; + vx_printf("task=%d, value=%c\n", task_id, value); } void main() { diff --git a/tests/regression/printf/main.cpp b/tests/regression/printf/main.cpp index 9eb13b4e..5d9bb2f0 100644 --- a/tests/regression/printf/main.cpp +++ b/tests/regression/printf/main.cpp @@ -126,9 +126,9 @@ int main(int argc, char *argv[]) { // upload source buffer0 { - auto buf_ptr = (float*)vx_host_ptr(staging_buf); + auto buf_ptr = (int*)vx_host_ptr(staging_buf); for (uint32_t i = 0; i < num_points; ++i) { - buf_ptr[i] = i-1; + buf_ptr[i] = i; } } std::cout << "upload source buffer" << std::endl;