RTL code refactoring
This commit is contained in:
Blaise Tine
@@ -1,160 +0,0 @@
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`timescale 1ns/1ps
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module VX_tb_divide();
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`ifdef TRACE
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initial
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begin
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$dumpfile("trace.vcd");
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$dumpvars(0,test);
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end
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`endif
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reg clk;
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reg rst;
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reg [31:0] numer, denom;
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wire [31:0] o_div[0:7], o_rem[0:7];
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genvar i;
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generate
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for (i = 0; i < 8; i = i+1) begin : div_loop
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VX_divide#(
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.WIDTHN(32),
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.WIDTHD(32),
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.PIPELINE(i)
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) div(
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.clock(clk),
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.aclr(rst),
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.clken(1'b1),
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.numer(numer),
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.denom(denom),
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.quotient(o_div[i]),
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.remainder(o_rem[i])
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);
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end
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endgenerate
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initial begin
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clk = 0; rst = 0;
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numer = 56;
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denom = 11;
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$display("56 / 11 #0");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[1] != 1'bx || o_rem[1] != 1'bx) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected x,x EXITING");
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$finish();
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end
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if (o_div[2] != 1'bx || o_rem[2] != 1'bx) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected x,x EXITING");
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$finish();
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end
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if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected x,x EXITING");
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$finish();
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end
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#2;
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$display("56 / 11 #2");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1, EXITING");
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$finish();
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end
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if (o_div[1] != 5 || o_rem[1] != 1) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[2] != 1'bx || o_rem[2] != 1'bx) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected x,x EXITING");
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$finish();
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end
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if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected x,x EXITING");
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$finish();
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end
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#2;
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$display("56 / 11 #4");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[1] != 5 || o_rem[1] != 1) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[2] != 5 || o_rem[2] != 1) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected x,x EXITING");
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$finish();
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end
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#2;
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$display("56 / 11 #6");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[1] != 5 || o_rem[1] != 1) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[2] != 5 || o_rem[2] != 1) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[3] != 5 || o_rem[3] != 1) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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$display("PASS");
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$finish();
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end
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always #1
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clk = ~clk;
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endmodule: VX_tb_divide
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@@ -1,41 +1,135 @@
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module VX_generic_queue #(
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parameter DATAW = 4,
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parameter SIZE = 277
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module VX_generic_queue #(
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parameter DATAW,
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parameter SIZE = 16
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) (
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input wire clk,
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input wire reset,
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input wire push,
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input wire[DATAW-1:0] in_data,
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`IGNORE_WARNINGS_BEGIN
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input wire clk,
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input wire reset,
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input wire push,
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input wire pop,
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output wire empty,
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output wire full,
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`IGNORE_WARNINGS_END
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input wire [DATAW-1:0] in_data,
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output wire [DATAW-1:0] out_data
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);
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if (SIZE == 0) begin
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input wire pop,
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output wire[DATAW-1:0] out_data,
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output wire empty,
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output wire full
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);
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assign empty = 1;
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assign out_data = in_data;
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assign full = 0;
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reg [DATAW-1:0] data [SIZE-1:0];
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reg [`LOG2UP(SIZE)-1:0] head;
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reg [`LOG2UP(SIZE)-1:0] tail;
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end else begin // (SIZE > 0)
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`ifdef QUEUE_FORCE_MLAB
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(* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0];
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`else
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reg [DATAW-1:0] data [SIZE-1:0];
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`endif
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assign empty = (head == tail);
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assign full = (head == (tail+1));
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reg [DATAW-1:0] head_r;
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reg [`LOG2UP(SIZE+1)-1:0] size_r;
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wire reading;
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wire writing;
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integer i;
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always @(posedge clk) begin
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if (reset) begin
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head <= 0;
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tail <= 0;
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end else begin
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if (push && !full) begin
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data[tail] <= in_data;
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tail <= tail+1;
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end
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if (pop && !empty) begin
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head <= head + 1;
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end
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end
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end
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assign reading = pop && !empty;
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assign writing = push && !full;
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assign out_data = data[head];
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if (SIZE == 1) begin
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always @(posedge clk) begin
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if (reset) begin
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size_r <= 0;
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head_r <= 0;
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end else begin
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if (writing && !reading) begin
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size_r <= 1;
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end else if (reading && !writing) begin
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size_r <= 0;
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end
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if (writing) begin
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head_r <= in_data;
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end
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end
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end
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assign out_data = head_r;
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assign empty = (size_r == 0);
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assign full = (size_r != 0) && !pop;
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end else begin // (SIZE > 1)
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reg [DATAW-1:0] curr_r;
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reg [`LOG2UP(SIZE)-1:0] wr_ctr_r;
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reg [`LOG2UP(SIZE)-1:0] rd_ptr_r;
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reg [`LOG2UP(SIZE)-1:0] rd_next_ptr_r;
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reg empty_r;
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reg full_r;
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reg bypass_r;
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always @(posedge clk) begin
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if (reset) begin
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wr_ctr_r <= 0;
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end else begin
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if (writing)
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wr_ctr_r <= wr_ctr_r + 1;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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size_r <= 0;
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empty_r <= 1;
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full_r <= 0;
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end else begin
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if (writing && !reading) begin
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size_r <= size_r + 1;
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empty_r <= 0;
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if (size_r == SIZE-1)
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full_r <= 1;
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end else if (reading && !writing) begin
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size_r <= size_r - 1;
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if (size_r == 1)
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empty_r <= 1;
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full_r <= 0;
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end
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end
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end
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always @(posedge clk) begin
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if (writing) begin
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data[wr_ctr_r] <= in_data;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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curr_r <= 0;
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rd_ptr_r <= 0;
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rd_next_ptr_r <= 1;
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bypass_r <= 0;
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end else begin
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if (reading) begin
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if (SIZE == 2) begin
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rd_ptr_r <= rd_next_ptr_r;
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rd_next_ptr_r <= ~rd_next_ptr_r;
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end else if (SIZE > 2) begin
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rd_ptr_r <= rd_next_ptr_r;
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rd_next_ptr_r <= rd_ptr_r + 2;
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end
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end
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bypass_r <= writing && (empty_r || (1 == size_r) && reading);
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curr_r <= in_data;
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head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r];
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end
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end
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assign out_data = bypass_r ? curr_r : head_r;
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assign empty = empty_r;
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assign full = full_r;
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end
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end
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endmodule
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@@ -1,135 +0,0 @@
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module VX_generic_queue_ll #(
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parameter DATAW,
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parameter SIZE = 16
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) (
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`IGNORE_WARNINGS_BEGIN
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input wire clk,
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input wire reset,
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input wire push,
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input wire pop,
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output wire empty,
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output wire full,
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`IGNORE_WARNINGS_END
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input wire [DATAW-1:0] in_data,
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output wire [DATAW-1:0] out_data
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);
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if (SIZE == 0) begin
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assign empty = 1;
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assign out_data = in_data;
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assign full = 0;
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end else begin // (SIZE > 0)
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`ifdef QUEUE_FORCE_MLAB
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(* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0];
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`else
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reg [DATAW-1:0] data [SIZE-1:0];
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`endif
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reg [DATAW-1:0] head_r;
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reg [`LOG2UP(SIZE+1)-1:0] size_r;
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wire reading;
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wire writing;
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assign reading = pop && !empty;
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assign writing = push && !full;
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if (SIZE == 1) begin
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always @(posedge clk) begin
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if (reset) begin
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size_r <= 0;
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head_r <= 0;
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end else begin
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if (writing && !reading) begin
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size_r <= 1;
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end else if (reading && !writing) begin
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size_r <= 0;
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end
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if (writing) begin
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head_r <= in_data;
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end
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end
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end
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assign out_data = head_r;
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assign empty = (size_r == 0);
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assign full = (size_r != 0) && !pop;
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end else begin // (SIZE > 1)
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reg [DATAW-1:0] curr_r;
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reg [`LOG2UP(SIZE)-1:0] wr_ctr_r;
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reg [`LOG2UP(SIZE)-1:0] rd_ptr_r;
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reg [`LOG2UP(SIZE)-1:0] rd_next_ptr_r;
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reg empty_r;
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reg full_r;
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reg bypass_r;
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always @(posedge clk) begin
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if (reset) begin
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wr_ctr_r <= 0;
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end else begin
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if (writing)
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wr_ctr_r <= wr_ctr_r + 1;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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size_r <= 0;
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empty_r <= 1;
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full_r <= 0;
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end else begin
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if (writing && !reading) begin
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size_r <= size_r + 1;
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empty_r <= 0;
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if (size_r == SIZE-1)
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full_r <= 1;
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end else if (reading && !writing) begin
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size_r <= size_r - 1;
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if (size_r == 1)
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empty_r <= 1;
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full_r <= 0;
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end
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end
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end
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always @(posedge clk) begin
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if (writing) begin
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data[wr_ctr_r] <= in_data;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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curr_r <= 0;
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rd_ptr_r <= 0;
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rd_next_ptr_r <= 1;
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bypass_r <= 0;
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end else begin
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if (reading) begin
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if (SIZE == 2) begin
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rd_ptr_r <= rd_next_ptr_r;
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rd_next_ptr_r <= ~rd_next_ptr_r;
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end else if (SIZE > 2) begin
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rd_ptr_r <= rd_next_ptr_r;
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rd_next_ptr_r <= rd_ptr_r + 2;
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end
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end
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bypass_r <= writing && (empty_r || (1 == size_r) && reading);
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curr_r <= in_data;
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head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r];
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end
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end
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assign out_data = bypass_r ? curr_r : head_r;
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assign empty = empty_r;
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assign full = full_r;
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end
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end
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endmodule
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