RTL code refactoring

2020-04-20 13:01:42 -04:00
parent e8a4923eb4
commit a0e15af0dc
16 changed files with 149 additions and 202 deletions
--- a/simX/cache_simX.v
+++ b/simX/cache_simX.v
@@ -1,5 +1,5 @@

-`include "../old_rtl/VX_define.v"
+`include "VX_define.v"

 module cache_simX (
 	input       wire clk,    // Clock