rtl cache refactory
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@@ -70,13 +70,13 @@ state_t state;
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logic vx_dram_req_read;
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logic vx_dram_req_write;
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logic [31:0] vx_dram_req_addr;
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logic [`GLOBAL_BLOCK_SIZE_BYTES-1:0] vx_dram_req_data;
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logic [`GLOBAL_BLOCK_SIZE-1:0] vx_dram_req_data;
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logic vx_dram_req_ready;
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logic vx_dram_rsp_ready;
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logic vx_dram_rsp_valid;
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logic [31:0] vx_dram_rsp_addr;
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logic [`GLOBAL_BLOCK_SIZE_BYTES-1:0] vx_dram_rsp_data;
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logic [`GLOBAL_BLOCK_SIZE-1:0] vx_dram_rsp_data;
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logic vx_snp_req;
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logic [31:0] vx_snp_req_addr;
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