diff --git a/rtl/VX_alu.v b/rtl/VX_alu.v index 1eda2d0b..7a35fc9b 100644 --- a/rtl/VX_alu.v +++ b/rtl/VX_alu.v @@ -2,7 +2,8 @@ `include "VX_define.v" module VX_alu( - input wire[31:0] in_reg_data[1:0], + input wire[31:0] in_1, + input wire[31:0] in_2, input wire in_rs2_src, input wire[31:0] in_itype_immed, input wire[19:0] in_upper_immed, @@ -22,9 +23,9 @@ module VX_alu( assign which_in2 = in_rs2_src == `RS2_IMMED; - assign ALU_in1 = in_reg_data[0]; + assign ALU_in1 = in_1; - assign ALU_in2 = which_in2 ? in_itype_immed : in_reg_data[1]; + assign ALU_in2 = which_in2 ? in_itype_immed : in_2; assign upper_immed = {in_upper_immed, {12{1'b0}}}; diff --git a/rtl/VX_d_e_reg.v b/rtl/VX_d_e_reg.v index ed342586..def0e650 100644 --- a/rtl/VX_d_e_reg.v +++ b/rtl/VX_d_e_reg.v @@ -7,7 +7,8 @@ module VX_d_e_reg ( input wire[4:0] in_rd, input wire[4:0] in_rs1, input wire[4:0] in_rs2, - input wire[31:0] in_reg_data[`NT_T2_M1:0], + input wire[31:0] in_a_reg_data[`NT_M1:0], + input wire[31:0] in_b_reg_data[`NT_M1:0], input wire[4:0] in_alu_op, input wire[1:0] in_wb, input wire in_rs2_src, // NEW @@ -34,7 +35,8 @@ module VX_d_e_reg ( output wire[4:0] out_rd, output wire[4:0] out_rs1, output wire[4:0] out_rs2, - output wire[31:0] out_reg_data[`NT_T2_M1:0], + output wire[31:0] out_a_reg_data[`NT_M1:0], + output wire[31:0] out_b_reg_data[`NT_M1:0], output wire[4:0] out_alu_op, output wire[1:0] out_wb, output wire out_rs2_src, // NEW @@ -54,7 +56,8 @@ module VX_d_e_reg ( reg[4:0] rd; reg[4:0] rs1; reg[4:0] rs2; - reg[31:0] reg_data[`NT_T2_M1:0]; + reg[31:0] a_reg_data[`NT_M1:0]; + reg[31:0] b_reg_data[`NT_M1:0]; reg[4:0] alu_op; reg[1:0] wb; reg[31:0] PC_next_out; @@ -72,7 +75,7 @@ module VX_d_e_reg ( reg[31:0] jal_offset; reg valid[`NT_M1:0]; - reg[31:0] reg_data_z[`NT_T2_M1:0]; + reg[31:0] reg_data_z[`NT_M1:0]; reg valid_z[`NT_M1:0]; integer ini_reg; @@ -81,10 +84,11 @@ module VX_d_e_reg ( rs1 = 0; for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1) begin - reg_data[ini_reg] = 0; - reg_data_z[ini_reg] = 0; - valid[ini_reg] = 0; - valid_z[ini_reg] = 0; + a_reg_data[ini_reg] = 0; + b_reg_data[ini_reg] = 0; + reg_data_z[ini_reg] = 0; + valid[ini_reg] = 0; + valid_z[ini_reg] = 0; end rs2 = 0; alu_op = 0; @@ -111,7 +115,8 @@ module VX_d_e_reg ( assign out_rd = rd; assign out_rs1 = rs1; assign out_rs2 = rs2; - assign out_reg_data = reg_data; + assign out_a_reg_data = a_reg_data; + assign out_b_reg_data = b_reg_data; assign out_alu_op = alu_op; assign out_wb = wb; assign out_PC_next = PC_next_out; @@ -135,7 +140,8 @@ module VX_d_e_reg ( rd <= stalling ? 5'h0 : in_rd; rs1 <= stalling ? 5'h0 : in_rs1; rs2 <= stalling ? 5'h0 : in_rs2; - reg_data <= stalling ? reg_data_z : in_reg_data; + a_reg_data <= stalling ? reg_data_z : in_a_reg_data; + b_reg_data <= stalling ? reg_data_z : in_b_reg_data; alu_op <= stalling ? `NO_ALU : in_alu_op; wb <= stalling ? `NO_WB : in_wb; PC_next_out <= stalling ? 32'h0 : in_PC_next; diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v index 0b1d892b..a87c6eb8 100644 --- a/rtl/VX_decode.v +++ b/rtl/VX_decode.v @@ -27,7 +27,8 @@ module VX_decode( output wire[4:0] out_rd, output wire[4:0] out_rs1, output wire[4:0] out_rs2, - output wire[31:0] out_reg_data[`NT_T2_M1:0], + output wire[31:0] out_a_reg_data[`NT_M1:0], + output wire[31:0] out_b_reg_data[`NT_M1:0], output wire[1:0] out_wb, output wire[4:0] out_alu_op, output wire out_rs2_src, @@ -212,13 +213,11 @@ module VX_decode( // ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction); genvar index_out_reg; - genvar index_out_reg_2; generate - for (index_out_reg = 0; index_out_reg <= `NT; index_out_reg = index_out_reg + 2) + for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) begin - assign index_out_reg_2 = index_out_reg / 2; - assign out_reg_data[index_out_reg] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg_2] : rd1_register[index_out_reg_2])); - assign out_reg_data[index_out_reg+1] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg_2] : rd2_register[index_out_reg_2]; + assign out_a_reg_data[index_out_reg] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg])); + assign out_b_reg_data[index_out_reg] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg]; end endgenerate @@ -244,7 +243,7 @@ module VX_decode( // end assign out_is_csr = is_csr; - assign out_csr_mask = (is_csr_immed == 1'b1) ? {27'h0, out_rs1} : out_reg_data[0]; + assign out_csr_mask = (is_csr_immed == 1'b1) ? {27'h0, out_rs1} : out_a_reg_data[0]; assign out_wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL : diff --git a/rtl/VX_e_m_reg.v b/rtl/VX_e_m_reg.v index 7523239c..0718771d 100644 --- a/rtl/VX_e_m_reg.v +++ b/rtl/VX_e_m_reg.v @@ -10,7 +10,8 @@ module VX_e_m_reg ( input wire[1:0] in_wb, input wire[4:0] in_rs1, input wire[4:0] in_rs2, - input wire[31:0] in_reg_data[`NT_T2_M1:0], + input wire[31:0] in_a_reg_data[`NT_M1:0], + input wire[31:0] in_b_reg_data[`NT_M1:0], input wire[2:0] in_mem_read, // NEW input wire[2:0] in_mem_write, // NEW input wire[31:0] in_PC_next, @@ -33,7 +34,8 @@ module VX_e_m_reg ( output wire[1:0] out_wb, output wire[4:0] out_rs1, output wire[4:0] out_rs2, - output wire[31:0] out_reg_data[`NT_T2_M1:0], + output wire[31:0] out_a_reg_data[`NT_M1:0], + output wire[31:0] out_b_reg_data[`NT_M1:0], output wire[2:0] out_mem_read, output wire[2:0] out_mem_write, output wire[31:0] out_curr_PC, @@ -50,7 +52,8 @@ module VX_e_m_reg ( reg[4:0] rd; reg[4:0] rs1; reg[4:0] rs2; - reg[31:0] reg_data[`NT_T2_M1:0]; + reg[31:0] a_reg_data[`NT_M1:0]; + reg[31:0] b_reg_data[`NT_M1:0]; reg[1:0] wb; reg[31:0] PC_next; reg[2:0] mem_read; @@ -87,13 +90,12 @@ module VX_e_m_reg ( branch_type = 0; jal = `NO_JUMP; jal_dest = 0; + for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1) begin - reg_data[ini_reg] = 0; - // reg_data_z[ini_reg] = 0; + a_reg_data[ini_reg] = 0; + b_reg_data[ini_reg] = 0; valid[ini_reg] = 0; - // valid_z[ini_reg] = 0; - // alu_result_z[ini_reg] = 0; alu_result[ini_reg] = 0; end end @@ -108,7 +110,8 @@ module VX_e_m_reg ( assign out_PC_next = PC_next; assign out_mem_read = mem_read; assign out_mem_write = mem_write; - assign out_reg_data = reg_data; + assign out_a_reg_data = a_reg_data; + assign out_b_reg_data = b_reg_data; assign out_csr_address = csr_address; assign out_is_csr = is_csr; assign out_csr_result = csr_result; @@ -130,7 +133,8 @@ module VX_e_m_reg ( PC_next <= in_PC_next; mem_read <= in_mem_read; mem_write <= in_mem_write; - reg_data <= in_reg_data; + a_reg_data <= in_a_reg_data; + b_reg_data <= in_b_reg_data; csr_address <= in_csr_address; is_csr <= in_is_csr; csr_result <= in_csr_result; diff --git a/rtl/VX_execute.v b/rtl/VX_execute.v index 0d1c9dec..3fb0119a 100644 --- a/rtl/VX_execute.v +++ b/rtl/VX_execute.v @@ -5,7 +5,8 @@ module VX_execute ( input wire[4:0] in_rd, input wire[4:0] in_rs1, input wire[4:0] in_rs2, - input wire[31:0] in_reg_data[`NT_T2_M1:0], + input wire[31:0] in_a_reg_data[`NT_M1:0], + input wire[31:0] in_b_reg_data[`NT_M1:0], input wire[4:0] in_alu_op, input wire[1:0] in_wb, input wire in_rs2_src, // NEW @@ -32,7 +33,8 @@ module VX_execute ( output wire[1:0] out_wb, output wire[4:0] out_rs1, output wire[4:0] out_rs2, - output wire[31:0] out_reg_data[`NT_T2_M1:0], + output wire[31:0] out_a_reg_data[`NT_M1:0], + output wire[31:0] out_b_reg_data[`NT_M1:0], output wire[2:0] out_mem_read, output wire[2:0] out_mem_write, output wire out_jal, @@ -57,28 +59,46 @@ module VX_execute ( // ); // genvar index; - // genvar index_2; + // reg[5:0] index_2; // generate - // assign index_2 = 0; - // for (index=0; index <= `NT; index=index+2) + // for (index=0; index < `NT; index=index+1) // begin: gen_code_label + // assign index_2 = index * 2; // VX_alu vx_alu( - // .in_reg_data (in_reg_data[index+1:index]), + // .in_reg_data (in_reg_data[(index_2+1):(index_2)]), // .in_rs2_src (in_rs2_src), // .in_itype_immed(in_itype_immed), // .in_upper_immed(in_upper_immed), // .in_alu_op (in_alu_op), // .in_csr_data (in_csr_data), // .in_curr_PC (in_curr_PC), - // .out_alu_result(out_alu_result[index_2]) + // .out_alu_result(out_alu_result[index]) // ); - // index_2 = index_2 + 1; // end // endgenerate + // genvar index_out_reg; + // generate + // for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) + // begin + // VX_alu vx_alu_0( + // // .in_reg_data (in_reg_data[1:0]), + // .in_1 (in_a_reg_data[index_out_reg]), + // .in_2 (in_b_reg_data[index_out_reg]), + // .in_rs2_src (in_rs2_src), + // .in_itype_immed(in_itype_immed), + // .in_upper_immed(in_upper_immed), + // .in_alu_op (in_alu_op), + // .in_csr_data (in_csr_data), + // .in_curr_PC (in_curr_PC), + // .out_alu_result(out_alu_result[index_out_reg]) + // ); + // end + // endgenerate VX_alu vx_alu_0( - .in_reg_data (in_reg_data[1:0]), + .in_1 (in_a_reg_data[0]), + .in_2 (in_b_reg_data[0]), .in_rs2_src (in_rs2_src), .in_itype_immed(in_itype_immed), .in_upper_immed(in_upper_immed), @@ -89,7 +109,8 @@ module VX_execute ( ); VX_alu vx_alu_1( - .in_reg_data (in_reg_data[3:2]), + .in_1 (in_a_reg_data[1]), + .in_2 (in_b_reg_data[1]), .in_rs2_src (in_rs2_src), .in_itype_immed(in_itype_immed), .in_upper_immed(in_upper_immed), @@ -99,7 +120,7 @@ module VX_execute ( .out_alu_result(out_alu_result[1]) ); - assign out_jal_dest = $signed(in_reg_data[0]) + $signed(in_jal_offset); + assign out_jal_dest = $signed(in_a_reg_data[0]) + $signed(in_jal_offset); assign out_jal = in_jal; always @(*) begin @@ -125,7 +146,8 @@ module VX_execute ( assign out_mem_read = in_mem_read; assign out_mem_write = in_mem_write; assign out_rs1 = in_rs1; - assign out_reg_data = in_reg_data; + assign out_a_reg_data = in_a_reg_data; + assign out_b_reg_data = in_b_reg_data; assign out_rs2 = in_rs2; assign out_PC_next = in_PC_next; assign out_is_csr = in_is_csr; diff --git a/rtl/VX_memory.v b/rtl/VX_memory.v index 9a169a67..0721bebf 100644 --- a/rtl/VX_memory.v +++ b/rtl/VX_memory.v @@ -38,7 +38,7 @@ module VX_memory ( always @(in_mem_read, in_cache_driver_out_data) begin if (in_mem_read == `LW_MEM_READ) begin - // $display("PC: %h ----> Received: %h", in_curr_PC, in_cache_driver_out_data); + $display("PC: %h ----> Received: %h for addr: ", in_curr_PC, in_cache_driver_out_data[0], in_alu_result[0]); end end diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 8fe84096..c77ab0c8 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -5,8 +5,9 @@ module Vortex( input wire clk, input wire reset, input wire[31:0] fe_instruction, - input wire[31:0] in_cache_driver_out_data_0, - input wire[31:0] in_cache_driver_out_data_1, + // input wire[31:0] in_cache_driver_out_data_0, + // input wire[31:0] in_cache_driver_out_data_1, + input wire[31:0] in_cache_driver_out_data[`NT_M1:0], output wire[31:0] curr_PC, output wire[31:0] out_cache_driver_in_address[`NT_M1:0], output wire[2:0] out_cache_driver_in_mem_read, @@ -15,10 +16,10 @@ module Vortex( output wire[31:0] out_cache_driver_in_data[`NT_M1:0] ); -wire[31:0] in_cache_driver_out_data[`NT_M1:0]; +// wire[31:0] in_cache_driver_out_data[`NT_M1:0]; -assign in_cache_driver_out_data[0] = in_cache_driver_out_data_0; -assign in_cache_driver_out_data[1] = in_cache_driver_out_data_1; +// assign in_cache_driver_out_data[0] = in_cache_driver_out_data_0; +// assign in_cache_driver_out_data[1] = in_cache_driver_out_data_1; assign curr_PC = fetch_curr_PC; @@ -42,7 +43,8 @@ wire[31:0] decode_csr_mask; wire[4:0] decode_rd; wire[4:0] decode_rs1; wire[4:0] decode_rs2; -wire[31:0] decode_reg_data[`NT_T2_M1:0]; +wire[31:0] decode_a_reg_data[`NT_M1:0]; +wire[31:0] decode_b_reg_data[`NT_M1:0]; wire[1:0] decode_wb; wire[4:0] decode_alu_op; wire decode_rs2_src; @@ -63,7 +65,8 @@ wire[31:0] d_e_csr_mask; wire[4:0] d_e_rd; wire[4:0] d_e_rs1; wire[4:0] d_e_rs2; -wire[31:0] d_e_reg_data[`NT_T2_M1:0]; +wire[31:0] d_e_a_reg_data[`NT_M1:0]; +wire[31:0] d_e_b_reg_data[`NT_M1:0]; wire[4:0] d_e_alu_op; wire[1:0] d_e_wb; wire d_e_rs2_src; @@ -89,14 +92,15 @@ wire[4:0] execute_rd; wire[1:0] execute_wb; wire[4:0] execute_rs1; wire[4:0] execute_rs2; -wire[31:0] execute_reg_data[`NT_T2_M1:0]; +wire[31:0] execute_a_reg_data[`NT_M1:0]; +wire[31:0] execute_b_reg_data[`NT_M1:0]; wire[2:0] execute_mem_read; wire[2:0] execute_mem_write; wire execute_jal; wire[31:0] execute_jal_dest; wire[31:0] execute_branch_offset; wire[31:0] execute_PC_next; -wire execute_valid[`NT_M1:0]; +wire execute_valid[`NT_M1:0]; // From e_m_register @@ -110,8 +114,9 @@ wire[4:0] e_m_rd; wire[1:0] e_m_wb; wire[4:0] e_m_rs1; /* verilator lint_off UNUSED */ -wire[31:0] e_m_reg_data[`NT_T2_M1:0]; +wire[31:0] e_m_a_reg_data[`NT_M1:0]; /* verilator lint_on UNUSED */ +wire[31:0] e_m_b_reg_data[`NT_M1:0]; wire[4:0] e_m_rs2; wire[2:0] e_m_mem_read; wire[2:0] e_m_mem_write; @@ -119,7 +124,7 @@ wire[31:0] e_m_curr_PC; wire[31:0] e_m_branch_offset; wire[2:0] e_m_branch_type; wire[31:0] e_m_PC_next; -wire e_m_valid[`NT_M1:0]; +wire e_m_valid[`NT_M1:0]; // From memory @@ -133,7 +138,7 @@ wire[1:0] memory_wb; wire[4:0] memory_rs1; wire[4:0] memory_rs2; wire[31:0] memory_PC_next; -wire memory_valid[`NT_M1:0]; +wire memory_valid[`NT_M1:0]; // From m_w_register wire[31:0] m_w_alu_result[`NT_M1:0]; @@ -235,7 +240,8 @@ VX_decode vx_decode( .out_rd (decode_rd), .out_rs1 (decode_rs1), .out_rs2 (decode_rs2), - .out_reg_data (decode_reg_data), + .out_a_reg_data (decode_a_reg_data), + .out_b_reg_data (decode_b_reg_data), .out_wb (decode_wb), .out_alu_op (decode_alu_op), .out_rs2_src (decode_rs2_src), @@ -257,7 +263,8 @@ VX_d_e_reg vx_d_e_reg( .in_rd (decode_rd), .in_rs1 (decode_rs1), .in_rs2 (decode_rs2), - .in_reg_data (decode_reg_data), + .in_a_reg_data (decode_a_reg_data), + .in_b_reg_data (decode_b_reg_data), .in_alu_op (decode_alu_op), .in_wb (decode_wb), .in_rs2_src (decode_rs2_src), @@ -284,7 +291,8 @@ VX_d_e_reg vx_d_e_reg( .out_rd (d_e_rd), .out_rs1 (d_e_rs1), .out_rs2 (d_e_rs2), - .out_reg_data (d_e_reg_data), + .out_a_reg_data (d_e_a_reg_data), + .out_b_reg_data (d_e_b_reg_data), .out_alu_op (d_e_alu_op), .out_wb (d_e_wb), .out_rs2_src (d_e_rs2_src), @@ -304,7 +312,8 @@ VX_execute vx_execute( .in_rd (d_e_rd), .in_rs1 (d_e_rs1), .in_rs2 (d_e_rs2), - .in_reg_data (d_e_reg_data), + .in_a_reg_data (d_e_a_reg_data), + .in_b_reg_data (d_e_b_reg_data), .in_alu_op (d_e_alu_op), .in_wb (d_e_wb), .in_rs2_src (d_e_rs2_src), @@ -331,7 +340,8 @@ VX_execute vx_execute( .out_wb (execute_wb), .out_rs1 (execute_rs1), .out_rs2 (execute_rs2), - .out_reg_data (execute_reg_data), + .out_a_reg_data (execute_a_reg_data), + .out_b_reg_data (execute_b_reg_data), .out_mem_read (execute_mem_read), .out_mem_write (execute_mem_write), .out_jal (execute_jal), @@ -349,7 +359,8 @@ VX_e_m_reg vx_e_m_reg( .in_wb (execute_wb), .in_rs1 (execute_rs1), .in_rs2 (execute_rs2), - .in_reg_data (execute_reg_data), + .in_a_reg_data (execute_a_reg_data), + .in_b_reg_data (execute_b_reg_data), .in_mem_read (execute_mem_read), .in_mem_write (execute_mem_write), .in_PC_next (execute_PC_next), @@ -372,7 +383,8 @@ VX_e_m_reg vx_e_m_reg( .out_wb (e_m_wb), .out_rs1 (e_m_rs1), .out_rs2 (e_m_rs2), - .out_reg_data (e_m_reg_data), + .out_a_reg_data (e_m_a_reg_data), + .out_b_reg_data (e_m_b_reg_data), .out_mem_read (e_m_mem_read), .out_mem_write (e_m_mem_write), .out_curr_PC (e_m_curr_PC), @@ -384,10 +396,10 @@ VX_e_m_reg vx_e_m_reg( .out_valid (e_m_valid) ); -wire[31:0] use_rd2[`NT_M1:0]; +// wire[31:0] use_rd2[`NT_M1:0]; -assign use_rd2[0] = e_m_reg_data[1]; -assign use_rd2[1] = e_m_reg_data[3]; +// assign use_rd2[0] = e_m_reg_data[1]; +// assign use_rd2[1] = e_m_reg_data[3]; VX_memory vx_memory( .in_alu_result (e_m_alu_result), @@ -397,7 +409,7 @@ VX_memory vx_memory( .in_wb (e_m_wb), .in_rs1 (e_m_rs1), .in_rs2 (e_m_rs2), - .in_rd2 (use_rd2), + .in_rd2 (e_m_b_reg_data), .in_PC_next (e_m_PC_next), .in_curr_PC (e_m_curr_PC), .in_branch_offset (e_m_branch_offset), diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex index e2985571..66696e66 100755 Binary files a/rtl/obj_dir/VVortex and b/rtl/obj_dir/VVortex differ diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp index 525b0898..67de734d 100644 --- a/rtl/obj_dir/VVortex.cpp +++ b/rtl/obj_dir/VVortex.cpp @@ -237,16 +237,14 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) VL_SIG16(__Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0,31,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0,31,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1,31,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v2,31,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v3,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1,31,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0,31,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1,31,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v2,31,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v3,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0,31,0); @@ -262,26 +260,20 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1 = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid [0U]; - // ALWAYS at VX_e_m_reg.v:123 + // ALWAYS at VX_e_m_reg.v:126 + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data + [1U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data + [0U]; + // ALWAYS at VX_e_m_reg.v:126 __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0 = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid [1U]; __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1 = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid [0U]; - // ALWAYS at VX_e_m_reg.v:123 - __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0 - = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data - [3U]; - __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1 - = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data - [2U]; - __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v2 - = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data - [1U]; - __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v3 - = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data - [0U]; // ALWAYS at VX_m_w_reg.v:60 __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0 = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result @@ -296,7 +288,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1 = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result [0U]; - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed = (0xfffffU & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : ((0x37U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) @@ -320,23 +312,23 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret); } - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src = (1U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (1U & (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype) | (0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) ? 1U : 0U)))); - // ALWAYS at VX_e_m_reg.v:123 + // ALWAYS at VX_e_m_reg.v:126 __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0 = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result [1U]; __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1 = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result [0U]; - // ALWAYS at VX_e_m_reg.v:123 + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type; - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0 = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z @@ -347,25 +339,25 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid [0U]); - // ALWAYS at VX_e_m_reg.v:123 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read; - // ALWAYS at VX_e_m_reg.v:123 + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write; - // ALWAYS at VX_e_m_reg.v:123 + // ALWAYS at VX_e_m_reg.v:126 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read; + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal; - // ALWAYS at VX_e_m_reg.v:123 + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC; - // ALWAYS at VX_e_m_reg.v:123 + // ALWAYS at VX_e_m_reg.v:126 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + = (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset); + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed; // ALWAYS at VX_m_w_reg.v:60 vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; - // ALWAYS at VX_e_m_reg.v:123 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest - = (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [0U] + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset); // ALWAYS at VX_register_file.v:36 if (VL_UNLIKELY((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) @@ -394,6 +386,17 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0 = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; } + // ALWAYS at VX_d_e_reg.v:138 + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data + [1U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data + [0U]); // ALWAYS at VX_csr_handler.v:43 if (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr) { __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0 @@ -402,46 +405,32 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) __Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address; } - // ALWAYS at VX_d_e_reg.v:133 - __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0 + // ALWAYS at VX_d_e_reg.v:138 + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0 = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z - [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data - [3U]); - __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1 - = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) - ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z - [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data - [2U]); - __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v2 - = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) - ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z - [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data [1U]); - __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v3 + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1 = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z - [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data [0U]); // ALWAYSPOST at VX_m_w_reg.v:69 vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[1U] = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0; vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[0U] = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1; - // ALWAYSPOST at VX_e_m_reg.v:142 + // ALWAYSPOST at VX_e_m_reg.v:137 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[1U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[0U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1; + // ALWAYSPOST at VX_e_m_reg.v:146 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1; - // ALWAYSPOST at VX_e_m_reg.v:133 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[3U] - = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0; - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[2U] - = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1; - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[1U] - = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v2; - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[0U] - = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v3; // ALWAYSPOST at VX_m_w_reg.v:62 vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[1U] = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0; @@ -452,12 +441,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0; vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[0U] = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1; - // ALWAYSPOST at VX_e_m_reg.v:125 + // ALWAYSPOST at VX_e_m_reg.v:128 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1; - // ALWAYSPOST at VX_d_e_reg.v:154 + // ALWAYSPOST at VX_d_e_reg.v:160 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] @@ -472,44 +461,39 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0] = __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0; } + // ALWAYSPOST at VX_d_e_reg.v:143 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[1U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[0U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1; // ALWAYSPOST at VX_csr_handler.v:45 if (__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0) { vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr[__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0] = __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0; } - // ALWAYSPOST at VX_d_e_reg.v:138 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[3U] - = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0; - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[2U] - = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1; - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[1U] - = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v2; - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[0U] - = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v3; + // ALWAYSPOST at VX_d_e_reg.v:144 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[1U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[0U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1; vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data - [3U]; - vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data - [2U]; - vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data - [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data - [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result [1U]; @@ -528,7 +512,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result [0U]; - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (IData)(vlTOPp->Vortex__DOT__decode_branch_type)); @@ -538,21 +522,21 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid [0U]; - vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read; - // ALWAYS at VX_d_e_reg.v:133 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read - = (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) - ? 7U : ((3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) - ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xcU) : 7U))); vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write; - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write = (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 7U : ((0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU) : 7U))); - // ALWAYS at VX_d_e_reg.v:133 + vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read; + // ALWAYS at VX_d_e_reg.v:138 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read + = (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 7U : ((3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU) : 7U))); + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal = ((~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) & ((0x6fU == @@ -576,28 +560,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) (0xfffU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U)))))))); - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC); - vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC - + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset - << 1U)); - // ALWAYS at VX_d_e_reg.v:133 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed - = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) - ? 0xdeadbeefU : vlTOPp->Vortex__DOT__decode_itype_immed); - vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] - = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; - vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] - = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; - vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] - = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; - vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] - = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; - // ALWAYS at VX_e_m_reg.v:123 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) @@ -629,16 +596,39 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) >> 0x14U)))) ? 0xb0000000U : 0xdeadbeefU) : 0xdeadbeefU)))); + vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset + << 1U)); + // ALWAYS at VX_d_e_reg.v:138 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0xdeadbeefU : vlTOPp->Vortex__DOT__decode_itype_immed); + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + // ALWAYS at VX_e_m_reg.v:126 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; // ALWAYS at VX_m_w_reg.v:60 vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd; // ALWAYS at VX_m_w_reg.v:60 vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb; - // ALWAYS at VX_e_m_reg.v:123 + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [0U]; + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address; - // ALWAYS at VX_e_m_reg.v:123 + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__is_csr; - // ALWAYS at VX_e_m_reg.v:123 + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_result = ((0xdU == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask @@ -649,34 +639,24 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ? (vlTOPp->Vortex__DOT__csr_decode_csr_data & ((IData)(0xffffffffU) - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask)) : 0xdeadbeefU))); - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data - [3U]; - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data - [2U]; - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data [0U]; vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid [1U]; vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid [0U]; + vlTOPp->Vortex__DOT__e_m_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__e_m_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [0U]; vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid [1U]; vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid [0U]; - vlTOPp->Vortex__DOT__e_m_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data - [3U]; - vlTOPp->Vortex__DOT__e_m_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data - [2U]; - vlTOPp->Vortex__DOT__e_m_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data - [1U]; - vlTOPp->Vortex__DOT__e_m_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data - [0U]; vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result [1U]; vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result @@ -693,6 +673,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) [1U]; vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid [0U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [0U]; vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle) @@ -715,13 +699,9 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) : vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr [vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address])))); - vlTOPp->Vortex__DOT__d_e_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data - [3U]; - vlTOPp->Vortex__DOT__d_e_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data - [2U]; - vlTOPp->Vortex__DOT__d_e_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + vlTOPp->Vortex__DOT__d_e_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data [1U]; - vlTOPp->Vortex__DOT__d_e_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + vlTOPp->Vortex__DOT__d_e_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data [0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] = vlTOPp->Vortex__DOT__m_w_valid[1U]; @@ -731,14 +711,14 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = vlTOPp->Vortex__DOT__m_w_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid[0U] = vlTOPp->Vortex__DOT__m_w_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] = vlTOPp->Vortex__DOT__e_m_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] = vlTOPp->Vortex__DOT__e_m_valid[0U]; - vlTOPp->Vortex__DOT__use_rd2[0U] = vlTOPp->Vortex__DOT__e_m_reg_data - [1U]; - vlTOPp->Vortex__DOT__use_rd2[1U] = vlTOPp->Vortex__DOT__e_m_reg_data - [3U]; vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] @@ -770,32 +750,36 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : ((IData)(4U) + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC)); - // ALWAYS at VX_e_m_reg.v:123 + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd; - // ALWAYS at VX_e_m_reg.v:123 + // ALWAYS at VX_e_m_reg.v:126 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb; - // ALWAYS at VX_d_e_reg.v:133 + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[0U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[0U]; + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (IData)(vlTOPp->Vortex__DOT__decode_csr_address)); - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__is_csr = ((~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr)); - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xeU)) ? (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)) - : vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data + : vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data [0U])); - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0xfU : (((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction @@ -803,14 +787,16 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) ? (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu) : (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu))); - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[3U] - = vlTOPp->Vortex__DOT__d_e_reg_data[3U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2U] - = vlTOPp->Vortex__DOT__d_e_reg_data[2U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[1U] - = vlTOPp->Vortex__DOT__d_e_reg_data[1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[0U] - = vlTOPp->Vortex__DOT__d_e_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid [1U]; @@ -823,10 +809,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid [0U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] - = vlTOPp->Vortex__DOT__use_rd2[1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] - = vlTOPp->Vortex__DOT__use_rd2[0U]; vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data @@ -905,30 +887,26 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[3U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [3U]; - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[2U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [2U]; - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data [0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [0U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [1U]); + vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data [1U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data [0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [3U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [2U]; vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid [1U]; vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid @@ -937,12 +915,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) [1U]; vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 - [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 - [0U]; vlTOPp->Vortex__DOT__writeback_write_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data [1U]; @@ -965,14 +937,14 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = (0x1fU & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 7U))); - // ALWAYS at VX_d_e_reg.v:133 + // ALWAYS at VX_d_e_reg.v:138 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : @@ -1017,32 +989,24 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr)) ? 1U : 0U)))); - vlTOPp->Vortex__DOT__execute_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data - [3U]; - vlTOPp->Vortex__DOT__execute_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data - [2U]; - vlTOPp->Vortex__DOT__execute_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data + vlTOPp->Vortex__DOT__execute_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data [1U]; - vlTOPp->Vortex__DOT__execute_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data + vlTOPp->Vortex__DOT__execute_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data [0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 - = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) - ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed - : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data - [1U]); - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 - = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) - ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed - : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [1U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)); vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1U] = vlTOPp->Vortex__DOT__memory_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] = vlTOPp->Vortex__DOT__memory_valid[0U]; - vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data - [1U]; - vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data - [0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] = vlTOPp->Vortex__DOT__writeback_write_data [1U]; @@ -1061,25 +1025,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = vlTOPp->Vortex__DOT__execute_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] = vlTOPp->Vortex__DOT__execute_valid[0U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[3U] - = vlTOPp->Vortex__DOT__execute_reg_data[3U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2U] - = vlTOPp->Vortex__DOT__execute_reg_data[2U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[1U] - = vlTOPp->Vortex__DOT__execute_reg_data[1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[0U] - = vlTOPp->Vortex__DOT__execute_reg_data[0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result - = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data - [0U]), - VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)); - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result - = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U]), - VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)); - // ALWAYS at VX_alu.v:47 + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[0U]; + // ALWAYS at VX_alu.v:48 if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result = 0U; @@ -1089,42 +1039,42 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) - ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] : VL_MODDIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)) : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) - ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] : VL_MODDIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) ? 0xffffffffU : VL_DIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)) : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) ? 0xffffffffU : VL_DIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))); } else { if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result = ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (IData)((((QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U])) * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) >> 0x20U)) : (IData)( (((((QData)((IData)( VL_NEGATE_I((IData)( (1U - & (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] >> 0x1fU)))))) << 0x20U) | (QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U]))) * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) >> 0x20U))); @@ -1138,7 +1088,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result); VL_WRITEF("(%x) %x * %x = %x\n", 32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC, - 32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + 32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2, 32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result); } @@ -1164,7 +1114,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed << 0xcU) : - ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] >= vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) ? 0U @@ -1174,26 +1124,26 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 - & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U]) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] | vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))) : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? VL_SHIFTRS_III(32,32,5, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)) - : (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) - : ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) ? 1U : 0U))) : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) @@ -1202,12 +1152,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (VL_LTS_III(1,32,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) ? 1U : 0U) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] << (0x1fU @@ -1216,15 +1166,15 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))))); } - // ALWAYS at VX_alu.v:47 + // ALWAYS at VX_alu.v:48 if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result = 0U; @@ -1234,43 +1184,43 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) - ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] : VL_MODDIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)) : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) - ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] : VL_MODDIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) ? 0xffffffffU : VL_DIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)) + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)) : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) ? 0xffffffffU : VL_DIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))); + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))); } else { if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result = ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (IData)((((QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U])) + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U])) * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) >> 0x20U)) : (IData)( (((((QData)((IData)( VL_NEGATE_I((IData)( (1U - & (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] >> 0x1fU)))))) << 0x20U) | (QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U]))) + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]))) * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) >> 0x20U))); } else { @@ -1283,8 +1233,8 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result); VL_WRITEF("(%x) %x * %x = %x\n", 32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC, - 32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2, + 32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2, 32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result); } } @@ -1309,8 +1259,8 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed << 0xcU) : - ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] >= vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) ? 0U : 0xffffffffU)) @@ -1319,27 +1269,27 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 - & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U]) + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] | vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))) : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? VL_SHIFTRS_III(32,32,5, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)) - : (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) - : ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) ? 1U : 0U))) : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? @@ -1347,13 +1297,13 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (VL_LTS_III(1,32,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) ? 1U : 0U) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] << (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) @@ -1361,12 +1311,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))))); } vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] @@ -1387,65 +1337,14 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) = vlTOPp->Vortex__DOT__execute_alu_result[0U]; } -VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__3\n"); ); +VL_INLINE_OPT void VVortex::_combo__TOP__3(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_combo__TOP__3\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // ALWAYS at VX_writeback.v:43 - if (VL_UNLIKELY((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)))) { - VL_WRITEF("[%x] WB Data: %x {%x}, to register: %2# [%1# %1#]\n", - 32,(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next - - (IData)(4U)),32,vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data - [0U],32,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result - [0U],5,vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd, - 1,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid - [0U],1,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid - [1U]); - } - // ALWAYS at VX_register_file.v:43 - vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data - = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers - [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0x14U))]; - // ALWAYS at VX_register_file.v:43 - vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data - = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers - [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0x14U))]; - // ALWAYS at VX_register_file.v:43 - vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data - = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers - [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU))]; - // ALWAYS at VX_register_file.v:43 - vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data - = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers - [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU))]; - vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[1U] - = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data; - vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] - = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data; - vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] - = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data; - vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] - = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data; -} - -VL_INLINE_OPT void VVortex::_combo__TOP__4(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_combo__TOP__4\n"); ); - VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->Vortex__DOT__in_cache_driver_out_data[0U] - = vlTOPp->in_cache_driver_out_data_0; - vlTOPp->Vortex__DOT__in_cache_driver_out_data[1U] - = vlTOPp->in_cache_driver_out_data_1; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] - = vlTOPp->Vortex__DOT__in_cache_driver_out_data - [1U]; + = vlTOPp->in_cache_driver_out_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] - = vlTOPp->Vortex__DOT__in_cache_driver_out_data - [0U]; + = vlTOPp->in_cache_driver_out_data[0U]; // ALWAYS at VX_memory.v:62 if (VL_UNLIKELY((0xbabebabeU != vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data [0U]))) { @@ -1459,6 +1358,14 @@ VL_INLINE_OPT void VVortex::_combo__TOP__4(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data [0U]; + // ALWAYS at VX_memory.v:39 + if (VL_UNLIKELY((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read)))) { + VL_WRITEF("PC: %x ----> Received: %x for addr: %x\n", + 32,vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC, + 32,vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [0U],32,vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]); + } vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result [1U]; vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result @@ -1473,14 +1380,14 @@ VL_INLINE_OPT void VVortex::_combo__TOP__4(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->Vortex__DOT__memory_mem_result[0U]; } -void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_settle__TOP__5\n"); ); +void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_settle__TOP__4\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - vlTOPp->Vortex__DOT__in_cache_driver_out_data[0U] - = vlTOPp->in_cache_driver_out_data_0; - vlTOPp->Vortex__DOT__in_cache_driver_out_data[1U] - = vlTOPp->in_cache_driver_out_data_1; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] + = vlTOPp->in_cache_driver_out_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] + = vlTOPp->in_cache_driver_out_data[0U]; vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid [1U]; @@ -1531,7 +1438,7 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) { (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U) : 0x55U)); - // ALWAYS at VX_decode.v:393 + // ALWAYS at VX_decode.v:392 vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)); vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = @@ -1557,7 +1464,7 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) { (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)))); - // ALWAYS at VX_decode.v:343 + // ALWAYS at VX_decode.v:342 vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U == (0x7fU @@ -1588,11 +1495,18 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) { ? 2U : 1U))) : 0U); - vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] - = vlTOPp->Vortex__DOT__in_cache_driver_out_data + // ALWAYS at VX_memory.v:62 + if (VL_UNLIKELY((0xbabebabeU != vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [0U]))) { + VL_WRITEF("MEM: data read from cache_driver: %x\n", + 32,vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [0U]); + } + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data [1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] - = vlTOPp->Vortex__DOT__in_cache_driver_out_data + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data [0U]; vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid [1U]; @@ -1610,7 +1524,7 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) { [1U]; vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result [0U]; - // ALWAYS at VX_decode.v:332 + // ALWAYS at VX_decode.v:331 vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) ? ( @@ -1826,18 +1740,9 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) { >> 0x19U))) ? 0U : 1U)))))))))); - // ALWAYS at VX_memory.v:62 - if (VL_UNLIKELY((0xbabebabeU != vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data - [0U]))) { - VL_WRITEF("MEM: data read from cache_driver: %x\n", - 32,vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data - [0U]); - } - vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result [0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] = vlTOPp->Vortex__DOT__m_w_valid[1U]; @@ -1867,16 +1772,6 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; - vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result - [1U]; - vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result - [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid - [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid - [0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1U] = vlTOPp->Vortex__DOT__memory_mem_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[0U] @@ -1885,6 +1780,12 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->Vortex__DOT__memory_mem_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] = vlTOPp->Vortex__DOT__memory_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]; vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid [1U]; vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid @@ -1895,6 +1796,51 @@ void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->Vortex__DOT__decode_valid[0U]; } +VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__5\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // ALWAYS at VX_writeback.v:43 + if (VL_UNLIKELY((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)))) { + VL_WRITEF("[%x] WB Data: %x {%x}, to register: %2# [%1# %1#]\n", + 32,(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next + - (IData)(4U)),32,vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [0U],32,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [0U],5,vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd, + 1,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid + [0U],1,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid + [1U]); + } + // ALWAYS at VX_register_file.v:43 + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + // ALWAYS at VX_register_file.v:43 + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + // ALWAYS at VX_register_file.v:43 + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + // ALWAYS at VX_register_file.v:43 + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data; +} + void VVortex::_initial__TOP__6(VVortex__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_initial__TOP__6\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; @@ -1920,7 +1866,7 @@ void VVortex::_initial__TOP__6(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle = VL_ULL(0); vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret = VL_ULL(0); vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address = 0U; - // INITIAL at VX_e_m_reg.v:74 + // INITIAL at VX_e_m_reg.v:77 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = 0U; @@ -1934,19 +1880,23 @@ void VVortex::_initial__TOP__6(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest = 0U; - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[0U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[0U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[0U] = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] = 0U; - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[1U] = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] = 0U; - // INITIAL at VX_d_e_reg.v:79 + // INITIAL at VX_d_e_reg.v:82 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = 0U; - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[0U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[0U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[0U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[0U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[0U] = 0U; - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[1U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[1U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[1U] = 0U; @@ -2023,7 +1973,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U) : 0x55U)); - // ALWAYS at VX_decode.v:393 + // ALWAYS at VX_decode.v:392 vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)); vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = @@ -2049,7 +1999,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)))); - // ALWAYS at VX_decode.v:343 + // ALWAYS at VX_decode.v:342 vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U == (0x7fU @@ -2090,7 +2040,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); - // ALWAYS at VX_decode.v:332 + // ALWAYS at VX_decode.v:331 vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) ? ( @@ -2439,29 +2389,23 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { : vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr [vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address])))); - vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read; vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write; + vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read; vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset << 1U)); + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data - [3U]; - vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data - [2U]; - vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data - [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data - [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result [1U]; @@ -2481,17 +2425,17 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data - [3U]; - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data - [2U]; - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data [0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; @@ -2521,18 +2465,14 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result [0U])); + vlTOPp->Vortex__DOT__e_m_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__e_m_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [0U]; vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid [1U]; vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid [0U]; - vlTOPp->Vortex__DOT__e_m_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data - [3U]; - vlTOPp->Vortex__DOT__e_m_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data - [2U]; - vlTOPp->Vortex__DOT__e_m_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data - [1U]; - vlTOPp->Vortex__DOT__e_m_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data - [0U]; vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result [1U]; vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result @@ -2541,13 +2481,13 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { [1U]; vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid [0U]; - vlTOPp->Vortex__DOT__d_e_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data - [3U]; - vlTOPp->Vortex__DOT__d_e_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data - [2U]; - vlTOPp->Vortex__DOT__d_e_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + vlTOPp->Vortex__DOT__d_e_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data [1U]; - vlTOPp->Vortex__DOT__d_e_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + vlTOPp->Vortex__DOT__d_e_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__d_e_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__d_e_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data [0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction @@ -2568,14 +2508,14 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__writeback_write_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[0U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] = vlTOPp->Vortex__DOT__e_m_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] = vlTOPp->Vortex__DOT__e_m_valid[0U]; - vlTOPp->Vortex__DOT__use_rd2[0U] = vlTOPp->Vortex__DOT__e_m_reg_data - [1U]; - vlTOPp->Vortex__DOT__use_rd2[1U] = vlTOPp->Vortex__DOT__e_m_reg_data - [3U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] = vlTOPp->Vortex__DOT__e_m_alu_result[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] @@ -2584,14 +2524,14 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->Vortex__DOT__d_e_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] = vlTOPp->Vortex__DOT__d_e_valid[0U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[3U] - = vlTOPp->Vortex__DOT__d_e_reg_data[3U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2U] - = vlTOPp->Vortex__DOT__d_e_reg_data[2U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[1U] - = vlTOPp->Vortex__DOT__d_e_reg_data[1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[0U] - = vlTOPp->Vortex__DOT__d_e_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[0U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) @@ -2622,6 +2562,12 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] = vlTOPp->Vortex__DOT__writeback_write_data [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid [1U]; @@ -2634,10 +2580,14 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid [0U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] - = vlTOPp->Vortex__DOT__use_rd2[1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] - = vlTOPp->Vortex__DOT__use_rd2[0U]; + // ALWAYS at VX_memory.v:39 + if (VL_UNLIKELY((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read)))) { + VL_WRITEF("PC: %x ----> Received: %x for addr: %x\n", + 32,vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC, + 32,vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [0U],32,vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]); + } vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result [1U]; @@ -2702,30 +2652,22 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[3U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [3U]; - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[2U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [2U]; - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data [0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [1U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [3U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [2U]; + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [0U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [1U]); vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)); @@ -2750,6 +2692,10 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)); + vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [1U]; + vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [0U]; vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid [1U]; vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid @@ -2758,12 +2704,6 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { [1U]; vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 - [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 - [0U]; vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address [1U]; vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address @@ -2786,24 +2726,20 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { [1U]; vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid [0U]; - vlTOPp->Vortex__DOT__execute_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data - [3U]; - vlTOPp->Vortex__DOT__execute_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data - [2U]; - vlTOPp->Vortex__DOT__execute_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data + vlTOPp->Vortex__DOT__execute_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data [1U]; - vlTOPp->Vortex__DOT__execute_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data + vlTOPp->Vortex__DOT__execute_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data [0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 - = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) - ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed - : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data - [1U]); - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 - = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) - ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed - : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [1U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)); vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] = (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid))); @@ -2815,10 +2751,6 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->Vortex__DOT__memory_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] = vlTOPp->Vortex__DOT__memory_valid[0U]; - vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data - [1U]; - vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data - [0U]; vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC; vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] = vlTOPp->Vortex__DOT__memory_alu_result[1U]; @@ -2832,29 +2764,11 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { = vlTOPp->Vortex__DOT__execute_valid[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] = vlTOPp->Vortex__DOT__execute_valid[0U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[3U] - = vlTOPp->Vortex__DOT__execute_reg_data[3U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2U] - = vlTOPp->Vortex__DOT__execute_reg_data[2U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[1U] - = vlTOPp->Vortex__DOT__execute_reg_data[1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[0U] - = vlTOPp->Vortex__DOT__execute_reg_data[0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result - = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data - [0U]), - VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)); - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result - = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U]), - VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)); - vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid - [1U]; - vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid - [0U]; - // ALWAYS at VX_alu.v:47 + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[0U]; + // ALWAYS at VX_alu.v:48 if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result = 0U; @@ -2864,42 +2778,42 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) - ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] : VL_MODDIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)) : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) - ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] : VL_MODDIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) ? 0xffffffffU : VL_DIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)) : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) ? 0xffffffffU : VL_DIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))); } else { if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result = ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (IData)((((QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U])) * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) >> 0x20U)) : (IData)( (((((QData)((IData)( VL_NEGATE_I((IData)( (1U - & (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] >> 0x1fU)))))) << 0x20U) | (QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U]))) * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) >> 0x20U))); @@ -2913,7 +2827,7 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result); VL_WRITEF("(%x) %x * %x = %x\n", 32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC, - 32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + 32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2, 32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result); } @@ -2939,7 +2853,7 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed << 0xcU) : - ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] >= vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) ? 0U @@ -2949,26 +2863,26 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 - & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U]) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] | vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)))) : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? VL_SHIFTRS_III(32,32,5, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2)) - : (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) - : ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) ? 1U : 0U))) : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) @@ -2977,12 +2891,12 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (VL_LTS_III(1,32,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) ? 1U : 0U) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] << (0x1fU @@ -2991,15 +2905,15 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data [0U] + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2))))); } - // ALWAYS at VX_alu.v:47 + // ALWAYS at VX_alu.v:48 if ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { if ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result = 0U; @@ -3009,43 +2923,43 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { = ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) - ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] : VL_MODDIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)) : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) - ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] : VL_MODDIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) ? 0xffffffffU : VL_DIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)) + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)) : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) ? 0xffffffffU : VL_DIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))); + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))); } else { if ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))) { vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result = ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (IData)((((QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U])) + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U])) * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) >> 0x20U)) : (IData)( (((((QData)((IData)( VL_NEGATE_I((IData)( (1U - & (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] >> 0x1fU)))))) << 0x20U) | (QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U]))) + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]))) * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) >> 0x20U))); } else { @@ -3058,8 +2972,8 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { = (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result); VL_WRITEF("(%x) %x * %x = %x\n", 32,vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC, - 32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2, + 32,vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U],32,vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2, 32,vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result); } } @@ -3084,8 +2998,8 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed << 0xcU) : - ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] >= vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) ? 0U : 0xffffffffU)) @@ -3094,27 +3008,27 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 - & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U]) + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] | vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))) : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? VL_SHIFTRS_III(32,32,5, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)) - : (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) - : ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) ? 1U : 0U))) : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? @@ -3122,13 +3036,13 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? (VL_LTS_III(1,32,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) ? 1U : 0U) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] << (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))) @@ -3136,22 +3050,26 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2) : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data - [0U] + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2))))); } - vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1U] - = vlTOPp->Vortex__DOT__fetch_valid[1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[0U] - = vlTOPp->Vortex__DOT__fetch_valid[0U]; + vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [1U]; + vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result; vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[1U] = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result; + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__fetch_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__fetch_valid[0U]; vlTOPp->Vortex__DOT__execute_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result [1U]; vlTOPp->Vortex__DOT__execute_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result @@ -3300,46 +3218,46 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[0U] = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[1U] + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[0U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register [0U]); - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[3U] + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[1U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data - [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register - [0U]); - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[0U] + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register + [1U]); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[0U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register [0U])); - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[2U] + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[1U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data - [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register - [0U])); - vlTOPp->Vortex__DOT__decode_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data - [3U]; - vlTOPp->Vortex__DOT__decode_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data - [2U]; - vlTOPp->Vortex__DOT__decode_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register + [1U])); + vlTOPp->Vortex__DOT__decode_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data [1U]; - vlTOPp->Vortex__DOT__decode_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data + vlTOPp->Vortex__DOT__decode_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data [0U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[3U] - = vlTOPp->Vortex__DOT__decode_reg_data[3U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[2U] - = vlTOPp->Vortex__DOT__decode_reg_data[2U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[1U] - = vlTOPp->Vortex__DOT__decode_reg_data[1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[0U] - = vlTOPp->Vortex__DOT__decode_reg_data[0U]; + vlTOPp->Vortex__DOT__decode_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__decode_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__decode_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__decode_b_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[1U] + = vlTOPp->Vortex__DOT__decode_a_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[0U] + = vlTOPp->Vortex__DOT__decode_a_reg_data[0U]; } VL_INLINE_OPT void VVortex::_combo__TOP__9(VVortex__Syms* __restrict vlSymsp) { @@ -3482,46 +3400,46 @@ VL_INLINE_OPT void VVortex::_combo__TOP__9(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[0U] = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data [0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[1U] + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[0U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register [0U]); - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[3U] + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[1U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data - [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register - [0U]); - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[0U] + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register + [1U]); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[0U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register [0U])); - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[2U] + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[1U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data - [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register - [0U])); - vlTOPp->Vortex__DOT__decode_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data - [3U]; - vlTOPp->Vortex__DOT__decode_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data - [2U]; - vlTOPp->Vortex__DOT__decode_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register + [1U])); + vlTOPp->Vortex__DOT__decode_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data [1U]; - vlTOPp->Vortex__DOT__decode_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data + vlTOPp->Vortex__DOT__decode_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data [0U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[3U] - = vlTOPp->Vortex__DOT__decode_reg_data[3U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[2U] - = vlTOPp->Vortex__DOT__decode_reg_data[2U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[1U] - = vlTOPp->Vortex__DOT__decode_reg_data[1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[0U] - = vlTOPp->Vortex__DOT__decode_reg_data[0U]; + vlTOPp->Vortex__DOT__decode_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__decode_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__decode_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__decode_b_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[1U] + = vlTOPp->Vortex__DOT__decode_a_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[0U] + = vlTOPp->Vortex__DOT__decode_a_reg_data[0U]; } void VVortex::_eval(VVortex__Syms* __restrict vlSymsp) { @@ -3535,10 +3453,10 @@ void VVortex::_eval(VVortex__Syms* __restrict vlSymsp) { if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) { vlTOPp->_sequent__TOP__2(vlSymsp); } + vlTOPp->_combo__TOP__3(vlSymsp); if (((~ (IData)(vlTOPp->clk)) & (IData)(vlTOPp->__Vclklast__TOP__clk))) { - vlTOPp->_sequent__TOP__3(vlSymsp); + vlTOPp->_sequent__TOP__5(vlSymsp); } - vlTOPp->_combo__TOP__4(vlSymsp); if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) { vlTOPp->_sequent__TOP__7(vlSymsp); @@ -3569,7 +3487,7 @@ void VVortex::_eval_settle(VVortex__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_eval_settle\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - vlTOPp->_settle__TOP__5(vlSymsp); + vlTOPp->_settle__TOP__4(vlSymsp); vlTOPp->_settle__TOP__8(vlSymsp); } @@ -3599,8 +3517,9 @@ void VVortex::_ctor_var_reset() { clk = VL_RAND_RESET_I(1); reset = VL_RAND_RESET_I(1); fe_instruction = VL_RAND_RESET_I(32); - in_cache_driver_out_data_0 = VL_RAND_RESET_I(32); - in_cache_driver_out_data_1 = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32); + }} curr_PC = VL_RAND_RESET_I(32); { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32); @@ -3613,9 +3532,6 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { - Vortex__DOT__in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32); - }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__fetch_valid[__Vi0] = VL_RAND_RESET_I(1); }} @@ -3623,16 +3539,22 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__f_d_valid[__Vi0] = VL_RAND_RESET_I(1); }} Vortex__DOT__decode_csr_address = VL_RAND_RESET_I(12); - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT__decode_reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__decode_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__decode_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__decode_itype_immed = VL_RAND_RESET_I(32); Vortex__DOT__decode_branch_type = VL_RAND_RESET_I(3); { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__decode_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT__d_e_reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__d_e_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__d_e_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__d_e_valid[__Vi0] = VL_RAND_RESET_I(1); @@ -3641,8 +3563,8 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__execute_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT__execute_reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__execute_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__execute_valid[__Vi0] = VL_RAND_RESET_I(1); @@ -3650,8 +3572,8 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__e_m_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT__e_m_reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__e_m_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__e_m_valid[__Vi0] = VL_RAND_RESET_I(1); @@ -3701,8 +3623,11 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_decode__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT____Vcellout__vx_decode__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); @@ -3722,20 +3647,26 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_execute__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT____Vcellout__vx_execute__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_execute__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); @@ -3743,14 +3674,17 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_execute__in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT____Vcellinp__vx_execute__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); @@ -3758,15 +3692,12 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { - Vortex__DOT__use_rd2[__Vi0] = VL_RAND_RESET_I(32); - }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1); }} @@ -3887,8 +3818,11 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_d_e_reg__DOT__rd = VL_RAND_RESET_I(5); - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT__vx_d_e_reg__DOT__reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_d_e_reg__DOT__alu_op = VL_RAND_RESET_I(5); Vortex__DOT__vx_d_e_reg__DOT__wb = VL_RAND_RESET_I(2); @@ -3908,7 +3842,7 @@ void VVortex::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_d_e_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); }} - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { @@ -3916,13 +3850,7 @@ void VVortex::_ctor_var_reset() { }} Vortex__DOT__vx_d_e_reg__DOT__stalling = VL_RAND_RESET_I(1); Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { - Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); - }} Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { - Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); - }} Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2 = VL_RAND_RESET_I(32); Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result = VL_RAND_RESET_Q(64); Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 = VL_RAND_RESET_I(32); @@ -3931,8 +3859,11 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_e_m_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_e_m_reg__DOT__rd = VL_RAND_RESET_I(5); - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - Vortex__DOT__vx_e_m_reg__DOT__reg_data[__Vi0] = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_e_m_reg__DOT__wb = VL_RAND_RESET_I(2); Vortex__DOT__vx_e_m_reg__DOT__PC_next = VL_RAND_RESET_I(32); diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h index 90aad2ba..5d031d33 100644 --- a/rtl/obj_dir/VVortex.h +++ b/rtl/obj_dir/VVortex.h @@ -26,9 +26,8 @@ VL_MODULE(VVortex) { VL_OUT8(out_cache_driver_in_mem_read,2,0); VL_OUT8(out_cache_driver_in_mem_write,2,0); VL_IN(fe_instruction,31,0); - VL_IN(in_cache_driver_out_data_0,31,0); - VL_IN(in_cache_driver_out_data_1,31,0); VL_OUT(curr_PC,31,0); + VL_IN(in_cache_driver_out_data[2],31,0); VL_OUT(out_cache_driver_in_address[2],31,0); VL_OUT8(out_cache_driver_in_valid[2],0,0); VL_OUT(out_cache_driver_in_data[2],31,0); @@ -115,18 +114,19 @@ VL_MODULE(VVortex) { VL_SIG64(Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0); - VL_SIG(Vortex__DOT__in_cache_driver_out_data[2],31,0); VL_SIG8(Vortex__DOT__fetch_valid[2],0,0); VL_SIG8(Vortex__DOT__f_d_valid[2],0,0); - VL_SIG(Vortex__DOT__decode_reg_data[4],31,0); + VL_SIG(Vortex__DOT__decode_a_reg_data[2],31,0); + VL_SIG(Vortex__DOT__decode_b_reg_data[2],31,0); VL_SIG8(Vortex__DOT__decode_valid[2],0,0); - VL_SIG(Vortex__DOT__d_e_reg_data[4],31,0); + VL_SIG(Vortex__DOT__d_e_a_reg_data[2],31,0); + VL_SIG(Vortex__DOT__d_e_b_reg_data[2],31,0); VL_SIG8(Vortex__DOT__d_e_valid[2],0,0); VL_SIG(Vortex__DOT__execute_alu_result[2],31,0); - VL_SIG(Vortex__DOT__execute_reg_data[4],31,0); + VL_SIG(Vortex__DOT__execute_b_reg_data[2],31,0); VL_SIG8(Vortex__DOT__execute_valid[2],0,0); VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0); - VL_SIG(Vortex__DOT__e_m_reg_data[4],31,0); + VL_SIG(Vortex__DOT__e_m_b_reg_data[2],31,0); VL_SIG8(Vortex__DOT__e_m_valid[2],0,0); VL_SIG(Vortex__DOT__memory_alu_result[2],31,0); VL_SIG(Vortex__DOT__memory_mem_result[2],31,0); @@ -137,18 +137,19 @@ VL_MODULE(VVortex) { VL_SIG(Vortex__DOT__writeback_write_data[2],31,0); VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0); VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0); - VL_SIG(Vortex__DOT__use_rd2[2],31,0); VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0); VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[2],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[2],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers[32],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers[32],31,0); - VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2],31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2],31,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0); - VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2],31,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[2],0,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0); - VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[2],31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[2],31,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[2],0,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0); @@ -162,70 +163,77 @@ VL_MODULE(VVortex) { // LOCAL VARIABLES // Internals; generally not touched by application code - // Begin mtask footprint all: - VL_SIG8(__Vtableidx1,2,0); - VL_SIG8(__Vclklast__TOP__clk,0,0); - VL_SIG8(__Vclklast__TOP__reset,0,0); - VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data,31,0); - VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data,31,0); - VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data,31,0); - VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data,31,0); - VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result,31,0); - VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result,31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[4],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[4],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[4],31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[4],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[4],31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[4],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[4],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0); - VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0); - VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[2],0,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0); - VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data[2],31,0); - VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data[2],31,0); + // Anonymous structures to workaround compiler member-count bugs + struct { + // Begin mtask footprint all: + VL_SIG8(__Vtableidx1,2,0); + VL_SIG8(__Vclklast__TOP__clk,0,0); + VL_SIG8(__Vclklast__TOP__reset,0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result,31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[2],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0); + }; + struct { + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0); + }; static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0); // INTERNAL VARIABLES @@ -260,7 +268,7 @@ VL_MODULE(VVortex) { private: static QData _change_request(VVortex__Syms* __restrict vlSymsp); public: - static void _combo__TOP__4(VVortex__Syms* __restrict vlSymsp); + static void _combo__TOP__3(VVortex__Syms* __restrict vlSymsp); static void _combo__TOP__9(VVortex__Syms* __restrict vlSymsp); private: void _ctor_var_reset(); @@ -276,9 +284,9 @@ VL_MODULE(VVortex) { static void _initial__TOP__6(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__1(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp); - static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp); - static void _settle__TOP__5(VVortex__Syms* __restrict vlSymsp); + static void _settle__TOP__4(VVortex__Syms* __restrict vlSymsp); static void _settle__TOP__8(VVortex__Syms* __restrict vlSymsp); } VL_ATTR_ALIGNED(128); diff --git a/rtl/obj_dir/VVortex__ALL.a b/rtl/obj_dir/VVortex__ALL.a index 2aff68e8..aca83764 100644 Binary files a/rtl/obj_dir/VVortex__ALL.a and b/rtl/obj_dir/VVortex__ALL.a differ diff --git a/rtl/obj_dir/VVortex__ALLcls.o b/rtl/obj_dir/VVortex__ALLcls.o index ec788c9d..a543a6ab 100644 Binary files a/rtl/obj_dir/VVortex__ALLcls.o and b/rtl/obj_dir/VVortex__ALLcls.o differ diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat index 6b47170d..d6d4f082 100644 --- a/rtl/obj_dir/VVortex__verFiles.dat +++ b/rtl/obj_dir/VVortex__verFiles.dat @@ -1,26 +1,26 @@ # DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp" S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" -S 2869 12889318286 1553929158 0 1553929158 0 "VX_alu.v" +S 2862 12889318286 1553966962 0 1553966962 0 "VX_alu.v" S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v" -S 4780 12889318287 1553672988 0 1553672988 0 "VX_d_e_reg.v" -S 11922 12889419225 1553929867 0 1553929867 0 "VX_decode.v" +S 5040 12889318287 1553995422 0 1553995422 0 "VX_d_e_reg.v" +S 11888 12889419225 1553995767 0 1553995767 0 "VX_decode.v" S 1551 12889419227 1553898607 0 1553898607 0 "VX_define.v" -S 3941 12889318289 1553673060 0 1553673060 0 "VX_e_m_reg.v" -S 4044 12889318290 1553932436 0 1553932436 0 "VX_execute.v" +S 4077 12889318289 1553997299 0 1553997299 0 "VX_e_m_reg.v" +S 4908 12889318290 1553997136 0 1553997136 0 "VX_execute.v" S 1382 12889050060 1553673124 0 1553673124 0 "VX_f_d_reg.v" S 4048 12889419228 1553932280 0 1553932280 0 "VX_fetch.v" S 5632 12889086478 1553672336 0 1553672336 0 "VX_forwarding.v" S 1677 12889085814 1553673165 0 1553673165 0 "VX_m_w_reg.v" -S 2973 12889084513 1553931546 0 1553931546 0 "VX_memory.v" +S 3002 12889084513 1553997670 0 1553997670 0 "VX_memory.v" S 1003 12889419229 1553930745 0 1553930745 0 "VX_register_file.v" S 1173 12889419230 1553930874 0 1553930874 0 "VX_writeback.v" -S 15887 12889419231 1553932044 0 1553932044 0 "Vortex.v" -T 187461 12889423037 1553932439 0 1553932439 0 "obj_dir/VVortex.cpp" -T 14542 12889423036 1553932439 0 1553932439 0 "obj_dir/VVortex.h" -T 1800 12889423039 1553932439 0 1553932439 0 "obj_dir/VVortex.mk" -T 530 12889423035 1553932439 0 1553932439 0 "obj_dir/VVortex__Syms.cpp" -T 717 12889423034 1553932439 0 1553932439 0 "obj_dir/VVortex__Syms.h" -T 464 12889423040 1553932439 0 1553932439 0 "obj_dir/VVortex__ver.d" -T 0 0 1553932439 0 1553932439 0 "obj_dir/VVortex__verFiles.dat" -T 1159 12889423038 1553932439 0 1553932439 0 "obj_dir/VVortex_classes.mk" +S 16452 12889419231 1553997933 0 1553997933 0 "Vortex.v" +T 183333 12889432530 1553998021 0 1553998021 0 "obj_dir/VVortex.cpp" +T 14673 12889432529 1553998021 0 1553998021 0 "obj_dir/VVortex.h" +T 1800 12889432532 1553998021 0 1553998021 0 "obj_dir/VVortex.mk" +T 530 12889432528 1553998021 0 1553998021 0 "obj_dir/VVortex__Syms.cpp" +T 717 12889432527 1553998021 0 1553998021 0 "obj_dir/VVortex__Syms.h" +T 464 12889432533 1553998021 0 1553998021 0 "obj_dir/VVortex__ver.d" +T 0 0 1553998021 0 1553998021 0 "obj_dir/VVortex__verFiles.dat" +T 1159 12889432531 1553998021 0 1553998021 0 "obj_dir/VVortex_classes.mk" diff --git a/rtl/obj_dir/debug.txt b/rtl/obj_dir/debug.txt index 7f9de19b..02fdafad 100644 --- a/rtl/obj_dir/debug.txt +++ b/rtl/obj_dir/debug.txt @@ -29418,8 +29418,8 @@ RF: Writing 00000000 to 10 RF: Writing 800020bc to 1 ---- ****** -[800000c0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ffffffff +[800000c0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -29470,8 +29470,8 @@ RF: Writing 00000002 to 28 RF: Writing 800020d4 to 1 ---- ****** -[800000d8] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000000 +[800000d8] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -29527,8 +29527,8 @@ RF: Writing 00000003 to 28 RF: Writing 800020ec to 1 ---- ****** -[800000f0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: fffffff0 +[800000f0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -29579,8 +29579,8 @@ RF: Writing 00000004 to 28 RF: Writing 80002104 to 1 ---- ****** -[80000108] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000000f +[80000108] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -29631,8 +29631,8 @@ RF: Writing 00000005 to 28 RF: Writing 8000211c to 1 ---- ****** -[80000120] WB Data: 80002003 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ffffffff +[80000120] WB Data: 80002003 {babebabe}, to register: 1 [1 0] ---- ****** @@ -29683,8 +29683,8 @@ RF: Writing 00000006 to 28 RF: Writing 80002134 to 1 ---- ****** -[80000138] WB Data: 80002003 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000000 +[80000138] WB Data: 80002003 {babebabe}, to register: 1 [1 0] ---- ****** @@ -29735,8 +29735,8 @@ RF: Writing 00000007 to 28 RF: Writing 8000214c to 1 ---- ****** -[80000150] WB Data: 80002003 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: fffffff0 +[80000150] WB Data: 80002003 {babebabe}, to register: 1 [1 0] ---- ****** @@ -29787,8 +29787,8 @@ RF: Writing 00000008 to 28 RF: Writing 80002164 to 1 ---- ****** -[80000168] WB Data: 80002003 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000000f +[80000168] WB Data: 80002003 {babebabe}, to register: 1 [1 0] ---- ****** @@ -29846,8 +29846,8 @@ RF: Writing 8000217c to 1 RF: Writing 80002000 to 1 ---- ****** -[80000184] WB Data: 80001fe0 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ffffffff +[80000184] WB Data: 80001fe0 {babebabe}, to register: 1 [1 0] ---- ****** @@ -29905,8 +29905,8 @@ RF: Writing 80002198 to 1 RF: Writing 80002000 to 1 ---- ****** -[800001a0] WB Data: 80001ffa {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000000 +[800001a0] WB Data: 80001ffa {babebabe}, to register: 1 [1 0] ---- ****** @@ -29971,8 +29971,8 @@ RF: Writing 00000000 to 4 RF: Writing 800021bc to 1 ---- ****** -[800001c0] WB Data: 80002001 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: fffffff0 +[800001c0] WB Data: 80002001 {babebabe}, to register: 1 [1 0] ---- ****** @@ -30062,8 +30062,8 @@ RF: Writing 00000002 to 5 RF: Writing 800021bc to 1 ---- ****** -[800001c0] WB Data: 80002001 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: fffffff0 +[800001c0] WB Data: 80002001 {babebabe}, to register: 1 [1 0] ---- ****** @@ -30167,8 +30167,8 @@ RF: Writing 00000000 to 4 RF: Writing 800021e8 to 1 ---- ****** -[800001ec] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000000f +[800001ec] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -30259,8 +30259,8 @@ RF: Writing 00000002 to 5 RF: Writing 800021e8 to 1 ---- ****** -[800001ec] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000000f +[800001ec] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -30365,8 +30365,8 @@ RF: Writing 00000000 to 4 RF: Writing 80002218 to 1 ---- ****** -[8000021c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000000 +[8000021c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -30458,8 +30458,8 @@ RF: Writing 00000002 to 5 RF: Writing 80002218 to 1 ---- ****** -[8000021c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000000 +[8000021c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -30565,8 +30565,8 @@ RF: Writing 00000000 to 4 RF: Writing 8000224c to 1 ---- ****** -[80000250] WB Data: 80002001 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: fffffff0 +[80000250] WB Data: 80002001 {babebabe}, to register: 1 [1 0] ---- ****** @@ -30644,8 +30644,8 @@ RF: Writing 00000002 to 5 RF: Writing 8000224c to 1 ---- ****** -[80000250] WB Data: 80002001 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: fffffff0 +[80000250] WB Data: 80002001 {babebabe}, to register: 1 [1 0] ---- ****** @@ -30744,8 +30744,8 @@ RF: Writing 80002274 to 1 RF: Writing 80002002 to 1 ---- ****** -[8000027c] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 0000000f +[8000027c] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -30829,8 +30829,8 @@ RF: Writing 80002274 to 1 RF: Writing 80002002 to 1 ---- ****** -[8000027c] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 0000000f +[8000027c] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -30934,8 +30934,8 @@ RF: Writing 80002000 to 1 ****** ---- ****** -[800002ac] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 00000000 +[800002ac] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -31025,8 +31025,8 @@ RF: Writing 80002000 to 1 ****** ---- ****** -[800002ac] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 00000000 +[800002ac] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -31103,8 +31103,8 @@ RF: Writing 00000002 to 5 RF: Writing 800022c8 to 3 ---- ****** -[800002cc] WB Data: 80002000 {babebabe}, to register: 3 [1 0] MEM: data read from cache_driver: ffffffff +[800002cc] WB Data: 80002000 {babebabe}, to register: 3 [1 0] ---- ****** @@ -31172,8 +31172,8 @@ RF: Writing 00000012 to 28 RF: Writing 800022e4 to 3 ---- ****** -[800002e8] WB Data: 80002000 {babebabe}, to register: 3 [1 0] MEM: data read from cache_driver: ffffffff +[800002e8] WB Data: 80002000 {babebabe}, to register: 3 [1 0] ---- ****** @@ -31546,8 +31546,8 @@ RF: Writing 00000000 to 10 RF: Writing 800020bc to 1 ---- ****** -[800000c0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000ff +[800000c0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -31598,8 +31598,8 @@ RF: Writing 00000002 to 28 RF: Writing 800020d4 to 1 ---- ****** -[800000d8] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000000 +[800000d8] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -31655,8 +31655,8 @@ RF: Writing 00000003 to 28 RF: Writing 800020ec to 1 ---- ****** -[800000f0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000f0 +[800000f0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -31707,8 +31707,8 @@ RF: Writing 00000004 to 28 RF: Writing 80002104 to 1 ---- ****** -[80000108] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000000f +[80000108] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -31759,8 +31759,8 @@ RF: Writing 00000005 to 28 RF: Writing 8000211c to 1 ---- ****** -[80000120] WB Data: 80002003 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000ff +[80000120] WB Data: 80002003 {babebabe}, to register: 1 [1 0] ---- ****** @@ -31811,8 +31811,8 @@ RF: Writing 00000006 to 28 RF: Writing 80002134 to 1 ---- ****** -[80000138] WB Data: 80002003 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000000 +[80000138] WB Data: 80002003 {babebabe}, to register: 1 [1 0] ---- ****** @@ -31863,8 +31863,8 @@ RF: Writing 00000007 to 28 RF: Writing 8000214c to 1 ---- ****** -[80000150] WB Data: 80002003 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000f0 +[80000150] WB Data: 80002003 {babebabe}, to register: 1 [1 0] ---- ****** @@ -31915,8 +31915,8 @@ RF: Writing 00000008 to 28 RF: Writing 80002164 to 1 ---- ****** -[80000168] WB Data: 80002003 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000000f +[80000168] WB Data: 80002003 {babebabe}, to register: 1 [1 0] ---- ****** @@ -31974,8 +31974,8 @@ RF: Writing 8000217c to 1 RF: Writing 80002000 to 1 ---- ****** -[80000184] WB Data: 80001fe0 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000ff +[80000184] WB Data: 80001fe0 {babebabe}, to register: 1 [1 0] ---- ****** @@ -32033,8 +32033,8 @@ RF: Writing 80002198 to 1 RF: Writing 80002000 to 1 ---- ****** -[800001a0] WB Data: 80001ffa {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000000 +[800001a0] WB Data: 80001ffa {babebabe}, to register: 1 [1 0] ---- ****** @@ -32099,8 +32099,8 @@ RF: Writing 00000000 to 4 RF: Writing 800021bc to 1 ---- ****** -[800001c0] WB Data: 80002001 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000f0 +[800001c0] WB Data: 80002001 {babebabe}, to register: 1 [1 0] ---- ****** @@ -32190,8 +32190,8 @@ RF: Writing 00000002 to 5 RF: Writing 800021bc to 1 ---- ****** -[800001c0] WB Data: 80002001 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000f0 +[800001c0] WB Data: 80002001 {babebabe}, to register: 1 [1 0] ---- ****** @@ -32295,8 +32295,8 @@ RF: Writing 00000000 to 4 RF: Writing 800021e8 to 1 ---- ****** -[800001ec] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000000f +[800001ec] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -32387,8 +32387,8 @@ RF: Writing 00000002 to 5 RF: Writing 800021e8 to 1 ---- ****** -[800001ec] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000000f +[800001ec] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -32493,8 +32493,8 @@ RF: Writing 00000000 to 4 RF: Writing 80002218 to 1 ---- ****** -[8000021c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000000 +[8000021c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -32586,8 +32586,8 @@ RF: Writing 00000002 to 5 RF: Writing 80002218 to 1 ---- ****** -[8000021c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000000 +[8000021c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -32693,8 +32693,8 @@ RF: Writing 00000000 to 4 RF: Writing 8000224c to 1 ---- ****** -[80000250] WB Data: 80002001 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000f0 +[80000250] WB Data: 80002001 {babebabe}, to register: 1 [1 0] ---- ****** @@ -32772,8 +32772,8 @@ RF: Writing 00000002 to 5 RF: Writing 8000224c to 1 ---- ****** -[80000250] WB Data: 80002001 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000f0 +[80000250] WB Data: 80002001 {babebabe}, to register: 1 [1 0] ---- ****** @@ -32872,8 +32872,8 @@ RF: Writing 80002274 to 1 RF: Writing 80002002 to 1 ---- ****** -[8000027c] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 0000000f +[8000027c] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -32957,8 +32957,8 @@ RF: Writing 80002274 to 1 RF: Writing 80002002 to 1 ---- ****** -[8000027c] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 0000000f +[8000027c] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -33062,8 +33062,8 @@ RF: Writing 80002000 to 1 ****** ---- ****** -[800002ac] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 00000000 +[800002ac] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -33153,8 +33153,8 @@ RF: Writing 80002000 to 1 ****** ---- ****** -[800002ac] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 00000000 +[800002ac] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -33231,8 +33231,8 @@ RF: Writing 00000002 to 5 RF: Writing 800022c8 to 3 ---- ****** -[800002cc] WB Data: 80002000 {babebabe}, to register: 3 [1 0] MEM: data read from cache_driver: 000000ff +[800002cc] WB Data: 80002000 {babebabe}, to register: 3 [1 0] ---- ****** @@ -33300,8 +33300,8 @@ RF: Writing 00000012 to 28 RF: Writing 800022e4 to 3 ---- ****** -[800002e8] WB Data: 80002000 {babebabe}, to register: 3 [1 0] MEM: data read from cache_driver: 000000ff +[800002e8] WB Data: 80002000 {babebabe}, to register: 3 [1 0] ---- ****** @@ -33674,8 +33674,8 @@ RF: Writing 00000000 to 10 RF: Writing 800020bc to 1 ---- ****** -[800000c0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000ff +[800000c0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -33726,8 +33726,8 @@ RF: Writing 00000002 to 28 RF: Writing 800020d4 to 1 ---- ****** -[800000d8] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ffffff00 +[800000d8] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -33783,8 +33783,8 @@ RF: Writing 00000003 to 28 RF: Writing 800020ec to 1 ---- ****** -[800000f0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[800000f0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -33842,8 +33842,8 @@ RF: Writing 00000004 to 28 RF: Writing 80002108 to 1 ---- ****** -[8000010c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: fffff00f +[8000010c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -33901,8 +33901,8 @@ RF: Writing 00000005 to 28 RF: Writing 80002124 to 1 ---- ****** -[80000128] WB Data: 80002006 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000ff +[80000128] WB Data: 80002006 {babebabe}, to register: 1 [1 0] ---- ****** @@ -33953,8 +33953,8 @@ RF: Writing 00000006 to 28 RF: Writing 8000213c to 1 ---- ****** -[80000140] WB Data: 80002006 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ffffff00 +[80000140] WB Data: 80002006 {babebabe}, to register: 1 [1 0] ---- ****** @@ -34005,8 +34005,8 @@ RF: Writing 00000007 to 28 RF: Writing 80002154 to 1 ---- ****** -[80000158] WB Data: 80002006 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[80000158] WB Data: 80002006 {babebabe}, to register: 1 [1 0] ---- ****** @@ -34064,8 +34064,8 @@ RF: Writing 00000008 to 28 RF: Writing 80002170 to 1 ---- ****** -[80000174] WB Data: 80002006 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: fffff00f +[80000174] WB Data: 80002006 {babebabe}, to register: 1 [1 0] ---- ****** @@ -34130,8 +34130,8 @@ RF: Writing 8000218c to 1 RF: Writing 80002000 to 1 ---- ****** -[80000194] WB Data: 80001fe0 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000ff +[80000194] WB Data: 80001fe0 {babebabe}, to register: 1 [1 0] ---- ****** @@ -34189,8 +34189,8 @@ RF: Writing 800021a8 to 1 RF: Writing 80002000 to 1 ---- ****** -[800001b0] WB Data: 80001ffb {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ffffff00 +[800001b0] WB Data: 80001ffb {babebabe}, to register: 1 [1 0] ---- ****** @@ -34255,8 +34255,8 @@ RF: Writing 00000000 to 4 RF: Writing 800021cc to 1 ---- ****** -[800001d0] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[800001d0] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -34353,8 +34353,8 @@ RF: Writing 00000002 to 5 RF: Writing 800021cc to 1 ---- ****** -[800001d0] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[800001d0] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -34465,8 +34465,8 @@ RF: Writing 00000000 to 4 RF: Writing 800021fc to 1 ---- ****** -[80000200] WB Data: 80002004 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: fffff00f +[80000200] WB Data: 80002004 {babebabe}, to register: 1 [1 0] ---- ****** @@ -34564,8 +34564,8 @@ RF: Writing 00000002 to 5 RF: Writing 800021fc to 1 ---- ****** -[80000200] WB Data: 80002004 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: fffff00f +[80000200] WB Data: 80002004 {babebabe}, to register: 1 [1 0] ---- ****** @@ -34677,8 +34677,8 @@ RF: Writing 00000000 to 4 RF: Writing 80002230 to 1 ---- ****** -[80000234] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ffffff00 +[80000234] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -34770,8 +34770,8 @@ RF: Writing 00000002 to 5 RF: Writing 80002230 to 1 ---- ****** -[80000234] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ffffff00 +[80000234] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -34877,8 +34877,8 @@ RF: Writing 00000000 to 4 RF: Writing 80002264 to 1 ---- ****** -[80000268] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[80000268] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -34958,8 +34958,8 @@ RF: Writing 00000002 to 5 RF: Writing 80002264 to 1 ---- ****** -[80000268] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[80000268] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -35060,8 +35060,8 @@ RF: Writing 80002290 to 1 RF: Writing 80002004 to 1 ---- ****** -[80000298] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: fffff00f +[80000298] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -35147,8 +35147,8 @@ RF: Writing 80002290 to 1 RF: Writing 80002004 to 1 ---- ****** -[80000298] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: fffff00f +[80000298] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -35254,8 +35254,8 @@ RF: Writing 80002000 to 1 ****** ---- ****** -[800002cc] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: ffffff00 +[800002cc] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -35345,8 +35345,8 @@ RF: Writing 80002000 to 1 ****** ---- ****** -[800002cc] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: ffffff00 +[800002cc] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -35423,8 +35423,8 @@ RF: Writing 00000002 to 5 RF: Writing 800022e8 to 3 ---- ****** -[800002ec] WB Data: 80002000 {babebabe}, to register: 3 [1 0] MEM: data read from cache_driver: 000000ff +[800002ec] WB Data: 80002000 {babebabe}, to register: 3 [1 0] ---- ****** @@ -35492,8 +35492,8 @@ RF: Writing 00000012 to 28 RF: Writing 80002304 to 3 ---- ****** -[80000308] WB Data: 80002000 {babebabe}, to register: 3 [1 0] MEM: data read from cache_driver: 000000ff +[80000308] WB Data: 80002000 {babebabe}, to register: 3 [1 0] ---- ****** @@ -35866,8 +35866,8 @@ RF: Writing 00000000 to 10 RF: Writing 800020bc to 1 ---- ****** -[800000c0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000ff +[800000c0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -35918,8 +35918,8 @@ RF: Writing 00000002 to 28 RF: Writing 800020d4 to 1 ---- ****** -[800000d8] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000ff00 +[800000d8] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -35977,8 +35977,8 @@ RF: Writing 00000003 to 28 RF: Writing 800020f0 to 1 ---- ****** -[800000f4] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[800000f4] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36036,8 +36036,8 @@ RF: Writing 00000004 to 28 RF: Writing 8000210c to 1 ---- ****** -[80000110] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000f00f +[80000110] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36095,8 +36095,8 @@ RF: Writing 00000005 to 28 RF: Writing 80002128 to 1 ---- ****** -[8000012c] WB Data: 80002006 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000ff +[8000012c] WB Data: 80002006 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36147,8 +36147,8 @@ RF: Writing 00000006 to 28 RF: Writing 80002140 to 1 ---- ****** -[80000144] WB Data: 80002006 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000ff00 +[80000144] WB Data: 80002006 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36206,8 +36206,8 @@ RF: Writing 00000007 to 28 RF: Writing 8000215c to 1 ---- ****** -[80000160] WB Data: 80002006 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[80000160] WB Data: 80002006 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36265,8 +36265,8 @@ RF: Writing 00000008 to 28 RF: Writing 80002178 to 1 ---- ****** -[8000017c] WB Data: 80002006 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000f00f +[8000017c] WB Data: 80002006 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36331,8 +36331,8 @@ RF: Writing 80002194 to 1 RF: Writing 80002000 to 1 ---- ****** -[8000019c] WB Data: 80001fe0 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 000000ff +[8000019c] WB Data: 80001fe0 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36390,8 +36390,8 @@ RF: Writing 800021b0 to 1 RF: Writing 80002000 to 1 ---- ****** -[800001b8] WB Data: 80001ffb {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000ff00 +[800001b8] WB Data: 80001ffb {babebabe}, to register: 1 [1 0] ---- ****** @@ -36463,8 +36463,8 @@ RF: Writing 00000000 to 4 RF: Writing 800021d8 to 1 ---- ****** -[800001dc] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[800001dc] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36561,8 +36561,8 @@ RF: Writing 00000002 to 5 RF: Writing 800021d8 to 1 ---- ****** -[800001dc] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[800001dc] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36673,8 +36673,8 @@ RF: Writing 00000000 to 4 RF: Writing 80002208 to 1 ---- ****** -[8000020c] WB Data: 80002004 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000f00f +[8000020c] WB Data: 80002004 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36772,8 +36772,8 @@ RF: Writing 00000002 to 5 RF: Writing 80002208 to 1 ---- ****** -[8000020c] WB Data: 80002004 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000f00f +[8000020c] WB Data: 80002004 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36885,8 +36885,8 @@ RF: Writing 00000000 to 4 RF: Writing 8000223c to 1 ---- ****** -[80000240] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000ff00 +[80000240] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -36985,8 +36985,8 @@ RF: Writing 00000002 to 5 RF: Writing 8000223c to 1 ---- ****** -[80000240] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0000ff00 +[80000240] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- ****** @@ -37099,8 +37099,8 @@ RF: Writing 00000000 to 4 RF: Writing 80002274 to 1 ---- ****** -[80000278] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[80000278] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -37180,8 +37180,8 @@ RF: Writing 00000002 to 5 RF: Writing 80002274 to 1 ---- ****** -[80000278] WB Data: 80002002 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00000ff0 +[80000278] WB Data: 80002002 {babebabe}, to register: 1 [1 0] ---- ****** @@ -37282,8 +37282,8 @@ RF: Writing 800022a0 to 1 RF: Writing 80002004 to 1 ---- ****** -[800002a8] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 0000f00f +[800002a8] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -37369,8 +37369,8 @@ RF: Writing 800022a0 to 1 RF: Writing 80002004 to 1 ---- ****** -[800002a8] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 0000f00f +[800002a8] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -37476,8 +37476,8 @@ RF: Writing 80002000 to 1 ****** ---- ****** -[800002dc] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 0000ff00 +[800002dc] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -37569,8 +37569,8 @@ RF: Writing 80002000 to 1 ****** ---- ****** -[800002dc] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: 0000ff00 +[800002dc] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- ****** @@ -37649,8 +37649,8 @@ RF: Writing 00000002 to 5 RF: Writing 800022fc to 3 ---- ****** -[80000300] WB Data: 80002000 {babebabe}, to register: 3 [1 0] MEM: data read from cache_driver: 000000ff +[80000300] WB Data: 80002000 {babebabe}, to register: 3 [1 0] ---- ****** @@ -37718,8 +37718,8 @@ RF: Writing 00000012 to 28 RF: Writing 80002318 to 3 ---- ****** -[8000031c] WB Data: 80002000 {babebabe}, to register: 3 [1 0] MEM: data read from cache_driver: 000000ff +[8000031c] WB Data: 80002000 {babebabe}, to register: 3 [1 0] ---- ****** @@ -38594,12 +38594,16 @@ RF: Writing 00000000 to 10 ---- ****** RF: Writing 800020bc to 1 +PC: 800000c4 ----> Received: babebabe for addr: 80002000 ---- +READING - Addr: 80002000 = ff00ff ****** -[800000c0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00ff00ff +PC: 800000c4 ----> Received: 00ff00ff for addr: 80002000 +[800000c0] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002000 = ff00ff ****** RF: Writing 80002000 to 1 MEM: data read from cache_driver: 00ff00ff @@ -38653,12 +38657,16 @@ RF: Writing 00000002 to 28 ---- ****** RF: Writing 800020d8 to 1 +PC: 800000e0 ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = ff00ff00 ****** -[800000dc] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ff00ff00 +PC: 800000e0 ----> Received: ff00ff00 for addr: 80002004 +[800000dc] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002004 = ff00ff00 ****** RF: Writing 80002000 to 1 MEM: data read from cache_driver: ff00ff00 @@ -38712,12 +38720,16 @@ RF: Writing 00000003 to 28 ---- ****** RF: Writing 800020f4 to 1 +PC: 800000fc ----> Received: babebabe for addr: 80002008 ---- +READING - Addr: 80002008 = ff00ff0 ****** -[800000f8] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0ff00ff0 +PC: 800000fc ----> Received: 0ff00ff0 for addr: 80002008 +[800000f8] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002008 = ff00ff0 ****** RF: Writing 80002000 to 1 MEM: data read from cache_driver: 0ff00ff0 @@ -38771,12 +38783,16 @@ RF: Writing 00000004 to 28 ---- ****** RF: Writing 80002110 to 1 +PC: 80000118 ----> Received: babebabe for addr: 8000200c ---- +READING - Addr: 8000200c = f00ff00f ****** -[80000114] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: f00ff00f +PC: 80000118 ----> Received: f00ff00f for addr: 8000200c +[80000114] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 8000200c = f00ff00f ****** RF: Writing 80002000 to 1 MEM: data read from cache_driver: f00ff00f @@ -38830,12 +38846,16 @@ RF: Writing 00000005 to 28 ---- ****** RF: Writing 8000212c to 1 +PC: 80000134 ----> Received: babebabe for addr: 80002000 ---- +READING - Addr: 80002000 = ff00ff ****** -[80000130] WB Data: 8000200c {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00ff00ff +PC: 80000134 ----> Received: 00ff00ff for addr: 80002000 +[80000130] WB Data: 8000200c {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002000 = ff00ff ****** RF: Writing 8000200c to 1 MEM: data read from cache_driver: 00ff00ff @@ -38889,12 +38909,16 @@ RF: Writing 00000006 to 28 ---- ****** RF: Writing 80002148 to 1 +PC: 80000150 ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = ff00ff00 ****** -[8000014c] WB Data: 8000200c {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ff00ff00 +PC: 80000150 ----> Received: ff00ff00 for addr: 80002004 +[8000014c] WB Data: 8000200c {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002004 = ff00ff00 ****** RF: Writing 8000200c to 1 MEM: data read from cache_driver: ff00ff00 @@ -38948,12 +38972,16 @@ RF: Writing 00000007 to 28 ---- ****** RF: Writing 80002164 to 1 +PC: 8000016c ----> Received: babebabe for addr: 80002008 ---- +READING - Addr: 80002008 = ff00ff0 ****** -[80000168] WB Data: 8000200c {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0ff00ff0 +PC: 8000016c ----> Received: 0ff00ff0 for addr: 80002008 +[80000168] WB Data: 8000200c {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002008 = ff00ff0 ****** RF: Writing 8000200c to 1 MEM: data read from cache_driver: 0ff00ff0 @@ -39007,12 +39035,16 @@ RF: Writing 00000008 to 28 ---- ****** RF: Writing 80002180 to 1 +PC: 80000188 ----> Received: babebabe for addr: 8000200c ---- +READING - Addr: 8000200c = f00ff00f ****** -[80000184] WB Data: 8000200c {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: f00ff00f +PC: 80000188 ----> Received: f00ff00f for addr: 8000200c +[80000184] WB Data: 8000200c {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 8000200c = f00ff00f ****** RF: Writing 8000200c to 1 MEM: data read from cache_driver: f00ff00f @@ -39073,12 +39105,16 @@ RF: Writing 8000219c to 1 ---- ****** RF: Writing 80002000 to 1 +PC: 800001a8 ----> Received: babebabe for addr: 80002000 ---- +READING - Addr: 80002000 = ff00ff ****** -[800001a4] WB Data: 80001fe0 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 00ff00ff +PC: 800001a8 ----> Received: 00ff00ff for addr: 80002000 +[800001a4] WB Data: 80001fe0 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002000 = ff00ff ****** RF: Writing 80001fe0 to 1 MEM: data read from cache_driver: 00ff00ff @@ -39139,12 +39175,16 @@ RF: Writing 800021bc to 1 ---- ****** RF: Writing 80002000 to 1 +PC: 800001c8 ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = ff00ff00 ****** -[800001c4] WB Data: 80001ffd {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ff00ff00 +PC: 800001c8 ----> Received: ff00ff00 for addr: 80002004 +[800001c4] WB Data: 80001ffd {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002004 = ff00ff00 ****** RF: Writing 80001ffd to 1 MEM: data read from cache_driver: ff00ff00 @@ -39212,12 +39252,16 @@ RF: Writing 00000000 to 4 ---- ****** RF: Writing 800021e4 to 1 +PC: 800001ec ----> Received: babebabe for addr: 80002008 ---- +READING - Addr: 80002008 = ff00ff0 ****** -[800001e8] WB Data: 80002004 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0ff00ff0 +PC: 800001ec ----> Received: 0ff00ff0 for addr: 80002008 +[800001e8] WB Data: 80002004 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002008 = ff00ff0 ****** RF: Writing 80002004 to 1 MEM: data read from cache_driver: 0ff00ff0 @@ -39310,12 +39354,16 @@ RF: Writing 00000002 to 5 ---- ****** RF: Writing 800021e4 to 1 +PC: 800001ec ----> Received: babebabe for addr: 80002008 ---- +READING - Addr: 80002008 = ff00ff0 ****** -[800001e8] WB Data: 80002004 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0ff00ff0 +PC: 800001ec ----> Received: 0ff00ff0 for addr: 80002008 +[800001e8] WB Data: 80002004 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002008 = ff00ff0 ****** RF: Writing 80002004 to 1 MEM: data read from cache_driver: 0ff00ff0 @@ -39422,12 +39470,16 @@ RF: Writing 00000000 to 4 ---- ****** RF: Writing 80002214 to 1 +PC: 8000021c ----> Received: babebabe for addr: 8000200c ---- +READING - Addr: 8000200c = f00ff00f ****** -[80000218] WB Data: 80002008 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: f00ff00f +PC: 8000021c ----> Received: f00ff00f for addr: 8000200c +[80000218] WB Data: 80002008 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 8000200c = f00ff00f ****** RF: Writing 80002008 to 1 MEM: data read from cache_driver: f00ff00f @@ -39521,12 +39573,16 @@ RF: Writing 00000002 to 5 ---- ****** RF: Writing 80002214 to 1 +PC: 8000021c ----> Received: babebabe for addr: 8000200c ---- +READING - Addr: 8000200c = f00ff00f ****** -[80000218] WB Data: 80002008 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: f00ff00f +PC: 8000021c ----> Received: f00ff00f for addr: 8000200c +[80000218] WB Data: 80002008 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 8000200c = f00ff00f ****** RF: Writing 80002008 to 1 MEM: data read from cache_driver: f00ff00f @@ -39634,12 +39690,16 @@ RF: Writing 00000000 to 4 ---- ****** RF: Writing 80002248 to 1 +PC: 80000250 ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = ff00ff00 ****** -[8000024c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ff00ff00 +PC: 80000250 ----> Received: ff00ff00 for addr: 80002004 +[8000024c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002004 = ff00ff00 ****** RF: Writing 80002000 to 1 MEM: data read from cache_driver: ff00ff00 @@ -39734,12 +39794,16 @@ RF: Writing 00000002 to 5 ---- ****** RF: Writing 80002248 to 1 +PC: 80000250 ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = ff00ff00 ****** -[8000024c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: ff00ff00 +PC: 80000250 ----> Received: ff00ff00 for addr: 80002004 +[8000024c] WB Data: 80002000 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002004 = ff00ff00 ****** RF: Writing 80002000 to 1 MEM: data read from cache_driver: ff00ff00 @@ -39848,12 +39912,16 @@ RF: Writing 00000000 to 4 ---- ****** RF: Writing 80002280 to 1 +PC: 80000288 ----> Received: babebabe for addr: 80002008 ---- +READING - Addr: 80002008 = ff00ff0 ****** -[80000284] WB Data: 80002004 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0ff00ff0 +PC: 80000288 ----> Received: 0ff00ff0 for addr: 80002008 +[80000284] WB Data: 80002004 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002008 = ff00ff0 ****** RF: Writing 80002004 to 1 MEM: data read from cache_driver: 0ff00ff0 @@ -39929,12 +39997,16 @@ RF: Writing 00000002 to 5 ---- ****** RF: Writing 80002280 to 1 +PC: 80000288 ----> Received: babebabe for addr: 80002008 ---- +READING - Addr: 80002008 = ff00ff0 ****** -[80000284] WB Data: 80002004 {babebabe}, to register: 1 [1 0] MEM: data read from cache_driver: 0ff00ff0 +PC: 80000288 ----> Received: 0ff00ff0 for addr: 80002008 +[80000284] WB Data: 80002004 {babebabe}, to register: 1 [1 0] ---- +READING - Addr: 80002008 = ff00ff0 ****** RF: Writing 80002004 to 1 MEM: data read from cache_driver: 0ff00ff0 @@ -40031,12 +40103,16 @@ RF: Writing 800022ac to 1 ---- ****** RF: Writing 80002008 to 1 +PC: 800002b8 ----> Received: babebabe for addr: 8000200c ---- +READING - Addr: 8000200c = f00ff00f ****** -[800002b4] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: f00ff00f +PC: 800002b8 ----> Received: f00ff00f for addr: 8000200c +[800002b4] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- +READING - Addr: 8000200c = f00ff00f ****** MEM: data read from cache_driver: f00ff00f ---- @@ -40118,12 +40194,16 @@ RF: Writing 800022ac to 1 ---- ****** RF: Writing 80002008 to 1 +PC: 800002b8 ----> Received: babebabe for addr: 8000200c ---- +READING - Addr: 8000200c = f00ff00f ****** -[800002b4] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: f00ff00f +PC: 800002b8 ----> Received: f00ff00f for addr: 8000200c +[800002b4] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- +READING - Addr: 8000200c = f00ff00f ****** MEM: data read from cache_driver: f00ff00f ---- @@ -40225,12 +40305,16 @@ RF: Writing 80002000 to 1 ---- ****** +PC: 800002ec ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = ff00ff00 ****** -[800002e8] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: ff00ff00 +PC: 800002ec ----> Received: ff00ff00 for addr: 80002004 +[800002e8] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- +READING - Addr: 80002004 = ff00ff00 ****** MEM: data read from cache_driver: ff00ff00 ---- @@ -40318,12 +40402,16 @@ RF: Writing 80002000 to 1 ---- ****** +PC: 800002ec ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = ff00ff00 ****** -[800002e8] WB Data: 00000000 {babebabe}, to register: 0 [1 0] MEM: data read from cache_driver: ff00ff00 +PC: 800002ec ----> Received: ff00ff00 for addr: 80002004 +[800002e8] WB Data: 00000000 {babebabe}, to register: 0 [1 0] ---- +READING - Addr: 80002004 = ff00ff00 ****** MEM: data read from cache_driver: ff00ff00 ---- @@ -40398,12 +40486,16 @@ RF: Writing 00000002 to 5 ---- ****** RF: Writing 80002308 to 3 +PC: 80000310 ----> Received: babebabe for addr: 80002000 ---- +READING - Addr: 80002000 = ff00ff ****** -[8000030c] WB Data: 80002000 {babebabe}, to register: 3 [1 0] MEM: data read from cache_driver: 00ff00ff +PC: 80000310 ----> Received: 00ff00ff for addr: 80002000 +[8000030c] WB Data: 80002000 {babebabe}, to register: 3 [1 0] ---- +READING - Addr: 80002000 = ff00ff ****** RF: Writing 80002000 to 3 MEM: data read from cache_driver: 00ff00ff @@ -40467,12 +40559,16 @@ RF: Writing 00000012 to 28 ---- ****** RF: Writing 80002324 to 3 +PC: 8000032c ----> Received: babebabe for addr: 80002000 ---- +READING - Addr: 80002000 = ff00ff ****** -[80000328] WB Data: 80002000 {babebabe}, to register: 3 [1 0] MEM: data read from cache_driver: 00ff00ff +PC: 8000032c ----> Received: 00ff00ff for addr: 80002000 +[80000328] WB Data: 80002000 {babebabe}, to register: 3 [1 0] ---- +READING - Addr: 80002000 = ff00ff ****** RF: Writing 80002000 to 3 MEM: data read from cache_driver: 00ff00ff @@ -46959,8 +47055,8 @@ RF: Writing 80002002 to 1 RF: Writing 80002204 to 4 ---- ****** -[80000208] WB Data: 80002009 {babebabe}, to register: 4 [1 0] MEM: data read from cache_driver: ffffff98 +[80000208] WB Data: 80002009 {babebabe}, to register: 4 [1 0] ---- ****** @@ -50056,11 +50152,15 @@ RF: Writing beef1000 to 2 ---- ****** RF: Writing beef0aa0 to 2 +PC: 80000118 ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = beef0aa0 ****** MEM: data read from cache_driver: beef0aa0 +PC: 80000118 ----> Received: beef0aa0 for addr: 80002004 ---- +READING - Addr: 80002004 = beef0aa0 ****** MEM: data read from cache_driver: beef0aa0 ---- @@ -50616,8 +50716,8 @@ RF: Writing 8000200b to 1 RF: Writing 80002230 to 4 ---- ****** -[80000234] WB Data: 80002012 {babebabe}, to register: 4 [1 0] MEM: data read from cache_driver: 00003098 +[80000234] WB Data: 80002012 {babebabe}, to register: 4 [1 0] ---- ****** @@ -87376,11 +87476,15 @@ STORING aa00aa in 80002000 ---- ****** RF: Writing 00aa00aa to 2 +PC: 800000d0 ----> Received: babebabe for addr: 80002000 ---- +READING - Addr: 80002000 = aa00aa ****** MEM: data read from cache_driver: 00aa00aa +PC: 800000d0 ----> Received: 00aa00aa for addr: 80002000 ---- +READING - Addr: 80002000 = aa00aa ****** MEM: data read from cache_driver: 00aa00aa ---- @@ -87456,11 +87560,15 @@ STORING aa00aa00 in 80002004 ---- ****** RF: Writing aa00aa00 to 2 +PC: 800000f8 ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = aa00aa00 ****** MEM: data read from cache_driver: aa00aa00 +PC: 800000f8 ----> Received: aa00aa00 for addr: 80002004 ---- +READING - Addr: 80002004 = aa00aa00 ****** MEM: data read from cache_driver: aa00aa00 ---- @@ -87536,11 +87644,15 @@ STORING aa00aa0 in 80002008 ---- ****** RF: Writing 0aa00aa0 to 2 +PC: 80000120 ----> Received: babebabe for addr: 80002008 ---- +READING - Addr: 80002008 = aa00aa0 ****** MEM: data read from cache_driver: 0aa00aa0 +PC: 80000120 ----> Received: 0aa00aa0 for addr: 80002008 ---- +READING - Addr: 80002008 = aa00aa0 ****** MEM: data read from cache_driver: 0aa00aa0 ---- @@ -87616,11 +87728,15 @@ STORING a00aa00a in 8000200c ---- ****** RF: Writing a00aa00a to 2 +PC: 80000148 ----> Received: babebabe for addr: 8000200c ---- +READING - Addr: 8000200c = a00aa00a ****** MEM: data read from cache_driver: a00aa00a +PC: 80000148 ----> Received: a00aa00a for addr: 8000200c ---- +READING - Addr: 8000200c = a00aa00a ****** MEM: data read from cache_driver: a00aa00a ---- @@ -87696,11 +87812,15 @@ STORING aa00aa in 80002010 ---- ****** RF: Writing 00aa00aa to 2 +PC: 80000170 ----> Received: babebabe for addr: 80002010 ---- +READING - Addr: 80002010 = aa00aa ****** MEM: data read from cache_driver: 00aa00aa +PC: 80000170 ----> Received: 00aa00aa for addr: 80002010 ---- +READING - Addr: 80002010 = aa00aa ****** MEM: data read from cache_driver: 00aa00aa ---- @@ -87776,11 +87896,15 @@ STORING aa00aa00 in 80002014 ---- ****** RF: Writing aa00aa00 to 2 +PC: 80000198 ----> Received: babebabe for addr: 80002014 ---- +READING - Addr: 80002014 = aa00aa00 ****** MEM: data read from cache_driver: aa00aa00 +PC: 80000198 ----> Received: aa00aa00 for addr: 80002014 ---- +READING - Addr: 80002014 = aa00aa00 ****** MEM: data read from cache_driver: aa00aa00 ---- @@ -87856,11 +87980,15 @@ STORING aa00aa0 in 80002018 ---- ****** RF: Writing 0aa00aa0 to 2 +PC: 800001c0 ----> Received: babebabe for addr: 80002018 ---- +READING - Addr: 80002018 = aa00aa0 ****** MEM: data read from cache_driver: 0aa00aa0 +PC: 800001c0 ----> Received: 0aa00aa0 for addr: 80002018 ---- +READING - Addr: 80002018 = aa00aa0 ****** MEM: data read from cache_driver: 0aa00aa0 ---- @@ -87936,11 +88064,15 @@ STORING a00aa00a in 8000201c ---- ****** RF: Writing a00aa00a to 2 +PC: 800001e8 ----> Received: babebabe for addr: 8000201c ---- +READING - Addr: 8000201c = a00aa00a ****** MEM: data read from cache_driver: a00aa00a +PC: 800001e8 ----> Received: a00aa00a for addr: 8000201c ---- +READING - Addr: 8000201c = a00aa00a ****** MEM: data read from cache_driver: a00aa00a ---- @@ -88023,11 +88155,15 @@ STORING 12345678 in 80002020 ---- ****** RF: Writing 80002000 to 4 +PC: 80000214 ----> Received: babebabe for addr: 80002020 ---- +READING - Addr: 80002020 = 12345678 ****** MEM: data read from cache_driver: 12345678 +PC: 80000214 ----> Received: 12345678 for addr: 80002020 ---- +READING - Addr: 80002020 = 12345678 ****** MEM: data read from cache_driver: 12345678 ---- @@ -88132,12 +88268,16 @@ RF: Writing 8000201d to 1 ---- ****** RF: Writing 80002240 to 4 +PC: 80000248 ----> Received: babebabe for addr: 80002024 ---- +READING - Addr: 80002024 = 58213098 ****** -[80000244] WB Data: 80002024 {babebabe}, to register: 4 [1 0] MEM: data read from cache_driver: 58213098 +PC: 80000248 ----> Received: 58213098 for addr: 80002024 +[80000244] WB Data: 80002024 {babebabe}, to register: 4 [1 0] ---- +READING - Addr: 80002024 = 58213098 ****** RF: Writing 80002024 to 4 MEM: data read from cache_driver: 58213098 @@ -88228,11 +88368,15 @@ STORING aabbccdd in 80002000 ---- ****** RF: Writing 80002000 to 2 +PC: 80000278 ----> Received: babebabe for addr: 80002000 ---- +READING - Addr: 80002000 = aabbccdd ****** MEM: data read from cache_driver: aabbccdd +PC: 80000278 ----> Received: aabbccdd for addr: 80002000 ---- +READING - Addr: 80002000 = aabbccdd ****** MEM: data read from cache_driver: aabbccdd ---- @@ -88330,11 +88474,15 @@ STORING aabbccdd in 80002000 ---- ****** RF: Writing 80002000 to 2 +PC: 80000278 ----> Received: babebabe for addr: 80002000 ---- +READING - Addr: 80002000 = aabbccdd ****** MEM: data read from cache_driver: aabbccdd +PC: 80000278 ----> Received: aabbccdd for addr: 80002000 ---- +READING - Addr: 80002000 = aabbccdd ****** MEM: data read from cache_driver: aabbccdd ---- @@ -88452,11 +88600,15 @@ STORING daabbccd in 80002004 STORING daabbccd in 80002004 ---- ****** +PC: 800002b4 ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = daabbccd ****** MEM: data read from cache_driver: daabbccd +PC: 800002b4 ----> Received: daabbccd for addr: 80002004 ---- +READING - Addr: 80002004 = daabbccd ****** MEM: data read from cache_driver: daabbccd ---- @@ -88560,11 +88712,15 @@ STORING daabbccd in 80002004 STORING daabbccd in 80002004 ---- ****** +PC: 800002b4 ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = daabbccd ****** MEM: data read from cache_driver: daabbccd +PC: 800002b4 ----> Received: daabbccd for addr: 80002004 ---- +READING - Addr: 80002004 = daabbccd ****** MEM: data read from cache_driver: daabbccd ---- @@ -88688,11 +88844,15 @@ STORING ddaabbcc in 80002008 STORING ddaabbcc in 80002008 ---- ****** +PC: 800002f4 ----> Received: babebabe for addr: 80002008 ---- +READING - Addr: 80002008 = ddaabbcc ****** MEM: data read from cache_driver: ddaabbcc +PC: 800002f4 ----> Received: ddaabbcc for addr: 80002008 ---- +READING - Addr: 80002008 = ddaabbcc ****** MEM: data read from cache_driver: ddaabbcc ---- @@ -88802,11 +88962,15 @@ STORING ddaabbcc in 80002008 STORING ddaabbcc in 80002008 ---- ****** +PC: 800002f4 ----> Received: babebabe for addr: 80002008 ---- +READING - Addr: 80002008 = ddaabbcc ****** MEM: data read from cache_driver: ddaabbcc +PC: 800002f4 ----> Received: ddaabbcc for addr: 80002008 ---- +READING - Addr: 80002008 = ddaabbcc ****** MEM: data read from cache_driver: ddaabbcc ---- @@ -88924,11 +89088,15 @@ STORING cddaabbc in 8000200c ---- ****** RF: Writing 80002000 to 2 +PC: 80000330 ----> Received: babebabe for addr: 8000200c ---- +READING - Addr: 8000200c = cddaabbc ****** MEM: data read from cache_driver: cddaabbc +PC: 80000330 ----> Received: cddaabbc for addr: 8000200c ---- +READING - Addr: 8000200c = cddaabbc ****** MEM: data read from cache_driver: cddaabbc ---- @@ -89032,11 +89200,15 @@ STORING cddaabbc in 8000200c ---- ****** RF: Writing 80002000 to 2 +PC: 80000330 ----> Received: babebabe for addr: 8000200c ---- +READING - Addr: 8000200c = cddaabbc ****** MEM: data read from cache_driver: cddaabbc +PC: 80000330 ----> Received: cddaabbc for addr: 8000200c ---- +READING - Addr: 8000200c = cddaabbc ****** MEM: data read from cache_driver: cddaabbc ---- @@ -89160,11 +89332,15 @@ STORING ccddaabb in 80002010 STORING ccddaabb in 80002010 ---- ****** +PC: 80000370 ----> Received: babebabe for addr: 80002010 ---- +READING - Addr: 80002010 = ccddaabb ****** MEM: data read from cache_driver: ccddaabb +PC: 80000370 ----> Received: ccddaabb for addr: 80002010 ---- +READING - Addr: 80002010 = ccddaabb ****** MEM: data read from cache_driver: ccddaabb ---- @@ -89274,11 +89450,15 @@ STORING ccddaabb in 80002010 STORING ccddaabb in 80002010 ---- ****** +PC: 80000370 ----> Received: babebabe for addr: 80002010 ---- +READING - Addr: 80002010 = ccddaabb ****** MEM: data read from cache_driver: ccddaabb +PC: 80000370 ----> Received: ccddaabb for addr: 80002010 ---- +READING - Addr: 80002010 = ccddaabb ****** MEM: data read from cache_driver: ccddaabb ---- @@ -89402,11 +89582,15 @@ STORING bccddaab in 80002014 ---- ****** RF: Writing 80002000 to 2 +PC: 800003b0 ----> Received: babebabe for addr: 80002014 ---- +READING - Addr: 80002014 = bccddaab ****** MEM: data read from cache_driver: bccddaab +PC: 800003b0 ----> Received: bccddaab for addr: 80002014 ---- +READING - Addr: 80002014 = bccddaab ****** MEM: data read from cache_driver: bccddaab ---- @@ -89516,11 +89700,15 @@ STORING bccddaab in 80002014 ---- ****** RF: Writing 80002000 to 2 +PC: 800003b0 ----> Received: babebabe for addr: 80002014 ---- +READING - Addr: 80002014 = bccddaab ****** MEM: data read from cache_driver: bccddaab +PC: 800003b0 ----> Received: bccddaab for addr: 80002014 ---- +READING - Addr: 80002014 = bccddaab ****** MEM: data read from cache_driver: bccddaab ---- @@ -89632,11 +89820,15 @@ STORING 112233 in 80002000 ---- ****** RF: Writing 00112233 to 1 +PC: 800003e8 ----> Received: babebabe for addr: 80002000 ---- +READING - Addr: 80002000 = 112233 ****** MEM: data read from cache_driver: 00112233 +PC: 800003e8 ----> Received: 00112233 for addr: 80002000 ---- +READING - Addr: 80002000 = 112233 ****** MEM: data read from cache_driver: 00112233 ---- @@ -89734,11 +89926,15 @@ STORING 112233 in 80002000 ---- ****** RF: Writing 00112233 to 1 +PC: 800003e8 ----> Received: babebabe for addr: 80002000 ---- +READING - Addr: 80002000 = 112233 ****** MEM: data read from cache_driver: 00112233 +PC: 800003e8 ----> Received: 00112233 for addr: 80002000 ---- +READING - Addr: 80002000 = 112233 ****** MEM: data read from cache_driver: 00112233 ---- @@ -89856,11 +90052,15 @@ STORING 30011223 in 80002004 STORING 30011223 in 80002004 ---- ****** +PC: 80000424 ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = 30011223 ****** MEM: data read from cache_driver: 30011223 +PC: 80000424 ----> Received: 30011223 for addr: 80002004 ---- +READING - Addr: 80002004 = 30011223 ****** MEM: data read from cache_driver: 30011223 ---- @@ -89969,11 +90169,15 @@ STORING 30011223 in 80002004 STORING 30011223 in 80002004 ---- ****** +PC: 80000424 ----> Received: babebabe for addr: 80002004 ---- +READING - Addr: 80002004 = 30011223 ****** MEM: data read from cache_driver: 30011223 +PC: 80000424 ----> Received: 30011223 for addr: 80002004 ---- +READING - Addr: 80002004 = 30011223 ****** MEM: data read from cache_driver: 30011223 ---- @@ -90102,11 +90306,15 @@ STORING 33001122 in 80002008 STORING 33001122 in 80002008 ---- ****** +PC: 80000464 ----> Received: babebabe for addr: 80002008 ---- +READING - Addr: 80002008 = 33001122 ****** MEM: data read from cache_driver: 33001122 +PC: 80000464 ----> Received: 33001122 for addr: 80002008 ---- +READING - Addr: 80002008 = 33001122 ****** MEM: data read from cache_driver: 33001122 ---- @@ -90216,11 +90424,15 @@ STORING 33001122 in 80002008 STORING 33001122 in 80002008 ---- ****** +PC: 80000464 ----> Received: babebabe for addr: 80002008 ---- +READING - Addr: 80002008 = 33001122 ****** MEM: data read from cache_driver: 33001122 +PC: 80000464 ----> Received: 33001122 for addr: 80002008 ---- +READING - Addr: 80002008 = 33001122 ****** MEM: data read from cache_driver: 33001122 ---- @@ -90338,11 +90550,15 @@ STORING 23300112 in 8000200c ---- ****** RF: Writing 23300112 to 1 +PC: 800004a0 ----> Received: babebabe for addr: 8000200c ---- +READING - Addr: 8000200c = 23300112 ****** MEM: data read from cache_driver: 23300112 +PC: 800004a0 ----> Received: 23300112 for addr: 8000200c ---- +READING - Addr: 8000200c = 23300112 ****** MEM: data read from cache_driver: 23300112 ---- @@ -90446,11 +90662,15 @@ STORING 23300112 in 8000200c ---- ****** RF: Writing 23300112 to 1 +PC: 800004a0 ----> Received: babebabe for addr: 8000200c ---- +READING - Addr: 8000200c = 23300112 ****** MEM: data read from cache_driver: 23300112 +PC: 800004a0 ----> Received: 23300112 for addr: 8000200c ---- +READING - Addr: 8000200c = 23300112 ****** MEM: data read from cache_driver: 23300112 ---- @@ -90574,11 +90794,15 @@ STORING 22330011 in 80002010 STORING 22330011 in 80002010 ---- ****** +PC: 800004e0 ----> Received: babebabe for addr: 80002010 ---- +READING - Addr: 80002010 = 22330011 ****** MEM: data read from cache_driver: 22330011 +PC: 800004e0 ----> Received: 22330011 for addr: 80002010 ---- +READING - Addr: 80002010 = 22330011 ****** MEM: data read from cache_driver: 22330011 ---- @@ -90698,11 +90922,15 @@ STORING 22330011 in 80002010 STORING 22330011 in 80002010 ---- ****** +PC: 800004e0 ----> Received: babebabe for addr: 80002010 ---- +READING - Addr: 80002010 = 22330011 ****** MEM: data read from cache_driver: 22330011 +PC: 800004e0 ----> Received: 22330011 for addr: 80002010 ---- +READING - Addr: 80002010 = 22330011 ****** MEM: data read from cache_driver: 22330011 ---- @@ -90836,11 +91064,15 @@ STORING 12233001 in 80002014 ---- ****** RF: Writing 12233001 to 1 +PC: 80000520 ----> Received: babebabe for addr: 80002014 ---- +READING - Addr: 80002014 = 12233001 ****** MEM: data read from cache_driver: 12233001 +PC: 80000520 ----> Received: 12233001 for addr: 80002014 ---- +READING - Addr: 80002014 = 12233001 ****** MEM: data read from cache_driver: 12233001 ---- @@ -90950,11 +91182,15 @@ STORING 12233001 in 80002014 ---- ****** RF: Writing 12233001 to 1 +PC: 80000520 ----> Received: babebabe for addr: 80002014 ---- +READING - Addr: 80002014 = 12233001 ****** MEM: data read from cache_driver: 12233001 +PC: 80000520 ----> Received: 12233001 for addr: 80002014 ---- +READING - Addr: 80002014 = 12233001 ****** MEM: data read from cache_driver: 12233001 ---- @@ -100088,7 +100324,7 @@ RF: Writing 0000000f to 1 ****** RF: Writing 0000000b to 2 (80000378) 0000000f * 0000000b = 000000a5 -(80000378) 0000000f * 0000000b = 000000a5 +(80000378) 00000000 * 0000000b = 00000000 ---- ****** [80000370] WB Data: 00000000 {babebabe}, to register: 0 [1 0] @@ -100152,7 +100388,7 @@ RF: Writing 0000000f to 1 ****** RF: Writing 0000000b to 2 (80000378) 0000000f * 0000000b = 000000a5 -(80000378) 0000000f * 0000000b = 000000a5 +(80000378) 00000000 * 0000000b = 00000000 ---- ****** [80000370] WB Data: 00000000 {babebabe}, to register: 0 [1 0] @@ -100403,7 +100639,7 @@ RF: Writing 0000000e to 1 ---- ****** (800003d4) 0000000e * 0000000b = 0000009a -(800003d4) 0000000e * 0000000b = 0000009a +(800003d4) 00000000 * 0000000b = 00000000 ---- ****** [800003cc] WB Data: 0000000b {babebabe}, to register: 2 [1 0] @@ -100467,7 +100703,7 @@ RF: Writing 0000000e to 1 ---- ****** (800003d4) 0000000e * 0000000b = 0000009a -(800003d4) 0000000e * 0000000b = 0000009a +(800003d4) 00000000 * 0000000b = 00000000 ---- ****** [800003cc] WB Data: 0000000b {babebabe}, to register: 2 [1 0] @@ -100567,7 +100803,7 @@ RF: Writing 0000000f to 1 ---- ****** (80000404) 0000000f * 0000000b = 000000a5 -(80000404) 0000000f * 0000000b = 000000a5 +(80000404) 00000000 * 0000000b = 00000000 ---- ****** [800003fc] WB Data: 00000000 {babebabe}, to register: 0 [1 0] @@ -100631,7 +100867,7 @@ RF: Writing 0000000f to 1 ---- ****** (80000404) 0000000f * 0000000b = 000000a5 -(80000404) 0000000f * 0000000b = 000000a5 +(80000404) 00000000 * 0000000b = 00000000 ---- ****** [800003fc] WB Data: 00000000 {babebabe}, to register: 0 [1 0] @@ -101024,7 +101260,7 @@ RF: Writing 0000000b to 2 ****** RF: Writing 0000000f to 1 (80000488) 0000000f * 0000000b = 000000a5 -(80000488) 0000000f * 0000000b = 000000a5 +(80000488) 0000000f * 00000000 = 00000000 ---- ****** [80000480] WB Data: 00000000 {babebabe}, to register: 0 [1 0] @@ -101088,7 +101324,7 @@ RF: Writing 0000000b to 2 ****** RF: Writing 0000000f to 1 (80000488) 0000000f * 0000000b = 000000a5 -(80000488) 0000000f * 0000000b = 000000a5 +(80000488) 0000000f * 00000000 = 00000000 ---- ****** [80000480] WB Data: 00000000 {babebabe}, to register: 0 [1 0] @@ -101339,7 +101575,7 @@ RF: Writing 0000000b to 2 ---- ****** (800004e4) 0000000e * 0000000b = 0000009a -(800004e4) 0000000e * 0000000b = 0000009a +(800004e4) 0000000e * 00000000 = 00000000 ---- ****** [800004dc] WB Data: 0000000e {babebabe}, to register: 1 [1 0] @@ -101403,7 +101639,7 @@ RF: Writing 0000000b to 2 ---- ****** (800004e4) 0000000e * 0000000b = 0000009a -(800004e4) 0000000e * 0000000b = 0000009a +(800004e4) 0000000e * 00000000 = 00000000 ---- ****** [800004dc] WB Data: 0000000e {babebabe}, to register: 1 [1 0] @@ -101503,7 +101739,7 @@ RF: Writing 0000000b to 2 ---- ****** (80000514) 0000000f * 0000000b = 000000a5 -(80000514) 0000000f * 0000000b = 000000a5 +(80000514) 0000000f * 00000000 = 00000000 ---- ****** [8000050c] WB Data: 00000000 {babebabe}, to register: 0 [1 0] @@ -101567,7 +101803,7 @@ RF: Writing 0000000b to 2 ---- ****** (80000514) 0000000f * 0000000b = 000000a5 -(80000514) 0000000f * 0000000b = 000000a5 +(80000514) 0000000f * 00000000 = 00000000 ---- ****** [8000050c] WB Data: 00000000 {babebabe}, to register: 0 [1 0] diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o index 75b01f5b..7d6d8cf9 100644 Binary files a/rtl/obj_dir/test_bench.o and b/rtl/obj_dir/test_bench.o differ diff --git a/rtl/test_bench.cpp b/rtl/test_bench.cpp index 49acb289..09709d6e 100644 --- a/rtl/test_bench.cpp +++ b/rtl/test_bench.cpp @@ -78,7 +78,7 @@ int main(int argc, char **argv) if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n"; - // char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex"; + // char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; // bool curr = v.simulate(testing); // if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl; diff --git a/rtl/test_bench.h b/rtl/test_bench.h index 1fcaa751..5f559903 100644 --- a/rtl/test_bench.h +++ b/rtl/test_bench.h @@ -206,52 +206,50 @@ bool Vortex::dbus_driver() printf("----\n"); for (unsigned curr_th = 0; curr_th < NT; curr_th++) { - - unsigned & in_data_use = (curr_th == 0) ? vortex->in_cache_driver_out_data_0 : vortex->in_cache_driver_out_data_1; - - if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[0]) + + if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th]) { - addr = (uint32_t) vortex->out_cache_driver_in_address[1]; + addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th]; ram.getWord(addr, &data_read); if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ) { - in_data_use = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF); + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF); } else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ) { - in_data_use = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF); + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF); } else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ) { // printf("Reading mem - Addr: %x = %x\n", addr, data_read); - // std::cout << "Reading mem - Addr: " << std::hex << addr << " = " << data_read << "\n"; + std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n"; std::cout << std::dec; - in_data_use = data_read; + vortex->in_cache_driver_out_data[curr_th] = data_read; } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ) { - in_data_use = (data_read & 0xFF); + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF); } else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ) { - in_data_use = (data_read & 0xFFFF); + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF); } else { - in_data_use = 0xbabebabe; + vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe; } } else { - in_data_use = 0xbabebabe; + vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe; } } @@ -321,13 +319,16 @@ bool Vortex::simulate(std::string file_to_simulate) // cycle++; // } + bool istop; + bool dstop; + // for (int i = 0; i < 500; i++) while (this->stop && (!(stop && (counter > 5)))) { // std::cout << "************* Cycle: " << cycle << "\n"; - bool istop = ibus_driver(); - bool dstop = !dbus_driver(); + istop = ibus_driver(); + dstop = !dbus_driver(); vortex->clk = 1; vortex->eval();