diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v
index be6cbcbd..6b65c227 100644
--- a/hw/rtl/VX_execute.v
+++ b/hw/rtl/VX_execute.v
@@ -131,4 +131,11 @@ module VX_execute #(
         .gpu_commit_if  (gpu_commit_if)
     );
 
+    // special workaround to get RISC-V tests Pass/Fail status
+    wire ebreak /* verilator public */;
+    assign ebreak = alu_req_if.valid && alu_req_if.ready
+                 && `IS_BR_MOD(alu_req_if.op_mod)
+                 && (`BR_OP(alu_req_if.op_type) == `BR_EBREAK 
+                  || `BR_OP(alu_req_if.op_type) == `BR_ECALL);
+
 endmodule
diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp
index e3964cb8..7dc57c43 100644
--- a/hw/simulate/simulator.cpp
+++ b/hw/simulate/simulator.cpp
@@ -300,7 +300,7 @@ void Simulator::run() {
 
   // execute program
   while (vortex_->busy 
-      && !vortex_->ebreak) {
+      && !get_ebreak()) {
     this->step();
   }
 
@@ -308,6 +308,10 @@ void Simulator::run() {
   this->wait(5);  
 }
 
+bool Simulator::get_ebreak() const {
+  return (int)vortex_->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak;
+}
+
 int Simulator::get_last_wb_value(int reg) const {
   return (int)vortex_->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
 }
diff --git a/hw/simulate/simulator.h b/hw/simulate/simulator.h
index 261870d5..cc131a4b 100644
--- a/hw/simulate/simulator.h
+++ b/hw/simulate/simulator.h
@@ -40,7 +40,10 @@ public:
   void get_csr(int core_id, int addr, unsigned *value);
 
   void run();  
+
   int get_last_wb_value(int reg) const;  
+  
+  bool get_ebreak() const;
 
   void print_stats(std::ostream& out);
 
@@ -60,7 +63,7 @@ private:
   void eval_mem_bus();
   void eval_io_bus();
   void eval_csr_bus();
-  
+
   std::list<mem_req_t> mem_rsp_vec_;
   bool mem_rsp_active_;