From a4d6ada16df9b49645f0d75da749f908788b18e9 Mon Sep 17 00:00:00 2001 From: Lingjun Zhu Date: Thu, 17 Oct 2019 14:18:52 -0400 Subject: [PATCH] Fixed the issues of memory during synthesis --- rtl/VX_gpr.v | 2 +- syn/syn.tcl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/VX_gpr.v b/rtl/VX_gpr.v index b096a953..694126f9 100644 --- a/rtl/VX_gpr.v +++ b/rtl/VX_gpr.v @@ -48,7 +48,7 @@ module VX_gpr ( // .q1 (out_b_reg_data) // ); - // wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}}; + wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}}; /* verilator lint_off PINCONNECTEMPTY */ rf2_32x128_wm1 first_ram ( .CENYA(), diff --git a/syn/syn.tcl b/syn/syn.tcl index b4cb37c4..0ce1b74c 100755 --- a/syn/syn.tcl +++ b/syn/syn.tcl @@ -1,5 +1,5 @@ set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs] -set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32_128_wm1_ss_0p81v_0p81v_125c.db dw_foundation.sldb] +set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_125c.db dw_foundation.sldb] set symbol_library {} set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db]