diff --git a/rtl/VX_define.v b/rtl/VX_define.v
index bcd3b87d..4f3eb68b 100644
--- a/rtl/VX_define.v
+++ b/rtl/VX_define.v
@@ -127,7 +127,7 @@
 
 `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
 
-//`define SINGLE_CORE_BENCH
+`define SINGLE_CORE_BENCH
 
 `define GLOBAL_BLOCK_SIZE_BYTES 16
 
diff --git a/rtl/VX_define_synth.v b/rtl/VX_define_synth.v
index a55023d9..79d1a158 100644
--- a/rtl/VX_define_synth.v
+++ b/rtl/VX_define_synth.v
@@ -12,7 +12,6 @@
 // L2 Cache size
 `define LLCACHE_SIZE_BYTES 8192
 
-
 // `define QUEUE_FORCE_MLAB 1
 
 // Use l3 cache (required for cluster behavior)
diff --git a/rtl/Vortex.v b/rtl/Vortex.v
index 9759216e..8660861f 100644
--- a/rtl/Vortex.v
+++ b/rtl/Vortex.v
@@ -2,110 +2,92 @@
 `include "VX_cache_config.v"
 
 module Vortex
-	#(
+	#( 
 		parameter CORE_ID = 0
-	)
-	(
-		`ifdef SINGLE_CORE_BENCH
-			input  wire           clk,
-			input  wire           reset,
-			// IO
-			output wire        io_valid,
-			output wire[31:0]  io_data,
+	) (		
+`ifdef SINGLE_CORE_BENCH
 
-			// DRAM Dcache Req
-		    output wire                              dram_req,
-		    output wire                              dram_req_write,
-		    output wire                              dram_req_read,
-		    output wire [31:0]                       dram_req_addr,
-		    output wire [31:0]                       dram_req_size,
-		    output wire [31:0]                       dram_req_data[`DBANK_LINE_SIZE_RNG],
-		    output wire [31:0]                       dram_expected_lat,
+	// Clock
+	input  wire           	clk,
+	input  wire           	reset,
 
-			// DRAM Dcache Res
-			output wire                              dram_fill_accept,
-		    input  wire                              dram_fill_rsp,
-		    input  wire [31:0]                       dram_fill_rsp_addr,
-		    input  wire [31:0]                       dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
+	// IO
+	output wire        		io_valid,
+	output wire[31:0]  		io_data,
+
+	// DRAM Dcache Req
+	output wire             dram_req,
+	output wire             dram_req_write,
+	output wire             dram_req_read,
+	output wire [31:0]      dram_req_addr,
+	output wire [31:0]      dram_req_size,
+	output wire [31:0]      dram_req_data[`DBANK_LINE_SIZE_RNG],
+	output wire [31:0]      dram_expected_lat,
+
+	// DRAM Dcache Res
+	output wire             dram_fill_accept,
+	input  wire             dram_fill_rsp,
+	input  wire [31:0]      dram_fill_rsp_addr,
+	input  wire [31:0]      dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
+
+	// LLC Snooping
+	input  wire             snp_req,
+	input  wire [31:0]      snp_req_addr,
+	output wire             snp_req_delay,
+
+	output wire             out_ebreak
+
+`else 
+
+	input  wire           					 clk,
+	input  wire           					 reset,
+	// IO
+	output wire        						 io_valid,
+	output wire[31:0]  						 io_data,
+
+	// DRAM Dcache Req
+	output wire                              dram_req,
+	output wire                              dram_req_write,
+	output wire                              dram_req_read,
+	output wire [31:0]                       dram_req_addr,
+	output wire [31:0]                       dram_req_size,
+	output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data,
+	output wire [31:0]                       dram_expected_lat,
+
+	// DRAM Dcache Res
+	output wire                              dram_fill_accept,
+	input  wire                              dram_fill_rsp,
+	input  wire [31:0]                       dram_fill_rsp_addr,
+	input  wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
 
 
-			// DRAM Icache Req
-		    output wire                              I_dram_req,
-		    output wire                              I_dram_req_write,
-		    output wire                              I_dram_req_read,
-		    output wire [31:0]                       I_dram_req_addr,
-		    output wire [31:0]                       I_dram_req_size,
-		    output wire [31:0]                       I_dram_req_data[`IBANK_LINE_SIZE_RNG],
-		    output wire [31:0]                       I_dram_expected_lat,
+	// DRAM Icache Req
+	output wire                              I_dram_req,
+	output wire                              I_dram_req_write,
+	output wire                              I_dram_req_read,
+	output wire [31:0]                       I_dram_req_addr,
+	output wire [31:0]                       I_dram_req_size,
+	output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
+	output wire [31:0]                       I_dram_expected_lat,
 
-			// DRAM Icache Res
-			output wire                              I_dram_fill_accept,
-		    input  wire                              I_dram_fill_rsp,
-		    input  wire [31:0]                       I_dram_fill_rsp_addr,
-		    input  wire [31:0]                       I_dram_fill_rsp_data[`IBANK_LINE_SIZE_RNG],
-
-		    input  wire                              snp_req,
-		    input  wire [31:0]                       snp_req_addr,
-		    output wire                              snp_req_delay,
-
-		    input  wire                              I_snp_req,
-		    input  wire [31:0]                       I_snp_req_addr,
-		    output wire                              I_snp_req_delay,
-
-		    output wire        out_ebreak
-
-		 `else 
-
-			input  wire           clk,
-			input  wire           reset,
-			// IO
-			output wire        io_valid,
-			output wire[31:0]  io_data,
-
-			// DRAM Dcache Req
-		    output wire                              dram_req,
-		    output wire                              dram_req_write,
-		    output wire                              dram_req_read,
-		    output wire [31:0]                       dram_req_addr,
-		    output wire [31:0]                       dram_req_size,
-		    output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data,
-		    output wire [31:0]                       dram_expected_lat,
-
-			// DRAM Dcache Res
-			output wire                              dram_fill_accept,
-		    input  wire                              dram_fill_rsp,
-		    input  wire [31:0]                       dram_fill_rsp_addr,
-		    input  wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
+	// DRAM Icache Res
+	output wire                              I_dram_fill_accept,
+	input  wire                              I_dram_fill_rsp,
+	input  wire [31:0]                       I_dram_fill_rsp_addr,
+	input  wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
 
 
-			// DRAM Icache Req
-		    output wire                              I_dram_req,
-		    output wire                              I_dram_req_write,
-		    output wire                              I_dram_req_read,
-		    output wire [31:0]                       I_dram_req_addr,
-		    output wire [31:0]                       I_dram_req_size,
-		    output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
-		    output wire [31:0]                       I_dram_expected_lat,
+	input  wire                              snp_req,
+	input  wire [31:0]                       snp_req_addr,
+	output wire                              snp_req_delay,
 
-			// DRAM Icache Res
-			output wire                              I_dram_fill_accept,
-		    input  wire                              I_dram_fill_rsp,
-		    input  wire [31:0]                       I_dram_fill_rsp_addr,
-		    input  wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
+	input  wire                              I_snp_req,
+	input  wire [31:0]                       I_snp_req_addr,
+	output wire                              I_snp_req_delay,
 
-
-		    input  wire                              snp_req,
-		    input  wire [31:0]                       snp_req_addr,
-		    output wire                              snp_req_delay,
-
-		    input  wire                              I_snp_req,
-		    input  wire [31:0]                       I_snp_req_addr,
-		    output wire                              I_snp_req_delay,
-
-
-		    output wire        out_ebreak
-		`endif
-	);
+	output wire        						 out_ebreak
+`endif
+);
 
 	wire scheduler_empty;
 	wire out_ebreak_unqual;
diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v
index 1d926c53..f2630c90 100644
--- a/rtl/Vortex_SOC.v
+++ b/rtl/Vortex_SOC.v
@@ -3,9 +3,9 @@
 
 module Vortex_SOC (
 
-    // System Clock
-    input  wire            clk,
-    input  wire            reset,
+    // Clock
+    input  wire             clk,
+    input  wire             reset,
 
     // IO
     output wire             io_valid[`NUMBER_CORES-1:0],
@@ -13,7 +13,7 @@ module Vortex_SOC (
 
     output wire[31:0]       number_cores,
 
-    // DRAM Dcache Req
+    // DRAM Req
     output wire             out_dram_req,
     output wire             out_dram_req_write,
     output wire             out_dram_req_read,
@@ -22,12 +22,13 @@ module Vortex_SOC (
     output wire [31:0]      out_dram_req_data[`DBANK_LINE_SIZE_RNG],
     output wire [31:0]      out_dram_expected_lat,
 
-    // DRAM Dcache Res
+    // DRAM Res
     output wire             out_dram_fill_accept,
     input  wire             out_dram_fill_rsp,
     input  wire [31:0]      out_dram_fill_rsp_addr,
     input  wire [31:0]      out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
 
+    // LLC Snooping
     input  wire             llc_snp_req,
     input  wire             llc_snp_req_addr,
     output wire             llc_snp_req_delay,
@@ -529,7 +530,7 @@ module Vortex_SOC (
 
             assign io_valid[curr_core]  = per_core_io_valid[curr_core];
             assign io_data [curr_core]  = per_core_io_data [curr_core];
-            
+
             Vortex #(.CORE_ID(curr_core)) vortex_core(
                     .clk                        (clk),
                     .reset                      (reset),
@@ -605,8 +606,6 @@ module Vortex_SOC (
     //     end
     // endgenerate
 
-
-
     // 
     genvar l2c_curr_core;
     generate