From a801a16062eb1fbc45896949e4fb1f0a0f63ccd6 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sun, 29 Aug 2021 20:07:34 -0700 Subject: [PATCH] instruction decode refactoring fixing naming collision --- hw/rtl/VX_alu_unit.v | 32 ++-- hw/rtl/VX_csr_data.v | 18 +- hw/rtl/VX_csr_unit.v | 6 +- hw/rtl/VX_decode.v | 124 +++++++------- hw/rtl/VX_define.vh | 245 +++++++++++++-------------- hw/rtl/VX_execute.v | 6 +- hw/rtl/VX_fpu_unit.v | 4 +- hw/rtl/VX_gpu_unit.v | 8 +- hw/rtl/VX_ibuffer.v | 2 +- hw/rtl/VX_instr_demux.v | 32 ++-- hw/rtl/VX_lsu_unit.v | 22 +-- hw/rtl/VX_muldiv.v | 14 +- hw/rtl/VX_print_instr.vh | 156 ++++++++--------- hw/rtl/VX_types.vh | 2 +- hw/rtl/fp_cores/VX_fp_cvt.v | 10 +- hw/rtl/fp_cores/VX_fp_div.v | 2 +- hw/rtl/fp_cores/VX_fp_fma.v | 2 +- hw/rtl/fp_cores/VX_fp_ncomp.v | 30 ++-- hw/rtl/fp_cores/VX_fp_rounding.v | 12 +- hw/rtl/fp_cores/VX_fp_sqrt.v | 2 +- hw/rtl/fp_cores/VX_fpu_dpi.v | 34 ++-- hw/rtl/fp_cores/VX_fpu_fpga.v | 30 ++-- hw/rtl/fp_cores/VX_fpu_fpnew.v | 50 +++--- hw/rtl/interfaces/VX_alu_req_if.v | 4 +- hw/rtl/interfaces/VX_csr_req_if.v | 2 +- hw/rtl/interfaces/VX_decode_if.v | 4 +- hw/rtl/interfaces/VX_fpu_req_if.v | 4 +- hw/rtl/interfaces/VX_fpu_to_csr_if.v | 2 +- hw/rtl/interfaces/VX_gpu_req_if.v | 2 +- hw/rtl/interfaces/VX_ibuffer_if.v | 4 +- hw/rtl/interfaces/VX_lsu_req_if.v | 2 +- hw/scripts/scope.json | 4 +- 32 files changed, 434 insertions(+), 437 deletions(-) diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index 8f7f5e90..7934a4b3 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -25,12 +25,12 @@ module VX_alu_unit #( wire stall_in, stall_out; `UNUSED_VAR (alu_req_if.op_mod) - wire is_br_op = `ALU_IS_BR(alu_req_if.op_mod); - wire [`ALU_BITS-1:0] alu_op = `ALU_OP(alu_req_if.op_type); - wire [`BR_BITS-1:0] br_op = `BR_OP(alu_req_if.op_type); - wire alu_signed = `ALU_SIGNED(alu_op); - wire [1:0] alu_op_class = `ALU_OP_CLASS(alu_op); - wire is_sub = (alu_op == `ALU_SUB); + wire is_br_op = `INST_ALU_IS_BR(alu_req_if.op_mod); + wire [`INST_ALU_BITS-1:0] alu_op = `INST_ALU_OP(alu_req_if.op_type); + wire [`INST_BR_BITS-1:0] br_op = `INST_BR_OP(alu_req_if.op_type); + wire alu_signed = `INST_ALU_SIGNED(alu_op); + wire [1:0] alu_op_class = `INST_ALU_OP_CLASS(alu_op); + wire is_sub = (alu_op == `INST_ALU_SUB); wire [`NUM_THREADS-1:0][31:0] alu_in1 = alu_req_if.rs1_data; wire [`NUM_THREADS-1:0][31:0] alu_in2 = alu_req_if.rs2_data; @@ -57,10 +57,10 @@ module VX_alu_unit #( for (genvar i = 0; i < `NUM_THREADS; i++) begin always @(*) begin case (alu_op) - `ALU_AND: msc_result[i] = alu_in1[i] & alu_in2_imm[i]; - `ALU_OR: msc_result[i] = alu_in1[i] | alu_in2_imm[i]; - `ALU_XOR: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i]; - //`ALU_SLL, + `INST_ALU_AND: msc_result[i] = alu_in1[i] & alu_in2_imm[i]; + `INST_ALU_OR: msc_result[i] = alu_in1[i] | alu_in2_imm[i]; + `INST_ALU_XOR: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i]; + //`INST_ALU_SLL, default: msc_result[i] = alu_in1[i] << alu_in2_imm[i][4:0]; endcase end @@ -81,7 +81,7 @@ module VX_alu_unit #( // branch - wire is_jal = is_br_op && (br_op == `BR_JAL || br_op == `BR_JALR); + wire is_jal = is_br_op && (br_op == `INST_BR_JAL || br_op == `INST_BR_JALR); wire [`NUM_THREADS-1:0][31:0] alu_jal_result = is_jal ? {`NUM_THREADS{alu_req_if.next_PC}} : alu_result; wire [31:0] br_dest = add_result[alu_req_if.tid]; @@ -90,9 +90,9 @@ module VX_alu_unit #( wire is_less = cmp_result[32]; wire is_equal = ~(| cmp_result[31:0]); - wire br_neg = `BR_NEG(br_op); - wire br_less = `BR_LESS(br_op); - wire br_static = `BR_STATIC(br_op); + wire br_neg = `INST_BR_NEG(br_op); + wire br_less = `INST_BR_LESS(br_op); + wire br_static = `INST_BR_STATIC(br_op); wire br_taken = ((br_less ? is_less : is_equal) ^ br_neg) | br_static; // output @@ -118,14 +118,14 @@ module VX_alu_unit #( wire mul_wb; wire [`NUM_THREADS-1:0][31:0] mul_data; - wire is_mul_op = `ALU_IS_MUL(alu_req_if.op_mod); + wire is_mul_op = `INST_ALU_IS_MUL(alu_req_if.op_mod); VX_muldiv muldiv ( .clk (clk), .reset (reset), // Inputs - .alu_op (`MUL_OP(alu_req_if.op_type)), + .alu_op (`INST_MUL_OP(alu_req_if.op_type)), .wid_in (alu_req_if.wid), .tmask_in (alu_req_if.tmask), .PC_in (alu_req_if.PC), diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v index 3aa3a17e..e77f28b0 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.v @@ -42,7 +42,7 @@ module VX_csr_data #( reg [63:0] csr_cycle; reg [63:0] csr_instret; - reg [`NUM_WARPS-1:0][`FRM_BITS+`FFG_BITS-1:0] fcsr; + reg [`NUM_WARPS-1:0][`INST_FRM_BITS+`FFLAGS_BITS-1:0] fcsr; always @(posedge clk) begin @@ -52,16 +52,16 @@ module VX_csr_data #( end if (fpu_to_csr_if.write_enable) begin - fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0] <= fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0] - | fpu_to_csr_if.write_fflags; + fcsr[fpu_to_csr_if.write_wid][`FFLAGS_BITS-1:0] <= fcsr[fpu_to_csr_if.write_wid][`FFLAGS_BITS-1:0] + | fpu_to_csr_if.write_fflags; end `endif if (write_enable) begin case (write_addr) - `CSR_FFLAGS: fcsr[write_wid][`FFG_BITS-1:0] <= write_data[`FFG_BITS-1:0]; - `CSR_FRM: fcsr[write_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS] <= write_data[`FRM_BITS-1:0]; - `CSR_FCSR: fcsr[write_wid] <= write_data[`FFG_BITS+`FRM_BITS-1:0]; + `CSR_FFLAGS: fcsr[write_wid][`FFLAGS_BITS-1:0] <= write_data[`FFLAGS_BITS-1:0]; + `CSR_FRM: fcsr[write_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS] <= write_data[`INST_FRM_BITS-1:0]; + `CSR_FCSR: fcsr[write_wid] <= write_data[`FFLAGS_BITS+`INST_FRM_BITS-1:0]; `CSR_SATP: csr_satp <= write_data; @@ -104,8 +104,8 @@ module VX_csr_data #( read_data_r = 'x; read_addr_valid_r = 1; case (read_addr) - `CSR_FFLAGS : read_data_r = 32'(fcsr[read_wid][`FFG_BITS-1:0]); - `CSR_FRM : read_data_r = 32'(fcsr[read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS]); + `CSR_FFLAGS : read_data_r = 32'(fcsr[read_wid][`FFLAGS_BITS-1:0]); + `CSR_FRM : read_data_r = 32'(fcsr[read_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS]); `CSR_FCSR : read_data_r = 32'(fcsr[read_wid]); `CSR_WTID , @@ -222,7 +222,7 @@ module VX_csr_data #( assign read_data = read_data_r; `ifdef EXT_F_ENABLE - assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS]; + assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS]; `endif endmodule \ No newline at end of file diff --git a/hw/rtl/VX_csr_unit.v b/hw/rtl/VX_csr_unit.v index 54cad7e7..a41c1875 100644 --- a/hw/rtl/VX_csr_unit.v +++ b/hw/rtl/VX_csr_unit.v @@ -70,14 +70,14 @@ module VX_csr_unit #( always @(*) begin csr_we_s0_unqual = (csr_req_data != 0); case (csr_req_if.op_type) - `CSR_RW: begin + `INST_CSR_RW: begin csr_updated_data = csr_req_data; csr_we_s0_unqual = 1; end - `CSR_RS: begin + `INST_CSR_RS: begin csr_updated_data = csr_read_data_qual | csr_req_data; end - //`CSR_RC + //`INST_CSR_RC default: begin csr_updated_data = csr_read_data_qual & ~csr_req_data; end diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index eac4e60e..832a1537 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -32,8 +32,8 @@ module VX_decode #( `UNUSED_VAR (reset) reg [`EX_BITS-1:0] ex_type; - reg [`OP_BITS-1:0] op_type; - reg [`MOD_BITS-1:0] op_mod; + reg [`INST_OP_BITS-1:0] op_type; + reg [`INST_MOD_BITS-1:0] op_mod; reg [`NR_BITS-1:0] rd_r, rs1_r, rs2_r, rs3_r; reg [31:0] imm; reg use_rd, use_PC, use_imm; @@ -79,14 +79,14 @@ module VX_decode #( `INST_I: begin ex_type = `EX_ALU; case (func3) - 3'h0: op_type = `OP_BITS'(`ALU_ADD); - 3'h1: op_type = `OP_BITS'(`ALU_SLL); - 3'h2: op_type = `OP_BITS'(`ALU_SLT); - 3'h3: op_type = `OP_BITS'(`ALU_SLTU); - 3'h4: op_type = `OP_BITS'(`ALU_XOR); - 3'h5: op_type = (func7[5]) ? `OP_BITS'(`ALU_SRA) : `OP_BITS'(`ALU_SRL); - 3'h6: op_type = `OP_BITS'(`ALU_OR); - 3'h7: op_type = `OP_BITS'(`ALU_AND); + 3'h0: op_type = `INST_OP_BITS'(`INST_ALU_ADD); + 3'h1: op_type = `INST_OP_BITS'(`INST_ALU_SLL); + 3'h2: op_type = `INST_OP_BITS'(`INST_ALU_SLT); + 3'h3: op_type = `INST_OP_BITS'(`INST_ALU_SLTU); + 3'h4: op_type = `INST_OP_BITS'(`INST_ALU_XOR); + 3'h5: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SRA) : `INST_OP_BITS'(`INST_ALU_SRL); + 3'h6: op_type = `INST_OP_BITS'(`INST_ALU_OR); + 3'h7: op_type = `INST_OP_BITS'(`INST_ALU_AND); default:; endcase use_rd = 1; @@ -100,14 +100,14 @@ module VX_decode #( `ifdef EXT_F_ENABLE if (func7[0]) begin case (func3) - 3'h0: op_type = `OP_BITS'(`MUL_MUL); - 3'h1: op_type = `OP_BITS'(`MUL_MULH); - 3'h2: op_type = `OP_BITS'(`MUL_MULHSU); - 3'h3: op_type = `OP_BITS'(`MUL_MULHU); - 3'h4: op_type = `OP_BITS'(`MUL_DIV); - 3'h5: op_type = `OP_BITS'(`MUL_DIVU); - 3'h6: op_type = `OP_BITS'(`MUL_REM); - 3'h7: op_type = `OP_BITS'(`MUL_REMU); + 3'h0: op_type = `INST_OP_BITS'(`INST_MUL_MUL); + 3'h1: op_type = `INST_OP_BITS'(`INST_MUL_MULH); + 3'h2: op_type = `INST_OP_BITS'(`INST_MUL_MULHSU); + 3'h3: op_type = `INST_OP_BITS'(`INST_MUL_MULHU); + 3'h4: op_type = `INST_OP_BITS'(`INST_MUL_DIV); + 3'h5: op_type = `INST_OP_BITS'(`INST_MUL_DIVU); + 3'h6: op_type = `INST_OP_BITS'(`INST_MUL_REM); + 3'h7: op_type = `INST_OP_BITS'(`INST_MUL_REMU); default:; endcase op_mod = 2; @@ -115,14 +115,14 @@ module VX_decode #( `endif begin case (func3) - 3'h0: op_type = (func7[5]) ? `OP_BITS'(`ALU_SUB) : `OP_BITS'(`ALU_ADD); - 3'h1: op_type = `OP_BITS'(`ALU_SLL); - 3'h2: op_type = `OP_BITS'(`ALU_SLT); - 3'h3: op_type = `OP_BITS'(`ALU_SLTU); - 3'h4: op_type = `OP_BITS'(`ALU_XOR); - 3'h5: op_type = (func7[5]) ? `OP_BITS'(`ALU_SRA) : `OP_BITS'(`ALU_SRL); - 3'h6: op_type = `OP_BITS'(`ALU_OR); - 3'h7: op_type = `OP_BITS'(`ALU_AND); + 3'h0: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SUB) : `INST_OP_BITS'(`INST_ALU_ADD); + 3'h1: op_type = `INST_OP_BITS'(`INST_ALU_SLL); + 3'h2: op_type = `INST_OP_BITS'(`INST_ALU_SLT); + 3'h3: op_type = `INST_OP_BITS'(`INST_ALU_SLTU); + 3'h4: op_type = `INST_OP_BITS'(`INST_ALU_XOR); + 3'h5: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SRA) : `INST_OP_BITS'(`INST_ALU_SRL); + 3'h6: op_type = `INST_OP_BITS'(`INST_ALU_OR); + 3'h7: op_type = `INST_OP_BITS'(`INST_ALU_AND); default:; endcase end @@ -133,7 +133,7 @@ module VX_decode #( end `INST_LUI: begin ex_type = `EX_ALU; - op_type = `OP_BITS'(`ALU_LUI); + op_type = `INST_OP_BITS'(`INST_ALU_LUI); use_rd = 1; use_imm = 1; imm = {upper_imm, 12'(0)}; @@ -142,7 +142,7 @@ module VX_decode #( end `INST_AUIPC: begin ex_type = `EX_ALU; - op_type = `OP_BITS'(`ALU_AUIPC); + op_type = `INST_OP_BITS'(`INST_ALU_AUIPC); use_rd = 1; use_imm = 1; use_PC = 1; @@ -151,7 +151,7 @@ module VX_decode #( end `INST_JAL: begin ex_type = `EX_ALU; - op_type = `OP_BITS'(`BR_JAL); + op_type = `INST_OP_BITS'(`INST_BR_JAL); op_mod = 1; use_rd = 1; use_imm = 1; @@ -162,7 +162,7 @@ module VX_decode #( end `INST_JALR: begin ex_type = `EX_ALU; - op_type = `OP_BITS'(`BR_JALR); + op_type = `INST_OP_BITS'(`INST_BR_JALR); op_mod = 1; use_rd = 1; use_imm = 1; @@ -174,12 +174,12 @@ module VX_decode #( `INST_B: begin ex_type = `EX_ALU; case (func3) - 3'h0: op_type = `OP_BITS'(`BR_EQ); - 3'h1: op_type = `OP_BITS'(`BR_NE); - 3'h4: op_type = `OP_BITS'(`BR_LT); - 3'h5: op_type = `OP_BITS'(`BR_GE); - 3'h6: op_type = `OP_BITS'(`BR_LTU); - 3'h7: op_type = `OP_BITS'(`BR_GEU); + 3'h0: op_type = `INST_OP_BITS'(`INST_BR_EQ); + 3'h1: op_type = `INST_OP_BITS'(`INST_BR_NE); + 3'h4: op_type = `INST_OP_BITS'(`INST_BR_LT); + 3'h5: op_type = `INST_OP_BITS'(`INST_BR_GE); + 3'h6: op_type = `INST_OP_BITS'(`INST_BR_LTU); + 3'h7: op_type = `INST_OP_BITS'(`INST_BR_GEU); default:; endcase op_mod = 1; @@ -192,13 +192,13 @@ module VX_decode #( end `INST_F: begin ex_type = `EX_LSU; - op_type = `OP_BITS'(func3[0]); - op_mod = `MOD_BITS'(1); + op_type = `INST_OP_BITS'(func3[0]); + op_mod = `INST_MOD_BITS'(1); end `INST_SYS : begin if (func3[1:0] != 0) begin ex_type = `EX_CSR; - op_type = `OP_BITS'(func3[1:0]); + op_type = `INST_OP_BITS'(func3[1:0]); use_rd = 1; use_imm = func3[2]; imm = 32'(u_12); // addr @@ -211,11 +211,11 @@ module VX_decode #( end else begin ex_type = `EX_ALU; case (u_12) - 12'h000: op_type = `OP_BITS'(`BR_ECALL); - 12'h001: op_type = `OP_BITS'(`BR_EBREAK); - 12'h302: op_type = `OP_BITS'(`BR_MRET); - 12'h102: op_type = `OP_BITS'(`BR_SRET); - 12'h7B2: op_type = `OP_BITS'(`BR_DRET); + 12'h000: op_type = `INST_OP_BITS'(`INST_BR_ECALL); + 12'h001: op_type = `INST_OP_BITS'(`INST_BR_EBREAK); + 12'h302: op_type = `INST_OP_BITS'(`INST_BR_MRET); + 12'h102: op_type = `INST_OP_BITS'(`INST_BR_SRET); + 12'h7B2: op_type = `INST_OP_BITS'(`INST_BR_DRET); default:; endcase op_mod = 1; @@ -232,7 +232,7 @@ module VX_decode #( `endif `INST_L: begin ex_type = `EX_LSU; - op_type = `OP_BITS'({1'b0, func3}); + op_type = `INST_OP_BITS'({1'b0, func3}); use_rd = 1; imm = {{20{u_12[11]}}, u_12}; `ifdef EXT_F_ENABLE @@ -248,7 +248,7 @@ module VX_decode #( `endif `INST_S: begin ex_type = `EX_LSU; - op_type = `OP_BITS'({1'b1, func3}); + op_type = `INST_OP_BITS'({1'b1, func3}); imm = {{20{s_imm[11]}}, s_imm}; `USED_IREG (rs1); `ifdef EXT_F_ENABLE @@ -264,7 +264,7 @@ module VX_decode #( `INST_FNMSUB, `INST_FNMADD: begin ex_type = `EX_FPU; - op_type = `OP_BITS'(opcode[3:0]); + op_type = `INST_OP_BITS'(opcode[3:0]); op_mod = func3; use_rd = 1; `USED_FREG (rd); @@ -281,35 +281,35 @@ module VX_decode #( 7'h04, // FSUB 7'h08, // FMUL 7'h0C: begin // FDIV - op_type = `OP_BITS'(func7[3:0]); + op_type = `INST_OP_BITS'(func7[3:0]); `USED_FREG (rd); `USED_FREG (rs1); `USED_FREG (rs2); end 7'h2C: begin - op_type = `OP_BITS'(`FPU_SQRT); + op_type = `INST_OP_BITS'(`INST_FPU_SQRT); `USED_FREG (rd); `USED_FREG (rs1); end 7'h50: begin - op_type = `OP_BITS'(`FPU_CMP); + op_type = `INST_OP_BITS'(`INST_FPU_CMP); `USED_IREG (rd); `USED_FREG (rs1); `USED_FREG (rs2); end 7'h60: begin - op_type = (instr[20]) ? `OP_BITS'(`FPU_CVTWUS) : `OP_BITS'(`FPU_CVTWS); + op_type = (instr[20]) ? `INST_OP_BITS'(`INST_FPU_CVTWUS) : `INST_OP_BITS'(`INST_FPU_CVTWS); `USED_IREG (rd); `USED_FREG (rs1); end 7'h68: begin - op_type = (instr[20]) ? `OP_BITS'(`FPU_CVTSWU) : `OP_BITS'(`FPU_CVTSW); + op_type = (instr[20]) ? `INST_OP_BITS'(`INST_FPU_CVTSWU) : `INST_OP_BITS'(`INST_FPU_CVTSW); `USED_FREG (rd); `USED_IREG (rs1); end 7'h10: begin // FSGNJ=0, FSGNJN=1, FSGNJX=2 - op_type = `OP_BITS'(`FPU_MISC); + op_type = `INST_OP_BITS'(`INST_FPU_MISC); op_mod = {1'b0, func3[1:0]}; `USED_FREG (rd); `USED_FREG (rs1); @@ -317,7 +317,7 @@ module VX_decode #( end 7'h14: begin // FMIN=3, FMAX=4 - op_type = `OP_BITS'(`FPU_MISC); + op_type = `INST_OP_BITS'(`INST_FPU_MISC); op_mod = func3[0] ? 4 : 3; `USED_FREG (rd); `USED_FREG (rs1); @@ -326,10 +326,10 @@ module VX_decode #( 7'h70: begin if (func3[0]) begin // FCLASS - op_type = `OP_BITS'(`FPU_CLASS); + op_type = `INST_OP_BITS'(`INST_FPU_CLASS); end else begin // FMV.X.W=5 - op_type = `OP_BITS'(`FPU_MISC); + op_type = `INST_OP_BITS'(`INST_FPU_MISC); op_mod = 5; end `USED_IREG (rd); @@ -337,7 +337,7 @@ module VX_decode #( end 7'h78: begin // FMV.W.X=6 - op_type = `OP_BITS'(`FPU_MISC); + op_type = `INST_OP_BITS'(`INST_FPU_MISC); op_mod = 6; `USED_FREG (rd); `USED_IREG (rs1); @@ -350,26 +350,26 @@ module VX_decode #( ex_type = `EX_GPU; case (func3) 3'h0: begin - op_type = `OP_BITS'(`GPU_TMC); + op_type = `INST_OP_BITS'(`INST_GPU_TMC); is_wstall = 1; `USED_IREG (rs1); end 3'h1: begin - op_type = `OP_BITS'(`GPU_WSPAWN); + op_type = `INST_OP_BITS'(`INST_GPU_WSPAWN); `USED_IREG (rs1); `USED_IREG (rs2); end 3'h2: begin - op_type = `OP_BITS'(`GPU_SPLIT); + op_type = `INST_OP_BITS'(`INST_GPU_SPLIT); is_wstall = 1; `USED_IREG (rs1); end 3'h3: begin - op_type = `OP_BITS'(`GPU_JOIN); + op_type = `INST_OP_BITS'(`INST_GPU_JOIN); is_join = 1; end 3'h4: begin - op_type = `OP_BITS'(`GPU_BAR); + op_type = `INST_OP_BITS'(`INST_GPU_BAR); is_wstall = 1; `USED_IREG (rs1); `USED_IREG (rs2); diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 87f0001d..fe1b12c3 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -14,8 +14,6 @@ `define NB_BITS `LOG2UP(`NUM_BARRIERS) -`define REQS_BITS `LOG2UP(NUM_REQS) - `ifdef EXT_F_ENABLE `define NUM_REGS 64 `else @@ -32,6 +30,16 @@ /////////////////////////////////////////////////////////////////////////////// +`define EX_NOP 3'h0 +`define EX_ALU 3'h1 +`define EX_LSU 3'h2 +`define EX_CSR 3'h3 +`define EX_FPU 3'h4 +`define EX_GPU 3'h5 +`define EX_BITS 3 + +/////////////////////////////////////////////////////////////////////////////// + `define INST_LUI 7'b0110111 `define INST_AUIPC 7'b0010111 `define INST_JAL 7'b1101111 @@ -56,142 +64,131 @@ /////////////////////////////////////////////////////////////////////////////// -`define FRM_RNE 3'b000 // round to nearest even -`define FRM_RTZ 3'b001 // round to zero -`define FRM_RDN 3'b010 // round to -inf -`define FRM_RUP 3'b011 // round to +inf -`define FRM_RMM 3'b100 // round to nearest max magnitude -`define FRM_DYN 3'b111 // dynamic mode -`define FRM_BITS 3 +`define INST_FRM_RNE 3'b000 // round to nearest even +`define INST_FRM_RTZ 3'b001 // round to zero +`define INST_FRM_RDN 3'b010 // round to -inf +`define INST_FRM_RUP 3'b011 // round to +inf +`define INST_FRM_RMM 3'b100 // round to nearest max magnitude +`define INST_FRM_DYN 3'b111 // dynamic mode +`define INST_FRM_BITS 3 /////////////////////////////////////////////////////////////////////////////// -`define EX_NOP 3'h0 -`define EX_ALU 3'h1 -`define EX_LSU 3'h2 -`define EX_CSR 3'h3 -`define EX_FPU 3'h4 -`define EX_GPU 3'h5 -`define EX_BITS 3 - -`define NUM_EXS 6 -`define NE_BITS `LOG2UP(`NUM_EXS) +`define INST_OP_BITS 4 +`define INST_MOD_BITS 3 /////////////////////////////////////////////////////////////////////////////// -`define OP_BITS 4 -`define MOD_BITS 3 +`define INST_ALU_ADD 4'b0000 +`define INST_ALU_LUI 4'b0010 +`define INST_ALU_AUIPC 4'b0011 +`define INST_ALU_SLTU 4'b0100 +`define INST_ALU_SLT 4'b0101 +`define INST_ALU_SRL 4'b1000 +`define INST_ALU_SRA 4'b1001 +`define INST_ALU_SUB 4'b1011 +`define INST_ALU_AND 4'b1100 +`define INST_ALU_OR 4'b1101 +`define INST_ALU_XOR 4'b1110 +`define INST_ALU_SLL 4'b1111 +`define INST_ALU_OTHER 4'b0111 +`define INST_ALU_BITS 4 +`define INST_ALU_OP(x) x[`INST_ALU_BITS-1:0] +`define INST_ALU_OP_CLASS(x) x[3:2] +`define INST_ALU_SIGNED(x) x[0] +`define INST_ALU_IS_BR(x) x[0] +`define INST_ALU_IS_MUL(x) x[1] -`define ALU_ADD 4'b0000 -`define ALU_LUI 4'b0010 -`define ALU_AUIPC 4'b0011 -`define ALU_SLTU 4'b0100 -`define ALU_SLT 4'b0101 -`define ALU_SRL 4'b1000 -`define ALU_SRA 4'b1001 -`define ALU_SUB 4'b1011 -`define ALU_AND 4'b1100 -`define ALU_OR 4'b1101 -`define ALU_XOR 4'b1110 -`define ALU_SLL 4'b1111 -`define ALU_OTHER 4'b0111 -`define ALU_BITS 4 -`define ALU_OP(x) x[`ALU_BITS-1:0] -`define ALU_OP_CLASS(x) x[3:2] -`define ALU_SIGNED(x) x[0] -`define ALU_IS_BR(x) x[0] -`define ALU_IS_MUL(x) x[1] +`define INST_BR_EQ 4'b0000 +`define INST_BR_NE 4'b0010 +`define INST_BR_LTU 4'b0100 +`define INST_BR_GEU 4'b0110 +`define INST_BR_LT 4'b0101 +`define INST_BR_GE 4'b0111 +`define INST_BR_JAL 4'b1000 +`define INST_BR_JALR 4'b1001 +`define INST_BR_ECALL 4'b1010 +`define INST_BR_EBREAK 4'b1011 +`define INST_BR_MRET 4'b1100 +`define INST_BR_SRET 4'b1101 +`define INST_BR_DRET 4'b1110 +`define INST_BR_OTHER 4'b1111 +`define INST_BR_BITS 4 +`define INST_BR_OP(x) x[`INST_BR_BITS-1:0] +`define INST_BR_NEG(x) x[1] +`define INST_BR_LESS(x) x[2] +`define INST_BR_STATIC(x) x[3] -`define BR_EQ 4'b0000 -`define BR_NE 4'b0010 -`define BR_LTU 4'b0100 -`define BR_GEU 4'b0110 -`define BR_LT 4'b0101 -`define BR_GE 4'b0111 -`define BR_JAL 4'b1000 -`define BR_JALR 4'b1001 -`define BR_ECALL 4'b1010 -`define BR_EBREAK 4'b1011 -`define BR_MRET 4'b1100 -`define BR_SRET 4'b1101 -`define BR_DRET 4'b1110 -`define BR_OTHER 4'b1111 -`define BR_BITS 4 -`define BR_OP(x) x[`BR_BITS-1:0] -`define BR_NEG(x) x[1] -`define BR_LESS(x) x[2] -`define BR_STATIC(x) x[3] +`define INST_MUL_MUL 3'h0 +`define INST_MUL_MULH 3'h1 +`define INST_MUL_MULHSU 3'h2 +`define INST_MUL_MULHU 3'h3 +`define INST_MUL_DIV 3'h4 +`define INST_MUL_DIVU 3'h5 +`define INST_MUL_REM 3'h6 +`define INST_MUL_REMU 3'h7 +`define INST_MUL_BITS 3 +`define INST_MUL_OP(x) x[`INST_MUL_BITS-1:0] +`define INST_MUL_IS_DIV(x) x[2] -`define MUL_MUL 3'h0 -`define MUL_MULH 3'h1 -`define MUL_MULHSU 3'h2 -`define MUL_MULHU 3'h3 -`define MUL_DIV 3'h4 -`define MUL_DIVU 3'h5 -`define MUL_REM 3'h6 -`define MUL_REMU 3'h7 -`define MUL_BITS 3 -`define MUL_OP(x) x[`MUL_BITS-1:0] -`define MUL_IS_DIV(x) x[2] +`define INST_FMT_B 3'b000 +`define INST_FMT_H 3'b001 +`define INST_FMT_W 3'b010 +`define INST_FMT_BU 3'b100 +`define INST_FMT_HU 3'b101 -`define FMT_B 3'b000 -`define FMT_H 3'b001 -`define FMT_W 3'b010 -`define FMT_BU 3'b100 -`define FMT_HU 3'b101 +`define INST_LSU_LB 4'b0000 +`define INST_LSU_LH 4'b0001 +`define INST_LSU_LW 4'b0010 +`define INST_LSU_LBU 4'b0100 +`define INST_LSU_LHU 4'b0101 +`define INST_LSU_SB 4'b1000 +`define INST_LSU_SH 4'b1001 +`define INST_LSU_SW 4'b1010 +`define INST_LSU_BITS 4 +`define INST_LSU_FMT(x) x[2:0] +`define INST_LSU_WSIZE(x) x[1:0] +`define INST_LSU_OP(x) x[`INST_LSU_BITS-1:0] +`define INST_LSU_IS_FENCE(x) x[0] -`define LSU_LB 4'b0000 -`define LSU_LH 4'b0001 -`define LSU_LW 4'b0010 -`define LSU_LBU 4'b0100 -`define LSU_LHU 4'b0101 -`define LSU_SB 4'b1000 -`define LSU_SH 4'b1001 -`define LSU_SW 4'b1010 -`define LSU_BITS 4 -`define LSU_FMT(x) x[2:0] -`define LSU_WSIZE(x) x[1:0] -`define LSU_OP(x) x[`LSU_BITS-1:0] -`define LSU_IS_FENCE(x) x[0] +`define INST_FENCE_BITS 1 +`define INST_FENCE_D 1'h0 +`define INST_FENCE_I 1'h1 -`define FENCE_BITS 1 -`define FENCE_D 1'h0 -`define FENCE_I 1'h1 +`define INST_CSR_RW 2'h1 +`define INST_CSR_RS 2'h2 +`define INST_CSR_RC 2'h3 +`define INST_CSR_OTHER 2'h0 +`define INST_CSR_BITS 2 +`define INST_CSR_OP(x) x[`INST_CSR_BITS-1:0] -`define CSR_RW 2'h1 -`define CSR_RS 2'h2 -`define CSR_RC 2'h3 -`define CSR_OTHER 2'h0 -`define CSR_BITS 2 -`define CSR_OP(x) x[`CSR_BITS-1:0] +`define INST_FPU_ADD 4'h0 +`define INST_FPU_SUB 4'h4 +`define INST_FPU_MUL 4'h8 +`define INST_FPU_DIV 4'hC +`define INST_FPU_CVTWS 4'h1 // FCVT.W.S +`define INST_FPU_CVTWUS 4'h5 // FCVT.WU.S +`define INST_FPU_CVTSW 4'h9 // FCVT.S.W +`define INST_FPU_CVTSWU 4'hD // FCVT.S.WU +`define INST_FPU_SQRT 4'h2 +`define INST_FPU_CLASS 4'h6 +`define INST_FPU_CMP 4'hA +`define INST_FPU_MISC 4'hE // SGNJ, SGNJN, SGNJX, FMIN, FMAX, MVXW, MVWX +`define INST_FPU_MADD 4'h3 +`define INST_FPU_MSUB 4'h7 +`define INST_FPU_NMSUB 4'hB +`define INST_FPU_NMADD 4'hF +`define INST_FPU_BITS 4 +`define INST_FPU_OP(x) x[`INST_FPU_BITS-1:0] -`define FPU_ADD 4'h0 -`define FPU_SUB 4'h4 -`define FPU_MUL 4'h8 -`define FPU_DIV 4'hC -`define FPU_CVTWS 4'h1 // FCVT.W.S -`define FPU_CVTWUS 4'h5 // FCVT.WU.S -`define FPU_CVTSW 4'h9 // FCVT.S.W -`define FPU_CVTSWU 4'hD // FCVT.S.WU -`define FPU_SQRT 4'h2 -`define FPU_CLASS 4'h6 -`define FPU_CMP 4'hA -`define FPU_MISC 4'hE // SGNJ, SGNJN, SGNJX, FMIN, FMAX, MVXW, MVWX -`define FPU_MADD 4'h3 -`define FPU_MSUB 4'h7 -`define FPU_NMSUB 4'hB -`define FPU_NMADD 4'hF -`define FPU_BITS 4 -`define FPU_OP(x) x[`FPU_BITS-1:0] - -`define GPU_TMC 3'h0 -`define GPU_WSPAWN 3'h1 -`define GPU_SPLIT 3'h2 -`define GPU_JOIN 3'h3 -`define GPU_BAR 3'h4 -`define GPU_OTHER 3'h7 -`define GPU_BITS 3 -`define GPU_OP(x) x[`GPU_BITS-1:0] +`define INST_GPU_TMC 3'h0 +`define INST_GPU_WSPAWN 3'h1 +`define INST_GPU_SPLIT 3'h2 +`define INST_GPU_JOIN 3'h3 +`define INST_GPU_BAR 3'h4 +`define INST_GPU_OTHER 3'h7 +`define INST_GPU_BITS 3 +`define INST_GPU_OP(x) x[`INST_GPU_BITS-1:0] /////////////////////////////////////////////////////////////////////////////// diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v index dfb45259..730f9df1 100644 --- a/hw/rtl/VX_execute.v +++ b/hw/rtl/VX_execute.v @@ -133,8 +133,8 @@ module VX_execute #( // special workaround to get RISC-V tests Pass/Fail status wire ebreak /* verilator public */; assign ebreak = alu_req_if.valid && alu_req_if.ready - && `ALU_IS_BR(alu_req_if.op_mod) - && (`BR_OP(alu_req_if.op_type) == `BR_EBREAK - || `BR_OP(alu_req_if.op_type) == `BR_ECALL); + && `INST_ALU_IS_BR(alu_req_if.op_mod) + && (`INST_BR_OP(alu_req_if.op_type) == `INST_BR_EBREAK + || `INST_BR_OP(alu_req_if.op_type) == `INST_BR_ECALL); endmodule diff --git a/hw/rtl/VX_fpu_unit.v b/hw/rtl/VX_fpu_unit.v index a1e991c4..cba4d399 100644 --- a/hw/rtl/VX_fpu_unit.v +++ b/hw/rtl/VX_fpu_unit.v @@ -61,7 +61,7 @@ module VX_fpu_unit #( // resolve dynamic FRM from CSR assign fpu_to_csr_if.read_wid = fpu_req_if.wid; - wire [`FRM_BITS-1:0] fpu_frm = (fpu_req_if.op_mod == `FRM_DYN) ? fpu_to_csr_if.read_frm : fpu_req_if.op_mod; + wire [`INST_FRM_BITS-1:0] fpu_frm = (fpu_req_if.op_mod == `INST_FRM_DYN) ? fpu_to_csr_if.read_frm : fpu_req_if.op_mod; `ifdef FPU_DPI @@ -179,7 +179,7 @@ module VX_fpu_unit #( wire stall_out = ~fpu_commit_if.ready && fpu_commit_if.valid; VX_pipe_register #( - .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `FFG_BITS), + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `FFLAGS_BITS), .RESETW (1) ) pipe_reg ( .clk (clk), diff --git a/hw/rtl/VX_gpu_unit.v b/hw/rtl/VX_gpu_unit.v index 403bed95..e63f8e1b 100644 --- a/hw/rtl/VX_gpu_unit.v +++ b/hw/rtl/VX_gpu_unit.v @@ -25,10 +25,10 @@ module VX_gpu_unit #( gpu_barrier_t barrier; gpu_split_t split; - wire is_wspawn = (gpu_req_if.op_type == `GPU_WSPAWN); - wire is_tmc = (gpu_req_if.op_type == `GPU_TMC); - wire is_split = (gpu_req_if.op_type == `GPU_SPLIT); - wire is_bar = (gpu_req_if.op_type == `GPU_BAR); + wire is_wspawn = (gpu_req_if.op_type == `INST_GPU_WSPAWN); + wire is_tmc = (gpu_req_if.op_type == `INST_GPU_TMC); + wire is_split = (gpu_req_if.op_type == `INST_GPU_SPLIT); + wire is_bar = (gpu_req_if.op_type == `INST_GPU_BAR); // tmc diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.v index 7b62c3a4..8aaa02bb 100644 --- a/hw/rtl/VX_ibuffer.v +++ b/hw/rtl/VX_ibuffer.v @@ -15,7 +15,7 @@ module VX_ibuffer #( `UNUSED_PARAM (CORE_ID) - localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS; + localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `INST_OP_BITS + `INST_FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS; localparam ADDRW = $clog2(`IBUF_SIZE+1); localparam NWARPSW = $clog2(`NUM_WARPS+1); diff --git a/hw/rtl/VX_instr_demux.v b/hw/rtl/VX_instr_demux.v index e497bfcb..6b0423d7 100644 --- a/hw/rtl/VX_instr_demux.v +++ b/hw/rtl/VX_instr_demux.v @@ -41,15 +41,15 @@ module VX_instr_demux ( wire alu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_ALU); VX_skid_buffer #( - .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BITS + `MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)), + .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `INST_ALU_BITS + `INST_MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)), .OUTPUT_REG (1) ) alu_buffer ( .clk (clk), .reset (reset), .valid_in (alu_req_valid), .ready_in (alu_req_ready), - .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, `ALU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.imm, ibuffer_if.use_PC, ibuffer_if.use_imm, ibuffer_if.rd, ibuffer_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.op_mod, alu_req_if.imm, alu_req_if.use_PC, alu_req_if.use_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}), + .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, `INST_ALU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.imm, ibuffer_if.use_PC, ibuffer_if.use_imm, ibuffer_if.rd, ibuffer_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), + .data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.op_mod, alu_req_if.imm, alu_req_if.use_PC, alu_req_if.use_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}), .valid_out (alu_req_if.valid), .ready_out (alu_req_if.ready) ); @@ -57,18 +57,18 @@ module VX_instr_demux ( // lsu unit wire lsu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_LSU); - wire lsu_is_fence = `LSU_IS_FENCE(ibuffer_if.op_mod); + wire lsu_is_fence = `INST_LSU_IS_FENCE(ibuffer_if.op_mod); VX_skid_buffer #( - .DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 1 + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)), + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `INST_LSU_BITS + 1 + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)), .OUTPUT_REG (1) ) lsu_buffer ( .clk (clk), .reset (reset), .valid_in (lsu_req_valid), .ready_in (lsu_req_ready), - .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `LSU_OP(ibuffer_if.op_type), lsu_is_fence, ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.is_fence, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}), + .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `INST_LSU_OP(ibuffer_if.op_type), lsu_is_fence, ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), + .data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.is_fence, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}), .valid_out (lsu_req_if.valid), .ready_out (lsu_req_if.ready) ); @@ -78,15 +78,15 @@ module VX_instr_demux ( wire csr_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_CSR); VX_skid_buffer #( - .DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32), + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `INST_CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32), .OUTPUT_REG (1) ) csr_buffer ( .clk (clk), .reset (reset), .valid_in (csr_req_valid), .ready_in (csr_req_ready), - .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `CSR_OP(ibuffer_if.op_type), ibuffer_if.imm[`CSR_ADDR_BITS-1:0], ibuffer_if.rd, ibuffer_if.wb, ibuffer_if.use_imm, ibuffer_if.rs1, gpr_rsp_if.rs1_data[0]}), - .data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.rs1, csr_req_if.rs1_data}), + .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `INST_CSR_OP(ibuffer_if.op_type), ibuffer_if.imm[`CSR_ADDR_BITS-1:0], ibuffer_if.rd, ibuffer_if.wb, ibuffer_if.use_imm, ibuffer_if.rs1, gpr_rsp_if.rs1_data[0]}), + .data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.rs1, csr_req_if.rs1_data}), .valid_out (csr_req_if.valid), .ready_out (csr_req_if.ready) ); @@ -97,15 +97,15 @@ module VX_instr_demux ( wire fpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_FPU); VX_skid_buffer #( - .DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)), + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `INST_FPU_BITS + `INST_MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)), .OUTPUT_REG (1) ) fpu_buffer ( .clk (clk), .reset (reset), .valid_in (fpu_req_valid), .ready_in (fpu_req_ready), - .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `FPU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), - .data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}), + .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `INST_FPU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), + .data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}), .valid_out (fpu_req_if.valid), .ready_out (fpu_req_if.ready) ); @@ -118,15 +118,15 @@ module VX_instr_demux ( wire gpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_GPU); VX_skid_buffer #( - .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + + `NT_BITS + (`NUM_THREADS * 32 + 32)), + .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `INST_GPU_BITS + `NR_BITS + 1 + + `NT_BITS + (`NUM_THREADS * 32 + 32)), .OUTPUT_REG (1) ) gpu_buffer ( .clk (clk), .reset (reset), .valid_in (gpu_req_valid), .ready_in (gpu_req_ready), - .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, `GPU_OP(ibuffer_if.op_type), ibuffer_if.rd, ibuffer_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data[0]}), - .data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.tid, gpu_req_if.rs1_data, gpu_req_if.rs2_data}), + .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, `INST_GPU_OP(ibuffer_if.op_type), ibuffer_if.rd, ibuffer_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data[0]}), + .data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.tid, gpu_req_if.rs1_data, gpu_req_if.rs2_data}), .valid_out (gpu_req_if.valid), .ready_out (gpu_req_if.ready) ); diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 8adc6eed..b9a2ef5e 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -33,7 +33,7 @@ module VX_lsu_unit #( wire req_valid; wire [`NUM_THREADS-1:0] req_tmask; wire [`NUM_THREADS-1:0][31:0] req_addr; - wire [`LSU_BITS-1:0] req_type; + wire [`INST_LSU_BITS-1:0] req_type; wire [`NUM_THREADS-1:0][31:0] req_data; wire [`NR_BITS-1:0] req_rd; wire req_wb; @@ -80,7 +80,7 @@ module VX_lsu_unit #( wire lsu_valid = lsu_req_if.valid && ~fence_wait; VX_pipe_register #( - .DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + (`NUM_THREADS * ADDR_TYPEW) + `LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)), + .DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + (`NUM_THREADS * ADDR_TYPEW) + `INST_LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)), .RESETW (1) ) req_pipe_reg ( .clk (clk), @@ -97,7 +97,7 @@ module VX_lsu_unit #( wire [31:0] rsp_pc; wire [`NR_BITS-1:0] rsp_rd; wire rsp_wb; - wire [`LSU_BITS-1:0] rsp_type; + wire [`INST_LSU_BITS-1:0] rsp_type; wire rsp_is_dup; `UNUSED_VAR (rsp_type) @@ -132,8 +132,8 @@ module VX_lsu_unit #( assign mbuf_raddr = dcache_rsp_if.tag[ADDR_TYPEW +: `LSUQ_ADDR_BITS]; VX_index_buffer #( - .DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1), - .SIZE (`LSUQ_SIZE) + .DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `INST_LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1), + .SIZE (`LSUQ_SIZE) ) req_metadata ( .clk (clk), .reset (reset), @@ -202,7 +202,7 @@ module VX_lsu_unit #( always @(*) begin mem_req_byteen = {4{req_wb}}; - case (`LSU_WSIZE(req_type)) + case (`INST_LSU_WSIZE(req_type)) 0: mem_req_byteen[req_offset[i]] = 1; 1: begin mem_req_byteen[req_offset[i]] = 1; @@ -261,11 +261,11 @@ module VX_lsu_unit #( wire [7:0] rsp_data8 = rsp_offset[i][0] ? rsp_data16[15:8] : rsp_data16[7:0]; always @(*) begin - case (`LSU_FMT(rsp_type)) - `FMT_B: rsp_data[i] = 32'(signed'(rsp_data8)); - `FMT_H: rsp_data[i] = 32'(signed'(rsp_data16)); - `FMT_BU: rsp_data[i] = 32'(unsigned'(rsp_data8)); - `FMT_HU: rsp_data[i] = 32'(unsigned'(rsp_data16)); + case (`INST_LSU_FMT(rsp_type)) + `INST_FMT_B: rsp_data[i] = 32'(signed'(rsp_data8)); + `INST_FMT_H: rsp_data[i] = 32'(signed'(rsp_data16)); + `INST_FMT_BU: rsp_data[i] = 32'(unsigned'(rsp_data8)); + `INST_FMT_HU: rsp_data[i] = 32'(unsigned'(rsp_data16)); default: rsp_data[i] = rsp_data32; endcase end diff --git a/hw/rtl/VX_muldiv.v b/hw/rtl/VX_muldiv.v index 8a0a466e..107e6785 100644 --- a/hw/rtl/VX_muldiv.v +++ b/hw/rtl/VX_muldiv.v @@ -5,7 +5,7 @@ module VX_muldiv ( input wire reset, // Inputs - input wire [`MUL_BITS-1:0] alu_op, + input wire [`INST_MUL_BITS-1:0] alu_op, input wire [`NW_BITS-1:0] wid_in, input wire [`NUM_THREADS-1:0] tmask_in, input wire [31:0] PC_in, @@ -29,7 +29,7 @@ module VX_muldiv ( input wire ready_out ); - wire is_div_op = `MUL_IS_DIV(alu_op); + wire is_div_op = `INST_MUL_IS_DIV(alu_op); wire [`NUM_THREADS-1:0][31:0] mul_result; wire [`NW_BITS-1:0] mul_wid_out; @@ -44,9 +44,9 @@ module VX_muldiv ( wire mul_valid_in = valid_in && !is_div_op; wire mul_ready_in = ~stall_out || ~mul_valid_out; - wire is_mulh_in = (alu_op != `MUL_MUL); - wire is_signed_mul_a = (alu_op != `MUL_MULHU); - wire is_signed_mul_b = (alu_op != `MUL_MULHU && alu_op != `MUL_MULHSU); + wire is_mulh_in = (alu_op != `INST_MUL_MUL); + wire is_signed_mul_a = (alu_op != `INST_MUL_MULHU); + wire is_signed_mul_b = (alu_op != `INST_MUL_MULHU && alu_op != `INST_MUL_MULHSU); `ifdef IMUL_DPI @@ -123,8 +123,8 @@ module VX_muldiv ( wire [`NR_BITS-1:0] div_rd_out; wire div_wb_out; - wire is_rem_op_in = (alu_op == `MUL_REM) || (alu_op == `MUL_REMU); - wire is_signed_div = (alu_op == `MUL_DIV) || (alu_op == `MUL_REM); + wire is_rem_op_in = (alu_op == `INST_MUL_REM) || (alu_op == `INST_MUL_REMU); + wire is_signed_div = (alu_op == `INST_MUL_DIV) || (alu_op == `INST_MUL_REM); wire div_valid_in = valid_in && is_div_op; wire div_ready_out = ~stall_out && ~mul_valid_out; // arbitration prioritizes MUL wire div_ready_in; diff --git a/hw/rtl/VX_print_instr.vh b/hw/rtl/VX_print_instr.vh index 2931bc9f..24fc73a0 100644 --- a/hw/rtl/VX_print_instr.vh +++ b/hw/rtl/VX_print_instr.vh @@ -18,104 +18,104 @@ endtask task print_ex_op ( input [`EX_BITS-1:0] ex_type, - input [`OP_BITS-1:0] op_type, - input [`MOD_BITS-1:0] op_mod + input [`INST_OP_BITS-1:0] op_type, + input [`INST_MOD_BITS-1:0] op_mod ); case (ex_type) `EX_ALU: begin - if (`ALU_IS_BR(op_mod)) begin - case (`BR_BITS'(op_type)) - `BR_EQ: dpi_trace("BEQ"); - `BR_NE: dpi_trace("BNE"); - `BR_LT: dpi_trace("BLT"); - `BR_GE: dpi_trace("BGE"); - `BR_LTU: dpi_trace("BLTU"); - `BR_GEU: dpi_trace("BGEU"); - `BR_JAL: dpi_trace("JAL"); - `BR_JALR: dpi_trace("JALR"); - `BR_ECALL: dpi_trace("ECALL"); - `BR_EBREAK:dpi_trace("EBREAK"); - `BR_MRET: dpi_trace("MRET"); - `BR_SRET: dpi_trace("SRET"); - `BR_DRET: dpi_trace("DRET"); + if (`INST_ALU_IS_BR(op_mod)) begin + case (`INST_BR_BITS'(op_type)) + `INST_BR_EQ: dpi_trace("BEQ"); + `INST_BR_NE: dpi_trace("BNE"); + `INST_BR_LT: dpi_trace("BLT"); + `INST_BR_GE: dpi_trace("BGE"); + `INST_BR_LTU: dpi_trace("BLTU"); + `INST_BR_GEU: dpi_trace("BGEU"); + `INST_BR_JAL: dpi_trace("JAL"); + `INST_BR_JALR: dpi_trace("JALR"); + `INST_BR_ECALL: dpi_trace("ECALL"); + `INST_BR_EBREAK:dpi_trace("EBREAK"); + `INST_BR_MRET: dpi_trace("MRET"); + `INST_BR_SRET: dpi_trace("SRET"); + `INST_BR_DRET: dpi_trace("DRET"); default: dpi_trace("?"); endcase - end else if (`ALU_IS_MUL(op_mod)) begin - case (`MUL_BITS'(op_type)) - `MUL_MUL: dpi_trace("MUL"); - `MUL_MULH: dpi_trace("MULH"); - `MUL_MULHSU:dpi_trace("MULHSU"); - `MUL_MULHU: dpi_trace("MULHU"); - `MUL_DIV: dpi_trace("DIV"); - `MUL_DIVU: dpi_trace("DIVU"); - `MUL_REM: dpi_trace("REM"); - `MUL_REMU: dpi_trace("REMU"); + end else if (`INST_ALU_IS_MUL(op_mod)) begin + case (`INST_MUL_BITS'(op_type)) + `INST_MUL_MUL: dpi_trace("MUL"); + `INST_MUL_MULH: dpi_trace("MULH"); + `INST_MUL_MULHSU:dpi_trace("MULHSU"); + `INST_MUL_MULHU: dpi_trace("MULHU"); + `INST_MUL_DIV: dpi_trace("DIV"); + `INST_MUL_DIVU: dpi_trace("DIVU"); + `INST_MUL_REM: dpi_trace("REM"); + `INST_MUL_REMU: dpi_trace("REMU"); default: dpi_trace("?"); endcase end else begin - case (`ALU_BITS'(op_type)) - `ALU_ADD: dpi_trace("ADD"); - `ALU_SUB: dpi_trace("SUB"); - `ALU_SLL: dpi_trace("SLL"); - `ALU_SRL: dpi_trace("SRL"); - `ALU_SRA: dpi_trace("SRA"); - `ALU_SLT: dpi_trace("SLT"); - `ALU_SLTU: dpi_trace("SLTU"); - `ALU_XOR: dpi_trace("XOR"); - `ALU_OR: dpi_trace("OR"); - `ALU_AND: dpi_trace("AND"); - `ALU_LUI: dpi_trace("LUI"); - `ALU_AUIPC: dpi_trace("AUIPC"); + case (`INST_ALU_BITS'(op_type)) + `INST_ALU_ADD: dpi_trace("ADD"); + `INST_ALU_SUB: dpi_trace("SUB"); + `INST_ALU_SLL: dpi_trace("SLL"); + `INST_ALU_SRL: dpi_trace("SRL"); + `INST_ALU_SRA: dpi_trace("SRA"); + `INST_ALU_SLT: dpi_trace("SLT"); + `INST_ALU_SLTU: dpi_trace("SLTU"); + `INST_ALU_XOR: dpi_trace("XOR"); + `INST_ALU_OR: dpi_trace("OR"); + `INST_ALU_AND: dpi_trace("AND"); + `INST_ALU_LUI: dpi_trace("LUI"); + `INST_ALU_AUIPC: dpi_trace("AUIPC"); default: dpi_trace("?"); endcase end end `EX_LSU: begin if (op_mod == 0) begin - case (`LSU_BITS'(op_type)) - `LSU_LB: dpi_trace("LB"); - `LSU_LH: dpi_trace("LH"); - `LSU_LW: dpi_trace("LW"); - `LSU_LBU:dpi_trace("LBU"); - `LSU_LHU:dpi_trace("LHU"); - `LSU_SB: dpi_trace("SB"); - `LSU_SH: dpi_trace("SH"); - `LSU_SW: dpi_trace("SW"); + case (`INST_LSU_BITS'(op_type)) + `INST_LSU_LB: dpi_trace("LB"); + `INST_LSU_LH: dpi_trace("LH"); + `INST_LSU_LW: dpi_trace("LW"); + `INST_LSU_LBU:dpi_trace("LBU"); + `INST_LSU_LHU:dpi_trace("LHU"); + `INST_LSU_SB: dpi_trace("SB"); + `INST_LSU_SH: dpi_trace("SH"); + `INST_LSU_SW: dpi_trace("SW"); default: dpi_trace("?"); endcase end else if (op_mod == 1) begin - case (`FENCE_BITS'(op_type)) - `FENCE_D: dpi_trace("DFENCE"); - `FENCE_I: dpi_trace("IFENCE"); + case (`INST_FENCE_BITS'(op_type)) + `INST_FENCE_D: dpi_trace("DFENCE"); + `INST_FENCE_I: dpi_trace("IFENCE"); default: dpi_trace("?"); endcase end end `EX_CSR: begin - case (`CSR_BITS'(op_type)) - `CSR_RW: dpi_trace("CSRW"); - `CSR_RS: dpi_trace("CSRS"); - `CSR_RC: dpi_trace("CSRC"); + case (`INST_CSR_BITS'(op_type)) + `INST_CSR_RW: dpi_trace("CSRW"); + `INST_CSR_RS: dpi_trace("CSRS"); + `INST_CSR_RC: dpi_trace("CSRC"); default: dpi_trace("?"); endcase end `EX_FPU: begin - case (`FPU_BITS'(op_type)) - `FPU_ADD: dpi_trace("ADD"); - `FPU_SUB: dpi_trace("SUB"); - `FPU_MUL: dpi_trace("MUL"); - `FPU_DIV: dpi_trace("DIV"); - `FPU_SQRT: dpi_trace("SQRT"); - `FPU_MADD: dpi_trace("MADD"); - `FPU_NMSUB: dpi_trace("NMSUB"); - `FPU_NMADD: dpi_trace("NMADD"); - `FPU_CVTWS: dpi_trace("CVTWS"); - `FPU_CVTWUS:dpi_trace("CVTWUS"); - `FPU_CVTSW: dpi_trace("CVTSW"); - `FPU_CVTSWU:dpi_trace("CVTSWU"); - `FPU_CLASS: dpi_trace("CLASS"); - `FPU_CMP: dpi_trace("CMP"); - `FPU_MISC: begin + case (`INST_FPU_BITS'(op_type)) + `INST_FPU_ADD: dpi_trace("ADD"); + `INST_FPU_SUB: dpi_trace("SUB"); + `INST_FPU_MUL: dpi_trace("MUL"); + `INST_FPU_DIV: dpi_trace("DIV"); + `INST_FPU_SQRT: dpi_trace("SQRT"); + `INST_FPU_MADD: dpi_trace("MADD"); + `INST_FPU_NMSUB: dpi_trace("NMSUB"); + `INST_FPU_NMADD: dpi_trace("NMADD"); + `INST_FPU_CVTWS: dpi_trace("CVTWS"); + `INST_FPU_CVTWUS:dpi_trace("CVTWUS"); + `INST_FPU_CVTSW: dpi_trace("CVTSW"); + `INST_FPU_CVTSWU:dpi_trace("CVTSWU"); + `INST_FPU_CLASS: dpi_trace("CLASS"); + `INST_FPU_CMP: dpi_trace("CMP"); + `INST_FPU_MISC: begin case (op_mod) 0: dpi_trace("SGNJ"); 1: dpi_trace("SGNJN"); @@ -130,12 +130,12 @@ task print_ex_op ( endcase end `EX_GPU: begin - case (`GPU_BITS'(op_type)) - `GPU_TMC: dpi_trace("TMC"); - `GPU_WSPAWN:dpi_trace("WSPAWN"); - `GPU_SPLIT: dpi_trace("SPLIT"); - `GPU_JOIN: dpi_trace("JOIN"); - `GPU_BAR: dpi_trace("BAR"); + case (`INST_GPU_BITS'(op_type)) + `INST_GPU_TMC: dpi_trace("TMC"); + `INST_GPU_WSPAWN:dpi_trace("WSPAWN"); + `INST_GPU_SPLIT: dpi_trace("SPLIT"); + `INST_GPU_JOIN: dpi_trace("JOIN"); + `INST_GPU_BAR: dpi_trace("BAR"); default: dpi_trace("?"); endcase end diff --git a/hw/rtl/VX_types.vh b/hw/rtl/VX_types.vh index d444db0d..785ce444 100644 --- a/hw/rtl/VX_types.vh +++ b/hw/rtl/VX_types.vh @@ -21,7 +21,7 @@ typedef struct packed { logic NX; // 0-Inexact } fflags_t; -`define FFG_BITS $bits(fflags_t) +`define FFLAGS_BITS $bits(fflags_t) typedef struct packed { logic valid; diff --git a/hw/rtl/fp_cores/VX_fp_cvt.v b/hw/rtl/fp_cores/VX_fp_cvt.v index 1e823363..25e178c3 100644 --- a/hw/rtl/fp_cores/VX_fp_cvt.v +++ b/hw/rtl/fp_cores/VX_fp_cvt.v @@ -15,7 +15,7 @@ module VX_fp_cvt #( input wire [TAGW-1:0] tag_in, - input wire [`FRM_BITS-1:0] frm, + input wire [`INST_FRM_BITS-1:0] frm, input wire is_itof, input wire is_signed, @@ -101,7 +101,7 @@ module VX_fp_cvt #( wire stall; VX_pipe_register #( - .DATAW (1 + TAGW + 1 + `FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)), + .DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)), .RESETW (1) ) pipe_reg0 ( .clk (clk), @@ -167,7 +167,7 @@ module VX_fp_cvt #( wire [LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_s1; VX_pipe_register #( - .DATAW (1 + TAGW + 1 + `FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)), + .DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)), .RESETW (1) ) pipe_reg1 ( .clk (clk), @@ -253,7 +253,7 @@ module VX_fp_cvt #( wire [LANES-1:0] of_before_round_s2; VX_pipe_register #( - .DATAW (1 + TAGW + 1 + 1 + `FRM_BITS + LANES * ($bits(fp_type_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)), + .DATAW (1 + TAGW + 1 + 1 + `INST_FRM_BITS + LANES * ($bits(fp_type_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)), .RESETW (1) ) pipe_reg2 ( .clk (clk), @@ -435,7 +435,7 @@ module VX_fp_cvt #( assign stall = ~ready_out && valid_out; VX_pipe_register #( - .DATAW (1 + TAGW + (LANES * 32) + (LANES * `FFG_BITS)), + .DATAW (1 + TAGW + (LANES * 32) + (LANES * `FFLAGS_BITS)), .RESETW (1) ) pipe_reg4 ( .clk (clk), diff --git a/hw/rtl/fp_cores/VX_fp_div.v b/hw/rtl/fp_cores/VX_fp_div.v index 8dd110d3..163b4c0e 100644 --- a/hw/rtl/fp_cores/VX_fp_div.v +++ b/hw/rtl/fp_cores/VX_fp_div.v @@ -16,7 +16,7 @@ module VX_fp_div #( input wire [TAGW-1:0] tag_in, - input wire [`FRM_BITS-1:0] frm, + input wire [`INST_FRM_BITS-1:0] frm, input wire [LANES-1:0][31:0] dataa, input wire [LANES-1:0][31:0] datab, diff --git a/hw/rtl/fp_cores/VX_fp_fma.v b/hw/rtl/fp_cores/VX_fp_fma.v index faf26e87..13ee473b 100644 --- a/hw/rtl/fp_cores/VX_fp_fma.v +++ b/hw/rtl/fp_cores/VX_fp_fma.v @@ -16,7 +16,7 @@ module VX_fp_fma #( input wire [TAGW-1:0] tag_in, - input wire [`FRM_BITS-1:0] frm, + input wire [`INST_FRM_BITS-1:0] frm, input wire do_madd, input wire do_sub, diff --git a/hw/rtl/fp_cores/VX_fp_ncomp.v b/hw/rtl/fp_cores/VX_fp_ncomp.v index faf6ff38..11300a87 100644 --- a/hw/rtl/fp_cores/VX_fp_ncomp.v +++ b/hw/rtl/fp_cores/VX_fp_ncomp.v @@ -15,8 +15,8 @@ module VX_fp_ncomp #( input wire [TAGW-1:0] tag_in, - input wire [`FPU_BITS-1:0] op_type, - input wire [`FRM_BITS-1:0] frm, + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_FRM_BITS-1:0] frm, input wire [LANES-1:0][31:0] dataa, input wire [LANES-1:0][31:0] datab, @@ -77,8 +77,8 @@ module VX_fp_ncomp #( wire valid_in_s0; wire [TAGW-1:0] tag_in_s0; - wire [`FPU_BITS-1:0] op_type_s0; - wire [`FRM_BITS-1:0] frm_s0; + wire [`INST_FPU_BITS-1:0] op_type_s0; + wire [`INST_FRM_BITS-1:0] frm_s0; wire [LANES-1:0][31:0] dataa_s0, datab_s0; wire [LANES-1:0] a_sign_s0, b_sign_s0; wire [LANES-1:0][7:0] a_exponent_s0; @@ -89,7 +89,7 @@ module VX_fp_ncomp #( wire stall; VX_pipe_register #( - .DATAW (1 + TAGW + `FPU_BITS + `FRM_BITS + LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fp_type_t) + 1 + 1)), + .DATAW (1 + TAGW + `INST_FPU_BITS + `INST_FRM_BITS + LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fp_type_t) + 1 + 1)), .RESETW (1), .DEPTH (0) ) pipe_reg0 ( @@ -164,7 +164,7 @@ module VX_fp_ncomp #( for (genvar i = 0; i < LANES; i++) begin always @(*) begin case (frm_s0) - `FRM_RNE: begin // LE + `INST_FRM_RNE: begin // LE fcmp_fflags[i] = 5'h0; if (a_type_s0[i].is_nan || b_type_s0[i].is_nan) begin fcmp_res[i] = 32'h0; @@ -173,7 +173,7 @@ module VX_fp_ncomp #( fcmp_res[i] = {31'h0, (a_smaller_s0[i] | ab_equal_s0[i])}; end end - `FRM_RTZ: begin // LS + `INST_FRM_RTZ: begin // LS fcmp_fflags[i] = 5'h0; if (a_type_s0[i].is_nan || b_type_s0[i].is_nan) begin fcmp_res[i] = 32'h0; @@ -182,7 +182,7 @@ module VX_fp_ncomp #( fcmp_res[i] = {31'h0, (a_smaller_s0[i] & ~ab_equal_s0[i])}; end end - `FRM_RDN: begin // EQ + `INST_FRM_RDN: begin // EQ fcmp_fflags[i] = 5'h0; if (a_type_s0[i].is_nan || b_type_s0[i].is_nan) begin fcmp_res[i] = 32'h0; @@ -207,11 +207,11 @@ module VX_fp_ncomp #( for (genvar i = 0; i < LANES; i++) begin always @(*) begin case (op_type_s0) - `FPU_CLASS: begin + `INST_FPU_CLASS: begin tmp_result[i] = fclass_mask[i]; tmp_fflags[i] = 'x; end - `FPU_CMP: begin + `INST_FPU_CMP: begin tmp_result[i] = fcmp_res[i]; tmp_fflags[i] = fcmp_fflags[i]; end @@ -238,15 +238,15 @@ module VX_fp_ncomp #( end end - wire has_fflags_s0 = ((op_type_s0 == `FPU_MISC) - && (frm_s0 == 3 // MIN - || frm_s0 == 4)) // MAX - || (op_type_s0 == `FPU_CMP); // CMP + wire has_fflags_s0 = ((op_type_s0 == `INST_FPU_MISC) + && (frm_s0 == 3 // MIN + || frm_s0 == 4)) // MAX + || (op_type_s0 == `INST_FPU_CMP); // CMP assign stall = ~ready_out && valid_out; VX_pipe_register #( - .DATAW (1 + TAGW + (LANES * 32) + 1 + (LANES * `FFG_BITS)), + .DATAW (1 + TAGW + (LANES * 32) + 1 + (LANES * `FFLAGS_BITS)), .RESETW (1) ) pipe_reg1 ( .clk (clk), diff --git a/hw/rtl/fp_cores/VX_fp_rounding.v b/hw/rtl/fp_cores/VX_fp_rounding.v index 9e544e44..654f6e8d 100644 --- a/hw/rtl/fp_cores/VX_fp_rounding.v +++ b/hw/rtl/fp_cores/VX_fp_rounding.v @@ -34,7 +34,7 @@ module VX_fp_rounding #( always @(*) begin case (rnd_mode_i) - `FRM_RNE: // Decide accoring to round/sticky bits + `INST_FRM_RNE: // Decide accoring to round/sticky bits case (round_sticky_bits_i) 2'b00, 2'b01: round_up = 1'b0; // < ulp/2 away, round down @@ -42,10 +42,10 @@ module VX_fp_rounding #( 2'b11: round_up = 1'b1; // > ulp/2 away, round up default: round_up = 1'bx; endcase - `FRM_RTZ: round_up = 1'b0; // always round down - `FRM_RDN: round_up = (| round_sticky_bits_i) & sign_i; // to 0 if +, away if - - `FRM_RUP: round_up = (| round_sticky_bits_i) & ~sign_i; // to 0 if -, away if + - `FRM_RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up + `INST_FRM_RTZ: round_up = 1'b0; // always round down + `INST_FRM_RDN: round_up = (| round_sticky_bits_i) & sign_i; // to 0 if +, away if - + `INST_FRM_RUP: round_up = (| round_sticky_bits_i) & ~sign_i; // to 0 if -, away if + + `INST_FRM_RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up default: round_up = 1'bx; // propagate x endcase end @@ -58,7 +58,7 @@ module VX_fp_rounding #( // In case of effective subtraction (thus signs of addition operands must have differed) and a // true zero result, the result sign is '-' in case of RDN and '+' for other modes. - assign sign_o = (exact_zero_o && effective_subtraction_i) ? (rnd_mode_i == `FRM_RDN) + assign sign_o = (exact_zero_o && effective_subtraction_i) ? (rnd_mode_i == `INST_FRM_RDN) : sign_i; endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_sqrt.v b/hw/rtl/fp_cores/VX_fp_sqrt.v index 1debc04d..dc1b2bcb 100644 --- a/hw/rtl/fp_cores/VX_fp_sqrt.v +++ b/hw/rtl/fp_cores/VX_fp_sqrt.v @@ -16,7 +16,7 @@ module VX_fp_sqrt #( input wire [TAGW-1:0] tag_in, - input wire [`FRM_BITS-1:0] frm, + input wire [`INST_FRM_BITS-1:0] frm, input wire [LANES-1:0][31:0] dataa, output wire [LANES-1:0][31:0] result, diff --git a/hw/rtl/fp_cores/VX_fpu_dpi.v b/hw/rtl/fp_cores/VX_fpu_dpi.v index 10dab769..bd87485b 100644 --- a/hw/rtl/fp_cores/VX_fpu_dpi.v +++ b/hw/rtl/fp_cores/VX_fpu_dpi.v @@ -14,8 +14,8 @@ module VX_fpu_dpi #( input wire [TAGW-1:0] tag_in, - input wire [`FPU_BITS-1:0] op_type, - input wire [`MOD_BITS-1:0] frm, + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_MOD_BITS-1:0] frm, input wire [`NUM_THREADS-1:0][31:0] dataa, input wire [`NUM_THREADS-1:0][31:0] datab, @@ -76,21 +76,21 @@ module VX_fpu_dpi #( is_fsgnjx = 0; case (op_type) - `FPU_ADD: begin core_select = FPU_FMA; is_fadd = 1; end - `FPU_SUB: begin core_select = FPU_FMA; is_fsub = 1; end - `FPU_MUL: begin core_select = FPU_FMA; is_fmul = 1; end - `FPU_MADD: begin core_select = FPU_FMA; is_fmadd = 1; end - `FPU_MSUB: begin core_select = FPU_FMA; is_fmsub = 1; end - `FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = 1; end - `FPU_NMSUB: begin core_select = FPU_FMA; is_fnmsub = 1; end - `FPU_DIV: begin core_select = FPU_DIV; end - `FPU_SQRT: begin core_select = FPU_SQRT; end - `FPU_CVTWS: begin core_select = FPU_CVT; is_ftoi = 1; end - `FPU_CVTWUS:begin core_select = FPU_CVT; is_ftou = 1; end - `FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; end - `FPU_CVTSWU:begin core_select = FPU_CVT; is_utof = 1; end - `FPU_CLASS: begin core_select = FPU_NCP; is_fclss = 1; end - `FPU_CMP: begin core_select = FPU_NCP; + `INST_FPU_ADD: begin core_select = FPU_FMA; is_fadd = 1; end + `INST_FPU_SUB: begin core_select = FPU_FMA; is_fsub = 1; end + `INST_FPU_MUL: begin core_select = FPU_FMA; is_fmul = 1; end + `INST_FPU_MADD: begin core_select = FPU_FMA; is_fmadd = 1; end + `INST_FPU_MSUB: begin core_select = FPU_FMA; is_fmsub = 1; end + `INST_FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = 1; end + `INST_FPU_NMSUB: begin core_select = FPU_FMA; is_fnmsub = 1; end + `INST_FPU_DIV: begin core_select = FPU_DIV; end + `INST_FPU_SQRT: begin core_select = FPU_SQRT; end + `INST_FPU_CVTWS: begin core_select = FPU_CVT; is_ftoi = 1; end + `INST_FPU_CVTWUS:begin core_select = FPU_CVT; is_ftou = 1; end + `INST_FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; end + `INST_FPU_CVTSWU:begin core_select = FPU_CVT; is_utof = 1; end + `INST_FPU_CLASS: begin core_select = FPU_NCP; is_fclss = 1; end + `INST_FPU_CMP: begin core_select = FPU_NCP; is_fle = (frm == 0); is_flt = (frm == 1); is_feq = (frm == 2); diff --git a/hw/rtl/fp_cores/VX_fpu_fpga.v b/hw/rtl/fp_cores/VX_fpu_fpga.v index 791d1f4c..f07afb0d 100644 --- a/hw/rtl/fp_cores/VX_fpu_fpga.v +++ b/hw/rtl/fp_cores/VX_fpu_fpga.v @@ -11,8 +11,8 @@ module VX_fpu_fpga #( input wire [TAGW-1:0] tag_in, - input wire [`FPU_BITS-1:0] op_type, - input wire [`MOD_BITS-1:0] frm, + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_MOD_BITS-1:0] frm, input wire [`NUM_THREADS-1:0][31:0] dataa, input wire [`NUM_THREADS-1:0][31:0] datab, @@ -54,19 +54,19 @@ module VX_fpu_fpga #( is_itof = 0; is_signed = 0; case (op_type) - `FPU_ADD: begin core_select = FPU_FMA; end - `FPU_SUB: begin core_select = FPU_FMA; do_sub = 1; end - `FPU_MUL: begin core_select = FPU_FMA; do_neg = 1; end - `FPU_MADD: begin core_select = FPU_FMA; do_madd = 1; end - `FPU_MSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; end - `FPU_NMADD: begin core_select = FPU_FMA; do_madd = 1; do_neg = 1; end - `FPU_NMSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; do_neg = 1; end - `FPU_DIV: begin core_select = FPU_DIV; end - `FPU_SQRT: begin core_select = FPU_SQRT; end - `FPU_CVTWS: begin core_select = FPU_CVT; is_signed = 1; end - `FPU_CVTWUS: begin core_select = FPU_CVT; end - `FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; is_signed = 1; end - `FPU_CVTSWU: begin core_select = FPU_CVT; is_itof = 1; end + `INST_FPU_ADD: begin core_select = FPU_FMA; end + `INST_FPU_SUB: begin core_select = FPU_FMA; do_sub = 1; end + `INST_FPU_MUL: begin core_select = FPU_FMA; do_neg = 1; end + `INST_FPU_MADD: begin core_select = FPU_FMA; do_madd = 1; end + `INST_FPU_MSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; end + `INST_FPU_NMADD: begin core_select = FPU_FMA; do_madd = 1; do_neg = 1; end + `INST_FPU_NMSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; do_neg = 1; end + `INST_FPU_DIV: begin core_select = FPU_DIV; end + `INST_FPU_SQRT: begin core_select = FPU_SQRT; end + `INST_FPU_CVTWS: begin core_select = FPU_CVT; is_signed = 1; end + `INST_FPU_CVTWUS: begin core_select = FPU_CVT; end + `INST_FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; is_signed = 1; end + `INST_FPU_CVTSWU: begin core_select = FPU_CVT; is_itof = 1; end default: begin core_select = FPU_NCP; end endcase end diff --git a/hw/rtl/fp_cores/VX_fpu_fpnew.v b/hw/rtl/fp_cores/VX_fpu_fpnew.v index 3a8a8106..57a73bff 100644 --- a/hw/rtl/fp_cores/VX_fpu_fpnew.v +++ b/hw/rtl/fp_cores/VX_fpu_fpnew.v @@ -19,8 +19,8 @@ module VX_fpu_fpnew input wire [TAGW-1:0] tag_in, - input wire [`FPU_BITS-1:0] op_type, - input wire [`MOD_BITS-1:0] frm, + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_MOD_BITS-1:0] frm, input wire [`NUM_THREADS-1:0][31:0] dataa, input wire [`NUM_THREADS-1:0][31:0] datab, @@ -81,7 +81,7 @@ module VX_fpu_fpnew fpnew_pkg::status_t [`NUM_THREADS-1:0] fpu_status; reg [FOP_BITS-1:0] fpu_op; - reg [`FRM_BITS-1:0] fpu_rnd; + reg [`INST_FRM_BITS-1:0] fpu_rnd; reg fpu_op_mod; reg fpu_has_fflags, fpu_has_fflags_out; @@ -95,38 +95,38 @@ module VX_fpu_fpnew fpu_operands[2] = datac; case (op_type) - `FPU_ADD: begin + `INST_FPU_ADD: begin fpu_op = fpnew_pkg::ADD; fpu_operands[1] = dataa; fpu_operands[2] = datab; end - `FPU_SUB: begin + `INST_FPU_SUB: begin fpu_op = fpnew_pkg::ADD; fpu_operands[1] = dataa; fpu_operands[2] = datab; fpu_op_mod = 1; end - `FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end - `FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end - `FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end - `FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end - `FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end - `FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end - `FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end - `FPU_CVTWS: begin fpu_op = fpnew_pkg::F2I; end - `FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end - `FPU_CVTSW: begin fpu_op = fpnew_pkg::I2F; end - `FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end - `FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end - `FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end - `FPU_MISC: begin + `INST_FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end + `INST_FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end + `INST_FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end + `INST_FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end + `INST_FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end + `INST_FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end + `INST_FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end + `INST_FPU_CVTWS: begin fpu_op = fpnew_pkg::F2I; end + `INST_FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end + `INST_FPU_CVTSW: begin fpu_op = fpnew_pkg::I2F; end + `INST_FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end + `INST_FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end + `INST_FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end + `INST_FPU_MISC: begin case (frm) - 0: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RNE; fpu_has_fflags = 0; end - 1: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RTZ; fpu_has_fflags = 0; end - 2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RDN; fpu_has_fflags = 0; end - 3: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RNE; end - 4: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RTZ; end - default: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fpu_has_fflags = 0; end + 0: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RNE; fpu_has_fflags = 0; end + 1: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RTZ; fpu_has_fflags = 0; end + 2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RDN; fpu_has_fflags = 0; end + 3: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `INST_FRM_RNE; end + 4: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `INST_FRM_RTZ; end + default: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RUP; fpu_has_fflags = 0; end endcase end default:; diff --git a/hw/rtl/interfaces/VX_alu_req_if.v b/hw/rtl/interfaces/VX_alu_req_if.v index 2df383fb..8ae714af 100644 --- a/hw/rtl/interfaces/VX_alu_req_if.v +++ b/hw/rtl/interfaces/VX_alu_req_if.v @@ -10,8 +10,8 @@ interface VX_alu_req_if (); wire [`NUM_THREADS-1:0] tmask; wire [31:0] PC; wire [31:0] next_PC; - wire [`ALU_BITS-1:0] op_type; - wire [`MOD_BITS-1:0] op_mod; + wire [`INST_ALU_BITS-1:0] op_type; + wire [`INST_MOD_BITS-1:0] op_mod; wire use_PC; wire use_imm; wire [31:0] imm; diff --git a/hw/rtl/interfaces/VX_csr_req_if.v b/hw/rtl/interfaces/VX_csr_req_if.v index c02a67b4..3bcf635a 100644 --- a/hw/rtl/interfaces/VX_csr_req_if.v +++ b/hw/rtl/interfaces/VX_csr_req_if.v @@ -9,7 +9,7 @@ interface VX_csr_req_if (); wire [`NW_BITS-1:0] wid; wire [`NUM_THREADS-1:0] tmask; wire [31:0] PC; - wire [`CSR_BITS-1:0] op_type; + wire [`INST_CSR_BITS-1:0] op_type; wire [`CSR_ADDR_BITS-1:0] addr; wire [31:0] rs1_data; wire use_imm; diff --git a/hw/rtl/interfaces/VX_decode_if.v b/hw/rtl/interfaces/VX_decode_if.v index c8465911..e92f4592 100644 --- a/hw/rtl/interfaces/VX_decode_if.v +++ b/hw/rtl/interfaces/VX_decode_if.v @@ -10,8 +10,8 @@ interface VX_decode_if (); wire [`NUM_THREADS-1:0] tmask; wire [31:0] PC; wire [`EX_BITS-1:0] ex_type; - wire [`OP_BITS-1:0] op_type; - wire [`MOD_BITS-1:0] op_mod; + wire [`INST_OP_BITS-1:0] op_type; + wire [`INST_MOD_BITS-1:0] op_mod; wire wb; wire [`NR_BITS-1:0] rd; wire [`NR_BITS-1:0] rs1; diff --git a/hw/rtl/interfaces/VX_fpu_req_if.v b/hw/rtl/interfaces/VX_fpu_req_if.v index f03bddd4..92be96cf 100644 --- a/hw/rtl/interfaces/VX_fpu_req_if.v +++ b/hw/rtl/interfaces/VX_fpu_req_if.v @@ -9,8 +9,8 @@ interface VX_fpu_req_if (); wire [`NW_BITS-1:0] wid; wire [`NUM_THREADS-1:0] tmask; wire [31:0] PC; - wire [`FPU_BITS-1:0] op_type; - wire [`MOD_BITS-1:0] op_mod; + wire [`INST_FPU_BITS-1:0] op_type; + wire [`INST_MOD_BITS-1:0] op_mod; wire [`NUM_THREADS-1:0][31:0] rs1_data; wire [`NUM_THREADS-1:0][31:0] rs2_data; wire [`NUM_THREADS-1:0][31:0] rs3_data; diff --git a/hw/rtl/interfaces/VX_fpu_to_csr_if.v b/hw/rtl/interfaces/VX_fpu_to_csr_if.v index cd101820..3f27fa02 100644 --- a/hw/rtl/interfaces/VX_fpu_to_csr_if.v +++ b/hw/rtl/interfaces/VX_fpu_to_csr_if.v @@ -10,7 +10,7 @@ interface VX_fpu_to_csr_if (); fflags_t write_fflags; wire [`NW_BITS-1:0] read_wid; - wire [`FRM_BITS-1:0] read_frm; + wire [`INST_FRM_BITS-1:0] read_frm; endinterface diff --git a/hw/rtl/interfaces/VX_gpu_req_if.v b/hw/rtl/interfaces/VX_gpu_req_if.v index 1b49fda0..27ee1316 100644 --- a/hw/rtl/interfaces/VX_gpu_req_if.v +++ b/hw/rtl/interfaces/VX_gpu_req_if.v @@ -11,7 +11,7 @@ interface VX_gpu_req_if(); wire [`NUM_THREADS-1:0] tmask; wire [31:0] PC; wire [31:0] next_PC; - wire [`GPU_BITS-1:0] op_type; + wire [`INST_GPU_BITS-1:0] op_type; wire [`NT_BITS-1:0] tid; wire [`NUM_THREADS-1:0][31:0] rs1_data; wire [31:0] rs2_data; diff --git a/hw/rtl/interfaces/VX_ibuffer_if.v b/hw/rtl/interfaces/VX_ibuffer_if.v index 30f93026..d2277e48 100644 --- a/hw/rtl/interfaces/VX_ibuffer_if.v +++ b/hw/rtl/interfaces/VX_ibuffer_if.v @@ -11,8 +11,8 @@ interface VX_ibuffer_if (); wire [`NUM_THREADS-1:0] tmask; wire [31:0] PC; wire [`EX_BITS-1:0] ex_type; - wire [`OP_BITS-1:0] op_type; - wire [`MOD_BITS-1:0] op_mod; + wire [`INST_OP_BITS-1:0] op_type; + wire [`INST_MOD_BITS-1:0] op_mod; wire wb; wire [`NR_BITS-1:0] rd; wire [`NR_BITS-1:0] rs1; diff --git a/hw/rtl/interfaces/VX_lsu_req_if.v b/hw/rtl/interfaces/VX_lsu_req_if.v index c9797b0f..fed1f270 100644 --- a/hw/rtl/interfaces/VX_lsu_req_if.v +++ b/hw/rtl/interfaces/VX_lsu_req_if.v @@ -9,7 +9,7 @@ interface VX_lsu_req_if (); wire [`NW_BITS-1:0] wid; wire [`NUM_THREADS-1:0] tmask; wire [31:0] PC; - wire [`LSU_BITS-1:0] op_type; + wire [`INST_LSU_BITS-1:0] op_type; wire is_fence; wire [`NUM_THREADS-1:0][31:0] store_data; wire [`NUM_THREADS-1:0][31:0] base_addr; diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json index b5b4a11d..4af5231a 100644 --- a/hw/scripts/scope.json +++ b/hw/scripts/scope.json @@ -173,8 +173,8 @@ "issue_tmask":"`NUM_THREADS", "issue_pc": 32, "issue_ex_type":"`EX_BITS", - "issue_op_type":"`OP_BITS", - "issue_op_mod":"`MOD_BITS", + "issue_op_type":"`INST_OP_BITS", + "issue_op_mod":"`INST_MOD_BITS", "issue_wb": 1, "issue_rd":"`NR_BITS", "issue_rs1":"`NR_BITS",