From a8248b334c71e5226a265b2e1537498403e4d0b8 Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@yahoo.com>
Date: Fri, 16 Jul 2021 12:58:53 -0700
Subject: [PATCH] AVS wrapper optimization

---
 hw/rtl/afu/VX_avs_wrapper.v | 15 +++++++++------
 hw/rtl/afu/vortex_afu.sv    |  2 +-
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/hw/rtl/afu/VX_avs_wrapper.v b/hw/rtl/afu/VX_avs_wrapper.v
index 19123e83..328347bb 100644
--- a/hw/rtl/afu/VX_avs_wrapper.v
+++ b/hw/rtl/afu/VX_avs_wrapper.v
@@ -44,13 +44,14 @@ module VX_avs_wrapper #(
 );
 
     localparam BANK_ADDRW = `LOG2UP(NUM_BANKS);
+    localparam BUFFERED_OUTPUT = (NUM_BANKS > 2);
 
     // Requests handling
     
     wire [NUM_BANKS-1:0] avs_reqq_push, avs_reqq_pop, avs_reqq_ready;
+    wire [NUM_BANKS-1:0][REQ_TAG_WIDTH-1:0] avs_reqq_tag_out;
     wire [NUM_BANKS-1:0] req_queue_going_full;
     wire [NUM_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size;
-    wire [NUM_BANKS-1:0][REQ_TAG_WIDTH-1:0] avs_reqq_data_out;
     wire [BANK_ADDRW-1:0] req_bank_sel;
 
     if (NUM_BANKS >= 2) begin
@@ -80,14 +81,15 @@ module VX_avs_wrapper #(
         
         VX_fifo_queue #(
             .DATAW (REQ_TAG_WIDTH),
-            .SIZE  (RD_QUEUE_SIZE)
+            .SIZE  (RD_QUEUE_SIZE),
+            .BUFFERED (!BUFFERED_OUTPUT)
         ) rd_req_queue (
             .clk      (clk),
             .reset    (reset),
             .push     (avs_reqq_push[i]),        
             .pop      (avs_reqq_pop[i]),
             .data_in  (mem_req_tag),
-            .data_out (avs_reqq_data_out[i]),
+            .data_out (avs_reqq_tag_out[i]),
             `UNUSED_PIN (empty),
             `UNUSED_PIN (full),
             `UNUSED_PIN (alm_empty),
@@ -123,7 +125,8 @@ module VX_avs_wrapper #(
     for (genvar i = 0; i < NUM_BANKS; i++) begin
         VX_fifo_queue #(
             .DATAW (AVS_DATA_WIDTH),
-            .SIZE  (RD_QUEUE_SIZE)
+            .SIZE  (RD_QUEUE_SIZE),
+            .BUFFERED (!BUFFERED_OUTPUT)
         ) rd_rsp_queue (
             .clk      (clk),
             .reset    (reset),
@@ -141,14 +144,14 @@ module VX_avs_wrapper #(
     
     for (genvar i = 0; i < NUM_BANKS; i++) begin
         assign rsp_arb_valid_in[i] = !avs_rspq_empty[i];
-        assign rsp_arb_data_in[i]  = {avs_rspq_data_out[i], avs_reqq_data_out[i]};
+        assign rsp_arb_data_in[i]  = {avs_rspq_data_out[i], avs_reqq_tag_out[i]};
         assign avs_reqq_pop[i]     = rsp_arb_valid_in[i] && rsp_arb_ready_in[i];
     end
 
     VX_stream_arbiter #(
         .NUM_REQS (NUM_BANKS),
         .DATAW    (AVS_DATA_WIDTH + REQ_TAG_WIDTH),
-        .BUFFERED (NUM_BANKS > 2)
+        .BUFFERED (BUFFERED_OUTPUT)
     ) rsp_arb (
         .clk       (clk),
         .reset     (reset),
diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv
index 32ee0d94..7b828923 100644
--- a/hw/rtl/afu/vortex_afu.sv
+++ b/hw/rtl/afu/vortex_afu.sv
@@ -47,7 +47,7 @@ localparam CCI_LINE_WIDTH     = $bits(t_ccip_clData);
 localparam CCI_LINE_SIZE      = CCI_LINE_WIDTH / 8;
 localparam CCI_ADDR_WIDTH     = 32 - $clog2(CCI_LINE_SIZE);
 
-localparam AVS_RD_QUEUE_SIZE  = 16;
+localparam AVS_RD_QUEUE_SIZE  = 4;
 localparam AVS_REQ_TAGW_VX    = `MAX(`VX_MEM_TAG_WIDTH, `VX_MEM_TAG_WIDTH + $clog2(LMEM_LINE_WIDTH) - $clog2(`VX_MEM_LINE_WIDTH));
 localparam AVS_REQ_TAGW_CCI   = `MAX(CCI_ADDR_WIDTH, CCI_ADDR_WIDTH + $clog2(LMEM_LINE_WIDTH) - $clog2(CCI_LINE_WIDTH));
 localparam AVS_REQ_TAGW       = `MAX(AVS_REQ_TAGW_VX, AVS_REQ_TAGW_CCI);