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cache optimization - moved read requests to stage1 and eliminating stage3

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Blaise Tine
2020-12-31 07:40:58 -08:00
parent 9f128085d5
commit abe32ed553
16 changed files with 301 additions and 355 deletions
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driver/common/vx_utils.cpp
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@@ -292,7 +292,7 @@ extern int vx_dump_perf(vx_device_h device, FILE* stream) {
int avg_dram_lat = (int)(double(dram_lat_per_core) / double(dram_reads_per_core));
int dram_utilization = (int)((1.0 - (double(dram_reads_per_core + dram_writes_per_core) / double(dram_reads_per_core + dram_writes_per_core + dram_stalls_per_core))) * 100);
if (num_cores > 1) fprintf(stream, "PERF: core%d: dram requests=%ld (reads=%ld, writes=%ld)\n", core_id, (dram_reads_per_core + dram_writes_per_core), dram_reads_per_core, dram_writes_per_core);
if (num_cores > 1) fprintf(stream, "PERF: core%d: dram stalls=%d (utilization=%d%%)\n", core_id, dram_stalls_per_core, dram_utilization);
if (num_cores > 1) fprintf(stream, "PERF: core%d: dram stalls=%ld (utilization=%d%%)\n", core_id, dram_stalls_per_core, dram_utilization);
if (num_cores > 1) fprintf(stream, "PERF: core%d: average dram latency=%d cycles\n", core_id, avg_dram_lat);
dram_reads += dram_reads_per_core;
dram_writes += dram_writes_per_core;