cache optimization - moved read requests to stage1 and eliminating stage3
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@@ -172,7 +172,7 @@ module VX_lsu_unit #(
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assign dcache_req_if.data = req_data;
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`ifdef DBG_CACHE_REQ_INFO
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assign dcache_req_if.tag = {`NUM_THREADS{{req_pc, req_rd, req_wid, req_tag}}};
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assign dcache_req_if.tag = {`NUM_THREADS{{req_pc, req_wid, req_tag}}};
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`else
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assign dcache_req_if.tag = {`NUM_THREADS{req_tag}};
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`endif
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