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Changed all instances of DWord to XWord and DWordI to XWordI. Added XLEN parameterization to the simx Makefile

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This commit is contained in:
Santosh Srivatsan
2022-01-22 13:47:44 -05:00
parent 91c22a2592
commit ad92c09f5b
10 changed files with 77 additions and 60 deletions
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72
sim/simx/execute.cpp
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@@ -16,7 +16,7 @@
using namespace vortex;
static bool HasDivergentThreads(const ThreadMask &thread_mask,
const std::vector<std::vector<DWord>> &reg_file,
const std::vector<std::vector<XWord>> &reg_file,
unsigned reg) {
bool cond;
size_t thread_idx = 0;
@@ -52,7 +52,7 @@ inline void update_fcrs(uint32_t fflags, Core* core, uint32_t tid, uint32_t wid)
void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
assert(tmask_.any());
DWord nextPC = PC_ + core_->arch().wsize();
XWord nextPC = PC_ + core_->arch().wsize();
Word func2 = instr.getFunc2();
Word func3 = instr.getFunc3();
@@ -64,13 +64,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
int rsrc0 = instr.getRSrc(0);
int rsrc1 = instr.getRSrc(1);
int rsrc2 = instr.getRSrc(2);
DWord immsrc = instr.getImm();
XWord immsrc = instr.getImm();
Word vmask = instr.getVmask();
int num_threads = core_->arch().num_threads();
std::vector<DWord[3]> rsdata(num_threads);
std::vector<DWord> rddata(num_threads);
std::vector<XWord[3]> rsdata(num_threads);
std::vector<XWord> rddata(num_threads);
int num_rsrcs = instr.getNRSrc();
if (num_rsrcs) {
@@ -149,7 +149,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
switch (func3) {
case 0:
// RV32M: MUL
rddata[t] = ((DWordI)rsdata[t][0]) * ((DWordI)rsdata[t][1]);
rddata[t] = ((XWordI)rsdata[t][0]) * ((XWordI)rsdata[t][1]);
trace->alu.type = AluType::IMUL;
break;
case 1: {
@@ -175,11 +175,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
} break;
case 4: {
// RV32M: DIV
DWordI dividen = rsdata[t][0];
DWordI divisor = rsdata[t][1];
XWordI dividen = rsdata[t][0];
XWordI divisor = rsdata[t][1];
if (divisor == 0) {
rddata[t] = -1;
} else if (dividen == DWordI(0x8000000000000000) && divisor == DWordI(0xffffffffffffffff)) {
} else if (dividen == XWordI(0x8000000000000000) && divisor == XWordI(0xffffffffffffffff)) {
rddata[t] = dividen;
} else {
rddata[t] = dividen / divisor;
@@ -188,8 +188,8 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
} break;
case 5: {
// RV32M: DIVU
DWord dividen = rsdata[t][0];
DWord divisor = rsdata[t][1];
XWord dividen = rsdata[t][0];
XWord divisor = rsdata[t][1];
if (divisor == 0) {
rddata[t] = -1;
} else {
@@ -199,11 +199,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
} break;
case 6: {
// RV32M: REM
DWordI dividen = rsdata[t][0];
DWordI divisor = rsdata[t][1];
XWordI dividen = rsdata[t][0];
XWordI divisor = rsdata[t][1];
if (rsdata[t][1] == 0) {
rddata[t] = dividen;
} else if (dividen == DWordI(0x8000000000000000) && divisor == DWordI(0xffffffffffffffff)) {
} else if (dividen == XWordI(0x8000000000000000) && divisor == XWordI(0xffffffffffffffff)) {
rddata[t] = 0;
} else {
rddata[t] = dividen % divisor;
@@ -212,8 +212,8 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
} break;
case 7: {
// RV32M: REMU
DWord dividen = rsdata[t][0];
DWord divisor = rsdata[t][1];
XWord dividen = rsdata[t][0];
XWord divisor = rsdata[t][1];
if (rsdata[t][1] == 0) {
rddata[t] = dividen;
} else {
@@ -241,11 +241,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
break;
case 2:
// RV32I: LT
rddata[t] = (DWordI(rsdata[t][0]) < DWordI(rsdata[t][1]));
rddata[t] = (XWordI(rsdata[t][0]) < XWordI(rsdata[t][1]));
break;
case 3:
// RV32I: LTU
rddata[t] = (DWord(rsdata[t][0]) < DWord(rsdata[t][1]));
rddata[t] = (XWord(rsdata[t][0]) < XWord(rsdata[t][1]));
break;
case 4:
// RV32I: XOR
@@ -254,10 +254,10 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
case 5:
if (func7) {
// RV32I: SRA
rddata[t] = DWordI(rsdata[t][0]) >> DWordI(rsdata[t][1]);
rddata[t] = XWordI(rsdata[t][0]) >> XWordI(rsdata[t][1]);
} else {
// RV32I: SHR
rddata[t] = DWord(rsdata[t][0]) >> DWord(rsdata[t][1]);
rddata[t] = XWord(rsdata[t][0]) >> XWord(rsdata[t][1]);
}
break;
case 6:
@@ -293,7 +293,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
break;
case 2:
// RV32I: SLTI
rddata[t] = (DWordI(rsdata[t][0]) < DWordI(immsrc));
rddata[t] = (XWordI(rsdata[t][0]) < XWordI(immsrc));
break;
case 3: {
// RV32I: SLTIU
@@ -306,11 +306,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
case 5:
if (func7) {
// RV32I: SRAI
DWord result = DWordI(rsdata[t][0]) >> immsrc;
XWord result = XWordI(rsdata[t][0]) >> immsrc;
rddata[t] = result;
} else {
// RV32I: SRLI
DWord result = rsdata[t][0] >> immsrc;
XWord result = rsdata[t][0] >> immsrc;
rddata[t] = result;
}
break;
@@ -439,11 +439,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
case 5:
if (func7) {
// RV64I: SRAIW
DWord result = sext64((WordI)rsdata[t][0] >> (WordI)immsrc, 32);
XWord result = sext64((WordI)rsdata[t][0] >> (WordI)immsrc, 32);
rddata[t] = result;
} else {
// RV64I: SRLIW
DWord result = sext64((Word)rsdata[t][0] >> (Word)immsrc, 32);
XWord result = sext64((Word)rsdata[t][0] >> (Word)immsrc, 32);
rddata[t] = result;
}
break;
@@ -476,25 +476,25 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
break;
case 4:
// RV32I: BLT
if (DWordI(rsdata[t][0]) < DWordI(rsdata[t][1])) {
if (XWordI(rsdata[t][0]) < XWordI(rsdata[t][1])) {
nextPC = PC_ + immsrc;
}
break;
case 5:
// RV32I: BGE
if (DWordI(rsdata[t][0]) >= DWordI(rsdata[t][1])) {
if (XWordI(rsdata[t][0]) >= XWordI(rsdata[t][1])) {
nextPC = PC_ + immsrc;
}
break;
case 6:
// RV32I: BLTU
if (DWord(rsdata[t][0]) < DWord(rsdata[t][1])) {
if (XWord(rsdata[t][0]) < XWord(rsdata[t][1])) {
nextPC = PC_ + immsrc;
}
break;
case 7:
// RV32I: BGEU
if (DWord(rsdata[t][0]) >= DWord(rsdata[t][1])) {
if (XWord(rsdata[t][0]) >= XWord(rsdata[t][1])) {
nextPC = PC_ + immsrc;
}
break;
@@ -543,9 +543,9 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
for (int t = 0; t < num_threads; ++t) {
if (!tmask_.test(t))
continue;
DWord mem_addr = ((rsdata[t][0] + immsrc) & 0xFFFFFFFFFFFFFFFC); // double word aligned
DWord shift_by = ((rsdata[t][0] + immsrc) & 0x00000003) * 8;
DWord data_read = core_->dcache_read(mem_addr, 8);
XWord mem_addr = ((rsdata[t][0] + immsrc) & 0xFFFFFFFFFFFFFFFC); // double word aligned
XWord shift_by = ((rsdata[t][0] + immsrc) & 0x00000003) * 8;
XWord data_read = core_->dcache_read(mem_addr, 8);
trace->mem_addrs.at(t).push_back({mem_addr, 8});
DP(4, "LOAD MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << data_read);
switch (func3) {
@@ -567,15 +567,15 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
break;
case 4:
// RV32I: LBU
rddata[t] = DWord((data_read >> shift_by) & 0xFF);
rddata[t] = XWord((data_read >> shift_by) & 0xFF);
break;
case 5:
// RV32I: LHU
rddata[t] = DWord((data_read >> shift_by) & 0xFFFF);
rddata[t] = XWord((data_read >> shift_by) & 0xFFFF);
break;
case 6:
// RV64I: LWU
rddata[t] = DWord((data_read >> shift_by) & 0xFFFFFFFF);
rddata[t] = XWord((data_read >> shift_by) & 0xFFFFFFFF);
break;
default:
std::abort();
@@ -616,7 +616,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
for (int t = 0; t < num_threads; ++t) {
if (!tmask_.test(t))
continue;
DWord mem_addr = rsdata[t][0] + immsrc;
XWord mem_addr = rsdata[t][0] + immsrc;
trace->mem_addrs.at(t).push_back({mem_addr, (1u << func3)});
DP(4, "STORE MEM: ADDRESS=0x" << std::hex << mem_addr);
switch (func3) {